JPS6177368A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS6177368A JPS6177368A JP19857084A JP19857084A JPS6177368A JP S6177368 A JPS6177368 A JP S6177368A JP 19857084 A JP19857084 A JP 19857084A JP 19857084 A JP19857084 A JP 19857084A JP S6177368 A JPS6177368 A JP S6177368A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ingaas
- inp
- electron density
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 125000005842 heteroatom Chemical group 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はInGaAs層を動作層とする電界効果型ト
ランジスタ(以降FETと記す)の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the structure of a field effect transistor (hereinafter referred to as FET) having an InGaAs layer as an active layer.
InP基板に格子整合するIn I−x Ga 、 A
s (x =0.47、以下単にInGaAsと記す)
は、電子移動度が室温でGaAsの約2倍と大きく、ま
た、オーミック接触を形成する際に接触抵抗が小さくな
るために、現在マイクロ波素子の主流となっているGa
Asを用いたショットキ接合型電界効果トランジスタ(
以下GaAs MES FETと記す)に比べて伝達コ
ンダクタンスを大きく、ソース抵抗(接触抵抗とチャネ
ル抵抗の和)を低減できることが期待され、GaAsM
ES FETを上回る高性能マイクロ波素子用の材料と
して注目されている。In I-x Ga, A lattice matched to InP substrate
s (x = 0.47, hereinafter simply referred to as InGaAs)
GaAs is currently the mainstream material for microwave devices because its electron mobility is approximately twice as high as that of GaAs at room temperature, and its contact resistance is low when forming ohmic contacts.
Schottky junction field effect transistor using As (
It is expected that the transfer conductance will be larger and the source resistance (sum of contact resistance and channel resistance) will be lower than that of GaAsM
It is attracting attention as a material for high-performance microwave devices that exceeds ES FETs.
しかしながら、InGaAsはバンドギャップが0.7
8eVで、GaAsに比べて小さいためにInGaAs
表面上にショットキ接合を形成しようとしても逆方向の
リーク電流が大きく流れ、このためInGaAsを用い
たショットキ接合型のFETを構成することができなか
った。この問題を解決するためにゲートをショットキ接
合型からMIS(金属−絶縁膜一半導体)型にする、も
しくはpn接合型にするなどの方法が試みられているが
、前者では絶縁膜−半導体界面に生じる界面準位の影響
により伝達コンダクタンスが小さい。また、後者ではゲ
ートリーク電流の低減が不充分である等の理由により、
いずれの方法によってもゲートリーク電流が小さく良好
なマイクロ波性能を示す素子は得られていない。However, InGaAs has a bandgap of 0.7
8 eV, which is smaller than GaAs, so InGaAs
Even when attempting to form a Schottky junction on the surface, a large leakage current flows in the reverse direction, making it impossible to construct a Schottky junction FET using InGaAs. To solve this problem, attempts have been made to change the gate from a Schottky junction type to an MIS (metal-insulator-semiconductor) type, or to a pn junction type. The transfer conductance is small due to the effect of the generated interface states. In addition, due to reasons such as insufficient reduction of gate leakage current in the latter,
No matter which method is used, an element with small gate leakage current and good microwave performance has not been obtained.
さらに最近になって、GaAlAs/GaAsヘテロ接
合の界面に蓄積する電子の移動度がバルクGaAs結晶
の移動度に比べて飛躍的に増大するいわゆるr変調ドー
ピング」なる手法が開発され、この原理をInGaAs
/InP系にも適用し移動度の増加によるマイクロ波性
能の向上と、ゲート部のリーク電流の低減を図ることが
検討されている。以下に従来例としてInGaAs/I
nP系で変調ドーピングを利用した素子について述べる
。More recently, a technique called "r-modulation doping" has been developed, in which the mobility of electrons accumulated at the interface of the GaAlAs/GaAs heterojunction is dramatically increased compared to that of the bulk GaAs crystal, and this principle has been applied to InGaAs.
/InP systems are also being considered to improve microwave performance by increasing mobility and reduce leakage current at the gate. Below, as a conventional example, InGaAs/I
An nP-based device using modulation doping will be described.
第3図はInGaAs/InP接合を用いた変調ドープ
FETの断面図、第3図は熱平衡状態におけるゲート部
の深さ方向のエネルギバンド図を示したものである。両
図において、(101)は半絶縁性InP基板、(10
2)はアンドープInGaAs層(n !lXl0”C
m−’)、(103)はn”InP層(n=5 X 1
0”cm−3)、(104g)は前記n”InP層(1
03)とショットキ接合をなすゲート電極、(104s
)と(104d)は前記n”InP層(103)とオー
ミック接触をなす夫々ソース電極とドレイン電極である
。FIG. 3 is a cross-sectional view of a modulation doped FET using an InGaAs/InP junction, and FIG. 3 shows an energy band diagram in the depth direction of the gate portion in a thermal equilibrium state. In both figures, (101) is a semi-insulating InP substrate, (10
2) is an undoped InGaAs layer (n!lXl0”C
m-'), (103) is an n''InP layer (n=5 x 1
0"cm-3), (104g) is the n"InP layer (1
03) and a gate electrode forming a Schottky junction, (104s
) and (104d) are a source electrode and a drain electrode, respectively, which make ohmic contact with the n''InP layer (103).
InGaAs/TnPの接合においては、InGaAs
の方がInPに比べて電子親和力が約0,2eV大きい
ために、両材料の電子密度が上述の値、即ちInP層の
電子密度がInGaAs層の電子密度に比べて充分高い
場合には第4図の接合界面に示すように電子蓄積層(1
05)が形成される。この蓄積電子は、イオン化不純物
散乱体として働< InP中のドナーイオンとは空間的
に分離されているために、電子蓄積層(105)中を、
第4図で紙面に垂直な方向(第3図では左から右へ向か
う方向)に走行する電子の移動度は室温で約7500〜
80000m2/v−5ecにも達する。上記第3図に
示した変調ドープFETにおいても以下のような問題点
がある。In the InGaAs/TnP junction, InGaAs
Since the electron affinity of InP is about 0.2 eV larger than that of InP, if the electron density of both materials is the above-mentioned value, that is, the electron density of the InP layer is sufficiently higher than that of the InGaAs layer, the fourth As shown at the bonding interface in the figure, the electron storage layer (1
05) is formed. These accumulated electrons act as ionized impurity scatterers and are spatially separated from the donor ions in InP, so they move through the electron storage layer (105).
In Figure 4, the mobility of electrons traveling in the direction perpendicular to the paper (from left to right in Figure 3) is approximately 7500~ at room temperature.
It reaches 80,000m2/v-5ec. The modulation doped FET shown in FIG. 3 also has the following problems.
(i ) n+InP層(103)上にショットキ接
合を形成しゲートリーク電流の低減を図ろうとしてもこ
のInP層の電子密度が高いので、リーク電流の低減は
容易ではなく、この改善効果は小さい。(i) Even if an attempt is made to reduce the gate leakage current by forming a Schottky junction on the n+InP layer (103), since the electron density of this InP layer is high, it is not easy to reduce the leakage current, and the improvement effect is small.
(it ) InGaAs/InP系では伝導体下端
の不連続の度合(第4図にΔEcで示す)が、Ga 1
−xAl xAslGaAs系(x =0.3の場合9
に比べて小さいために、蓄積層(105)に溜り込む電
子面密度はせいぜい5×10”cm−2で、例えばリセ
ス構造GaAs MES FETの能動層の面密度5
X 10”cm−2に比べると約1桁も小さい。このた
め、素子のチャネル抵抗(ソース抵抗)が増加し、マイ
クロ波性能が向上しない。(it) In the InGaAs/InP system, the degree of discontinuity at the lower end of the conductor (indicated by ΔEc in Figure 4) is Ga 1
-xAl xAslGaAs system (9 for x = 0.3
Therefore, the surface density of electrons accumulated in the storage layer (105) is at most 5 x 10"cm-2, for example, the surface density of the active layer of a recessed GaAs MES FET is 5.
This is about an order of magnitude smaller than X 10"cm-2. Therefore, the channel resistance (source resistance) of the device increases, and the microwave performance does not improve.
(市)変調ドープ構造を形成するためには、即ち第4図
に示すようなバンド構造となるためには。(City) In order to form a modulation doped structure, that is, to form a band structure as shown in FIG.
通常InGaAs層の電子密度を1×1015CI11
−3以下にする必要がある。しかしながらInGaAs
のような混晶において、結晶中の不純物量を低減させる
ことは容易ではなく、結晶成長上困難な点が多い。Normally, the electron density of InGaAs layer is 1×1015CI11
Must be -3 or less. However, InGaAs
In such mixed crystals, it is not easy to reduce the amount of impurities in the crystal, and there are many difficulties in crystal growth.
以上に述べたように、第3図に示した変調ドープFET
においては、当初意図したゲートリーク電流およびソー
ス抵抗の低減という目的を達成するにはその改善効果は
不充分であり、ためにマイクロ波も従来のGaAs M
ES FETに比べて劣っており、InGaAsが高移
動度であるという有用性を生かすに到っていない。As mentioned above, the modulation doped FET shown in FIG.
However, the improvement effect was insufficient to achieve the originally intended purpose of reducing gate leakage current and source resistance, and therefore microwaves were
It is inferior to ES FET, and does not take advantage of the high mobility of InGaAs.
この発明は上記の問題点を解消するためになされたもの
であって、ゲートリーク電流が小さく、ソース抵抗の小
さい良好なマイクロ波特性を有するInGaAs層を能
動層とするFETを提供する。The present invention has been made to solve the above-mentioned problems, and provides an FET having an InGaAs layer as an active layer, which has low gate leakage current, low source resistance, and good microwave characteristics.
発明者は従来技術の問題点につき検討を重ねた結果、I
nGaAsの高移動度性を生かし、かつ、ゲートリーク
電流の低減をはかるには、ゲート部をInGaAs/I
nPヘテロ接合でIn型るとともに、InGaAs層の
電子密度を高く、InP層の電子密度を十分に低くする
ことによりInGaAs層そのものを主ため電流通路と
して動作せしめればよいことを見出し本発明を構成した
。−
すなわち、この発明にかかるFETは、半絶縁性InP
基板と、この基板上に形成されこの基板と格子整合する
InGaAs層と、このInGaAs層上に被着された
InP層と、このInP層上に設けられこれとショット
キ接合をなすゲート電極と、前記InP層もしくはIn
GaAs層上に前記ゲート電極を挟んでオーミック接触
をなすソース電極およびドレイン電極を備えた電界効果
型トランシタにおいて、InGaAs層が高電子密度に
、かつInP層が低電子密度に夫々設けられ、InGa
As層を主たる電流通路とする構造上の特徴を有するも
のである。As a result of repeated consideration of the problems of the prior art, the inventor found that I
In order to take advantage of the high mobility of nGaAs and to reduce gate leakage current, the gate part is made of InGaAs/I.
In addition to forming an In-type nP heterojunction, the inventors discovered that by making the electron density of the InGaAs layer high and the electron density of the InP layer sufficiently low, the InGaAs layer itself can be operated mainly as a current path, and the present invention is constructed. did. - That is, the FET according to the present invention is made of semi-insulating InP
a substrate, an InGaAs layer formed on the substrate and lattice matched with the substrate, an InP layer deposited on the InGaAs layer, a gate electrode provided on the InP layer and forming a Schottky junction therewith; InP layer or In
In a field effect transistor having a source electrode and a drain electrode that are in ohmic contact with the gate electrode sandwiched between them on a GaAs layer, an InGaAs layer is provided with a high electron density and an InP layer is provided with a low electron density.
It has a structural feature in which the As layer is the main current path.
以下、この発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図にこの発明に係わる素子の断面構造を、第2図に
熱平衡状態におけるゲート部の深さ方向のエネルギーバ
ンド図を示す。面図において、(101)は半絶縁性I
nP基板、(2)は上記InP基板(101)と格子整
合するInGaAs層でその電子密度は2×10”cm
−”、厚さは0.08μmである。また、(3)はIn
P層でその電子密度はI X 10” cm−”、厚さ
は0.1μmである。さらに、(4g)は上記InP層
(2)とショットキ接合をなすゲート電極で金で形成さ
れている。次に(4s)および(4d)は夫々ソース電
極およびドレイン電極で、前記InGaAs層(2)と
オーミック接触をなし、AuGe/Niで形成されてい
る。かかる構造の素子は通常のエピタキシャル成長技術
、素子・電極加工技術によって容易に製造することがで
きる。FIG. 1 shows a cross-sectional structure of an element according to the present invention, and FIG. 2 shows an energy band diagram in the depth direction of a gate portion in a state of thermal equilibrium. In the top view, (101) is semi-insulating I
The nP substrate (2) is an InGaAs layer lattice-matched to the above InP substrate (101), and its electron density is 2 x 10"cm.
-”, the thickness is 0.08 μm. Also, (3) is In
The P layer has an electron density of I x 10"cm-" and a thickness of 0.1 μm. Further, (4g) is a gate electrode forming a Schottky junction with the InP layer (2) and is made of gold. Next, (4s) and (4d) are a source electrode and a drain electrode, respectively, which make ohmic contact with the InGaAs layer (2) and are made of AuGe/Ni. Elements with such a structure can be easily manufactured using ordinary epitaxial growth techniques and element/electrode processing techniques.
叙上のこの発明の素子と従来例で述べた素子との相違は
第2図と第4図を比較すれば明瞭に判別される。すなわ
ち、第3図の従来例の素子では電子走行領域としてIn
GaAs層 inP界面に蓄積する電子蓄積層(第4図
(105))を利用しているが、この発明ではInGa
As層(2)そのものを電子走行領域(5)(第1図、
第2図)として用いている。The difference between the device of the present invention described above and the device described in the conventional example can be clearly distinguished by comparing FIGS. 2 and 4. That is, in the conventional device shown in FIG.
GaAs layer Although the electron storage layer (Fig. 4 (105)) that accumulates at the inP interface is used, in this invention
The As layer (2) itself is used as the electron transit region (5) (Fig. 1,
Figure 2).
第1図に示す素子の動作原理は現行のGaAs MES
FETと比べると、ゲート部がInGaAs/InPの
へテロ接合になっていることが異なるのみで基本的には
同じである。The operating principle of the device shown in Figure 1 is based on the current GaAs MES.
Compared to FETs, they are basically the same except that the gate part is an InGaAs/InP heterojunction.
この発明においては、InGaAs層の電子密度を高く
、InP層の電子密度を低くし、InGaAs層を主た
る電流通路とすることをその特徴としているが、各層の
電子密度をこのように選ぶエネルギーパンド図が第2図
に示す如くなるのは次の理由による。In this invention, the electron density of the InGaAs layer is high, the electron density of the InP layer is low, and the InGaAs layer is used as the main current path. The reason why is as shown in FIG. 2 is as follows.
一般にペテロ接合において第2図に示すバンド構造とな
るための必要条件は
(イ) χ 〉χ (ただしχは電子親和力)
InGaAs InP
(ロ) χInGaAs ” EgInGaAs <
χInP ” EgInP(ただしEgはバンドギャッ
プ)
(ハ) φ 〈φ (ただしφは仕事関数)I
nGaAs InP
で与えられる。InGaAs、 InPの各々のχおよ
びEgの値を次の第1表に掲げる。In general, the necessary conditions for a Peter junction to have the band structure shown in Figure 2 are (a) χ 〉χ (where χ is electron affinity)
InGaAs InP (b) χInGaAs ” EgInGaAs <
χInP ” EgInP (however, Eg is the band gap) (c) φ 〈φ (however, φ is the work function) I
It is given by nGaAs InP. The values of χ and Eg for InGaAs and InP are listed in Table 1 below.
第1表
上表の数値を(イ)、(ロ)の条件に代入すると、In
GaAs/InP系ではこれらの条件は満足されている
。Substituting the values in the upper table of Table 1 into the conditions (a) and (b), In
These conditions are satisfied in the GaAs/InP system.
残る(ハ)の条件についてはφは電子密度により変わる
が、上述した実施例の電子密度におけるTnGaAs、
InPによりφは各々4.59eV、 4.6]eVで
あり、(ハ)の条件も満足され、従って第2図に示す如
きバンド構造となる。Regarding the remaining condition (c), φ changes depending on the electron density, but TnGaAs at the electron density of the above example,
Due to InP, φ is 4.59 eV and 4.6] eV, respectively, and the condition (c) is also satisfied, resulting in a band structure as shown in FIG.
この発明に係わる素子を従来例による素子と比較すると
次の利点が認められる。When the device according to the present invention is compared with the conventional device, the following advantages are recognized.
(a)この発明に係わる素子においては、ショットキ接
合をなすInP層の電子密度が低いため、ゲートリーク
電流の極めて小さい良好な接合が得られる。(a) In the device according to the present invention, since the electron density of the InP layer forming the Schottky junction is low, a good junction with extremely low gate leakage current can be obtained.
また、ゲート部の容量がInP層とInGaAs層各層
の空乏層容量の直列接続となるため、ゲート容量が格段
に減少し素子性能が向上する。Furthermore, since the capacitance of the gate portion is a series connection of the depletion layer capacitances of the InP layer and the InGaAs layer, the gate capacitance is significantly reduced and the device performance is improved.
(b)電流通路であるInGaAs層の電子密度を高く
しているので、ソース電極直下の電子密度に換算してI
X 1011012C以上となり、このためチャネル
抵抗(ソース抵抗)が低減する。また、■託aAs層を
必ずしも高純度(低不純物濃度)にする必要がないので
、エピタキシャル成長上の困難を低減できる。(b) Since the electron density of the InGaAs layer, which is the current path, is high, the electron density directly under the source electrode is
X 1011012C or more, which reduces the channel resistance (source resistance). In addition, it is not necessary to make the aAs layer highly pure (low impurity concentration), so difficulties in epitaxial growth can be reduced.
なお、この発明に係わる素子においては、電子密度が高
密度であるInGaAs層を能動層として用いるために
第3図に示す従来例で述べた素子に比べてイオン化不純
物散乱の影響を強く受けてきまり、「変調ドーピング」
構造に比べて移動度が大きく低下するということはなく
、例えば電子密度2X10”c「3のInGaAs層で
7000cII12/v−8ec以上の移動度が得られ
る。In addition, in the device according to the present invention, since an InGaAs layer with a high electron density is used as an active layer, it is more affected by ionized impurity scattering than the device described in the conventional example shown in FIG. , "modulation doping"
The mobility does not decrease significantly compared to the structure, and for example, an InGaAs layer with an electron density of 2×10″c′3 can obtain a mobility of 7000cII12/v−8ec or more.
以上述べたようにこの発明によれば、InGaAsの高
移動度性を生かしながらゲートリーク電流が小さく、ソ
ース抵抗の小さい良好なマイクロ波性能を示すInGa
As層を能動層として用いるFETを提供することがで
きる。As described above, according to the present invention, InGaAs exhibits good microwave performance with low gate leakage current and low source resistance while taking advantage of the high mobility of InGaAs.
A FET using an As layer as an active layer can be provided.
なお、上記実施例においてはInGaAs層の電子密度
を2×1017CI11−3、InP層の電子密度をI
XIOI4cm−”とした場合について述べたが、この
発明はこれらの数値に何ら限定されることなく、高電子
密度のInGaAs層を主たる電流通路として用い、I
nP層を低密度とする場合に広く適用することができ、
発明者等の実施によると、InGaAs層の電子密度を
約I X 10”cm−”以上、InP層を約I X
10I10l5”以下とした場合にゲートリーク電流お
よびソース抵抗の低減というこの発明の効果が得られる
。また。In the above example, the electron density of the InGaAs layer is 2×1017CI11-3, and the electron density of the InP layer is I
Although the case where the
It can be widely applied when the nP layer has a low density,
According to the inventors' experiments, the electron density of the InGaAs layer is about I x 10"cm-" or more, and the electron density of the InP layer is about I x
When the value is 10I1015" or less, the effect of the present invention of reducing gate leakage current and source resistance can be obtained. Also.
実施例ではソースおよびドレインのオーミック接合をI
nGaAs層上に形成しているが、これに限定されるも
のではなく、InP層上に形成してもこの発明の利点は
そのまま適用できる。In the example, the ohmic junction of the source and drain is I
Although it is formed on the nGaAs layer, it is not limited thereto, and even if it is formed on the InP layer, the advantages of the present invention can be applied as is.
第1図はこの発明によるFETの断面図、第2図は第1
図に示す素子のゲート部深さ方向のエネルギーバンド図
、第3図は従来のFETの断面図、第4図は第3図に示
す素子のゲート部深さ方向のエネルギーバンド図である
。FIG. 1 is a sectional view of an FET according to the present invention, and FIG.
FIG. 3 is a sectional view of a conventional FET, and FIG. 4 is an energy band diagram of the device shown in FIG. 3 in the depth direction of the gate portion.
Claims (1)
板と格子整合するInGaAs層と、このInGaAs
層上に被着されたInP層と、このInP層上に設けら
れこれとショットキ接合をなすゲート電極と、前記In
P層もしくはInGaAs層上に前記ゲート電極を挟ん
でオーミック接触をなすソース電極およびドレイン電極
を備えた電界効果型トランジスタにおいて、InGaA
s層が高電子密度に、かつInP層が低電子密度に夫々
設けられ、InGaAs層を主たる電流通路とすること
を特徴とする電界効果型トランジスタ。A semi-insulating InP substrate, an InGaAs layer formed on this substrate and lattice matched to this substrate, and this InGaAs layer.
an InP layer deposited on the InP layer; a gate electrode provided on the InP layer and forming a Schottky junction therewith;
In a field effect transistor comprising a source electrode and a drain electrode that are in ohmic contact with the gate electrode sandwiched between them on a P layer or an InGaAs layer, an InGaAs
A field effect transistor characterized in that an S layer has a high electron density and an InP layer has a low electron density, and the InGaAs layer serves as a main current path.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19857084A JPS6177368A (en) | 1984-09-25 | 1984-09-25 | Field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19857084A JPS6177368A (en) | 1984-09-25 | 1984-09-25 | Field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6177368A true JPS6177368A (en) | 1986-04-19 |
Family
ID=16393377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19857084A Pending JPS6177368A (en) | 1984-09-25 | 1984-09-25 | Field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6177368A (en) |
-
1984
- 1984-09-25 JP JP19857084A patent/JPS6177368A/en active Pending
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