JPS6177325A - Pattern formation - Google Patents

Abstract

PURPOSE:To contrive to improve the MOS FET-manufacturing yield by enabling the formation of gates of T-type in cross-section with good accuracy in a small number of processes by a method wherein only a layer of resist film is formed on a substrate, exposed to light to a specific degree with charged beams, and developed; thereafter, a resist pattern with an enlarged space in the upper pat and narrowed space in the lower part, and the gate material is deposited. CONSTITUTION:A resist film 2 is produced by coating the substrate 1 with a resist 1, which is irradiated with hydrogen ions (H<+>) 3; successively, the resist film irradiated with H<+> 3 is irradiated over a narrower area. Then, the resist if exposed by this irradiation until reaching the substrate. Next, a resist pattern of cross-section shape is formed by development in the mixed solution of methylisobutylketone: isopropyl-alcohol=1:3, and a metallic layer 4 is deposited by evaporating aluminum over the whole surface as the gate-forming material. When the resist is removed by the lift-off method with the same developer, a gate 46 T-type in cross-section can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a pattern forming method, for example, in gate formation of an MO5 field effect transistor (MOS FET), in order to shorten the gate length and suppress an increase in gate resistance. The present invention relates to a method for forming the developed T-shaped cross-sectional gate using fewer steps than the conventional method.

[Conventional technology]

? In order to reduce the gate length of IOS PET and suppress the increase in gate resistance, research is underway on a technology to reduce resistance by forming the gate into a T-shaped cross section to reduce the gate length and increase the gate area. has been done.

This technique will be explained with reference to the sectional view of FIG. 3. First, as shown in FIG. 3 (al), a low-sensitivity resist is deposited on a substrate 31 to form a lower resist film 32.

Next, as shown in FIG. 3 (bl), the lower resist film 32
A high-sensitivity resist is deposited thereon to form an upper resist film 33.

Next, as shown in FIG. 3, the charged beam 34 (1
1 beam, ion beam, etc.).

Next, the upper resist film 33 is developed using a solution that develops only the high-sensitivity resist, thereby obtaining the pattern of the upper resist film shown in FIG. 3+d+.

Next, as shown in FIG. 3(e), the lower resist film 32 is patterned using a solution that develops only the low-sensitivity resist.

Next, as shown in FIG. 3 (fl), a gate material t135 is deposited, for example, by sputtering or by a sputtering method.

Finally, the resist was removed using the lift-off method, as shown in Figure 3 fgl.
A gate 35G shown in FIG. As shown in the figure, the gate 35G has a T-shaped cross section, the portion (gate length) in contact with the substrate 31 is narrow, and the gate has a sufficient area as a whole.

[Problems to be Solved by the Invention] In the conventional method for processing the above-described T-shaped cross-section gate, two layers of resists having different sensitivities are formed on a substrate. Of this 2Fi resist, the upper layer has a high mobility and the lower layer has a low sensitivity resolution. After exposure, the upper resist film is patterned with a solution that develops only the upper resist, and then only the lower resist is developed. The lower resist l-MW is patterned with a liquid, a gate material is deposited by vapor deposition or sputtering, and the resist is removed by a lift-off method to form a gate with a T-shaped cross section. In this way, two layers of resist 19 are formed,
The problem is that development must be performed twice using different developing solutions, which increases the number of steps.

[Means for resolving the problems] The present invention proposes a pattern forming method that solves the above problems.
The means for doing so includes resist IK! over a predetermined area of a resist film formed on a substrate. A step of irradiating the charged beam to such an extent that the resist film can be developed halfway, a step of irradiating the charged beam to the extent that all of the resist film is developed over a narrower area within the area, and developing the resist and exposing the exposed portion. A pattern forming method is performed, which includes the steps of removing the remaining resist and the gate forming material thereon, depositing a gate forming material on the entire surface, and removing the remaining resist and the gate forming material thereon by lift-off.

[Effect]

In the above method, when forming a gate of a MOS FET, a single layer of resist (IQ) is formed on a substrate, and a predetermined portion where a gate is to be formed is developed (resist removed) halfway through the resist film using a charged beam. Exposure to light until
Next, as described above, the resist film was exposed to light as described above. A resist pattern is formed in the shape, and then a gate material is deposited.
A gate having a desired T-shaped cross section is formed by lift-off.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

A group of researchers belonging to the present applicant conducted measurements on resist films that can be exposed using ion beams such as H', F'', and As'' with respect to the exposure characteristics of resist PMMA using an ion beam. The results shown in the figure were obtained (Japan Society for the Promotion of Science 132nd Committee 81st Study Group Exam f-t (57, 9, 24)).

In FIG. 2, the horizontal axis shows the acceleration energy in KeV, the vertical axis shows the thickness of the removed resist in μm,
Curve H+ is ion fffiH″″, dose Jf 1.6
X 1O-5C/cm', curve F+ is ion species F
+, dose amount 1. I x 10"" C/cm2
The relationship between acceleration energy and removed resist film thickness in the case of is shown.

In the case of H+, it takes 80K to expose a 1μm resist film.
An acceleration energy of eV is required. In the case of ^r, which has high sensitivity, an acceleration energy of 300 Keν or more is required for a film thickness of 0.5 μm, and it has been found that H4 is more advantageous. Therefore, in the embodiment of the present invention, PMMA was used for the resist and an H3 ion beam was used for exposure. The steps for carrying out the method of the present invention will be explained below with reference to the sectional view of FIG.

FIG. 1(a): A resist film 2 is formed by depositing a resist (P thickness A) on a substrate 1 to a thickness of 1 μm, and hydrogen ions (H”) 3 are applied at a dose of HH6X 10-' C/ cm' and acceleration energy of 40 Keν. Referring to FIG. 2, at this time, the resist film 2 is exposed to a depth of 0.7 μm from the surface.

(in Fig. 1): Subsequently, within the area of the resist cavity irradiated with the above-mentioned H'' 3, a dose of m 1.fix In -' C/
cm', smaller area with acceleration energy 80 kcV j
j:j to shoot.

By this irradiation, the resist 1- is exposed until it reaches the substrate.

The two instant ion beam injections described above first irradiate the ion beam over a wide area shown in FIG. The illumination may be made narrower as shown in FIG. 1 fhl, or by a vector scanning method.

Figure 1 (C): Next, a mixture of methyl isobutyl ketone (old [1M): isobrobyl alcohol (II'8) = 1:3]
Developed in fk for 90 seconds, D = 0.7.17m as shown in the figure,
A resist pattern with a cross-sectional shape of d = 0.3 μm is formed.

FIG. 1(d): Aluminum (1) is deposited on the entire surface as a gate forming material, and metal stones 4 are deposited to a thickness of 0.5 μm to 1.0 μm.

Typical gate materials include aluminum (aluminum) and molybdenum (Mo) for metals, doped polycrystalline silicon (doped polysilicon) for semiconductors, and MoSi2 and WSi2 for solicon metals. is deposited to a film thickness of 0.5 μm to 1.0 μM.

FIG. 1(e): When the resist is removed by the lift-off method using the same developing solution as above, a 4G film with a T-shaped cross section is obtained.

The illustrated gate length p can be set with high precision by adjusting the spread of irradiation of the ion beam 3a using the variable rectangle method or vector scan method described above.

〔Effect of the invention〕

As explained above, according to the present invention, a T-shaped cross-sectional gate, which can reduce the gate length and suppress an increase in gate resistance, can be formed with high accuracy in fewer steps than conventional methods in gate formation of a MOS FET. Since it is possible, MOS
This is highly effective in improving the manufacturing yield of FETs. Note that although the above example relates to the case where an ion beam is used to form the gate of a MOS FET, the scope of application of the present invention is not limited to that case, and may be applied to other pattern formation cases and where an electron beam or the like is used. This also applies to cases.

[Brief explanation of the drawing]

FIG. 1 ta+ to ffi+ are cross-sectional views of the main parts of a semiconductor device in the process of implementing the method of the present invention, and FIG. ff12 is a diagram showing the resist film thickness that can be exposed with an ion beam.
FIG. 3 is a sectional view similar to FIG. 1 of the conventional method. In the figure, ■ indicates a substrate, 2 indicates a resist film, 3 and 3a indicate an ion beam, 4 indicates a gate metal material, and 4G indicates a gate, respectively. Figure 1 Figure 2 Figure 1] '2□1 Figure 3 Figure 3

Claims (1)

[Claims] a step of irradiating the charged beam with a charged beam to the extent that the resist film is developed halfway over a predetermined area of the resist film formed on the substrate; It is characterized by including the steps of irradiating the resist with a charged beam, developing the resist and removing the exposed portion, depositing a gate forming material on the entire surface, and removing the remaining resist and the gate forming material thereon by lift-off. A pattern forming method.