JPS6173443A - Two-wire time division bidirectional communication device - Google Patents

Two-wire time division bidirectional communication device

Info

Publication number
JPS6173443A
JPS6173443A JP19612184A JP19612184A JPS6173443A JP S6173443 A JPS6173443 A JP S6173443A JP 19612184 A JP19612184 A JP 19612184A JP 19612184 A JP19612184 A JP 19612184A JP S6173443 A JPS6173443 A JP S6173443A
Authority
JP
Japan
Prior art keywords
switch
period
offset
receiving
equalizing amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19612184A
Other languages
Japanese (ja)
Inventor
Masayuki Sugaya
菅谷 公志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19612184A priority Critical patent/JPS6173443A/en
Publication of JPS6173443A publication Critical patent/JPS6173443A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

PURPOSE:To prevent the generation of a differential waveform in the output of an equalizing amplifier at switching from a transmitting period to a receiving period by providing an offset cancelling circuit between a receiving transformer and the equalizing amplifier. CONSTITUTION:The offset cancelling circuit 17 is constituted of a capacitor 12 and a switch 13. An offset charging period Tc is formed during the period from the start of the receiving period Tr to the arrival of a receiving signal S12. An input offset voltage of is charged in the capacitor 12 by shorting the switch 13 during the period Tc. After the priod Tc, the switch 13 is opened. Since the receiving period Tr has been already started at that time, a switch 15 is shorted and a switch 14 is opened, so that an input signal S12 of the equalizing amplifier 12 is obtained by subtracting the of from a transmission/ reception signal S11 in the receiving priod Tr as shown in S12. Thereby, the output S13 of the amplifier 16 is prevented from the generation of a differential waveform which may be generated in an ordinary example.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、二線式時分割双方向通信装置におけるオフセ
ント打ち消し回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an offset cancellation circuit in a two-wire time-division bidirectional communication device.

〔従来技術〕[Prior art]

二線式時分割双方向通信装置は、データの送信及び受信
を行うために、二線を時間的に2つに分割して、それぞ
れを送信期間、受信期間として双方向通信を行う装置で
ある。その通信装置IOの構成を第1図に示す。
A two-wire time-division two-way communication device is a device that performs two-way communication by dividing two wires into two in terms of time and using each as a transmission period and a reception period in order to transmit and receive data. . The configuration of the communication device IO is shown in FIG.

第1図において、1は通信装置10の入出力端子、2は
送信ドライバー、3は送信トランス、4は受信トランス
、5は後述の等化増幅器入力短絡用のスイッチ、6は後
述の等化増幅器切りはなし用のスイッチ、7は等化増幅
器である。
In FIG. 1, 1 is an input/output terminal of a communication device 10, 2 is a transmitting driver, 3 is a transmitting transformer, 4 is a receiving transformer, 5 is a switch for shorting the input of an equalizing amplifier, which will be described later, and 6 is an equalizing amplifier, which will be described later. 7 is an equalizing amplifier.

第1図の従来例において、第2図に示される如く、一般
的に送信期間Ttには、等化増幅器70入力に大振幅の
信号Sla加わらないように、スイッチ5は短絡、スイ
ンチロは開放しである。いま送信出力Slaのプラス、
マイナスの振幅にアンバランスがあると、等化増幅器7
の入力に直流のオフセット電圧が発生する。
In the conventional example shown in FIG. 1, as shown in FIG. 2, during the transmission period Tt, the switch 5 is generally shorted and the switch 5 is opened, so as not to apply the large amplitude signal Sla to the input of the equalizing amplifier 70. It is. Now the plus of the transmission output Sla,
If there is an imbalance in the negative amplitude, the equalizing amplifier 7
A DC offset voltage is generated at the input of the

次に受信期間Trとなり、スイッチ5が開放、スイッチ
6が短絡すると1等化増幅器7の入力信号S2としては
、5S2図の52の様な階段波S2aとなる。
Next, during the reception period Tr, when the switch 5 is open and the switch 6 is short-circuited, the input signal S2 of the equalization amplifier 7 becomes a staircase wave S2a like 52 in Fig. 5S2.

なお、等化増幅器7は、伝送路9の高域伝送損失を補う
ため、高域の利得を持ち上げである。このため等化増幅
器7の出力S3は、第2図の53の様を微分波形となる
Note that the equalizing amplifier 7 increases the gain in the high frequency range in order to compensate for the high frequency transmission loss of the transmission line 9. Therefore, the output S3 of the equalizing amplifier 7 has a differential waveform like 53 in FIG. 2.

したがって、従来の9!(10)では、入力DCオフセ
ント電圧と入力信号S2との振巾が同程度になると、等
化増幅器7の出力S3では、第2図のS3の如く、DC
オフセットによる微分波形と人力信号との区別がつかな
くなり、データが誤まるという欠点があった。
Therefore, the conventional 9! In (10), when the amplitudes of the input DC offset voltage and the input signal S2 become approximately the same, the output S3 of the equalizing amplifier 7 has a DC voltage as shown in S3 in FIG.
There was a drawback that the differential waveform due to the offset and the human input signal could not be distinguished, resulting in incorrect data.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、前述の従来技術の欠点、すなわち、送
信期間から受信期間に切り変った時の等化増幅器出力に
発生する微分波形を防ぐことにある。
SUMMARY OF THE INVENTION An object of the present invention is to prevent the above-mentioned drawbacks of the prior art, namely, the differential waveform that occurs in the equalization amplifier output when switching from the transmission period to the reception period.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、二線式時分割双方向通信装置の受信トランス
と等化増幅器との間に、直列に接続されるコンデンサー
と等化増幅器の入力を短絡するスイッチとで構成された
オフセット打消し回路である。
The present invention provides an offset canceling circuit that includes a capacitor connected in series between a receiving transformer and an equalizing amplifier of a two-wire time-division bidirectional communication device and a switch that short-circuits the input of the equalizing amplifier. It is.

〔実施例〕〔Example〕

本発明による一実施例の構成を第3図に示す。 The configuration of an embodiment according to the present invention is shown in FIG.

11は受信トランス、12はオフセット・チャージ用の
コンデンサ、13はオフセラ)−チャージ用のスイッチ
、!4は等化増幅器入力短絡用のスイッチ、15は等化
増幅器切りはなし用のスイッチ、1Bは等化増幅器であ
る。
11 is a receiving transformer, 12 is a capacitor for offset charging, 13 is an offset charging switch, ! 4 is a switch for short-circuiting the equalizing amplifier input, 15 is a switch for turning off the equalizing amplifier, and 1B is an equalizing amplifier.

上述の構成からなる実施例は、受信期間Trの初めから
受信信号S12が来るまでの間に、オフセット・チャー
ジ期間↑Cをもうける(第4図を参照のこと)、このオ
フセット・チャージ期間Tcに第3図のスイッチ13を
短絡することによって、コンデンサー圧に入力オフセッ
ト電圧Vofをチャージする(@4図のVafを参照の
こと)。
The embodiment configured as described above provides an offset charge period ↑C from the beginning of the reception period Tr until the arrival of the reception signal S12 (see FIG. 4), and in this offset charge period Tc. By shorting switch 13 in FIG. 3, the capacitor voltage is charged with the input offset voltage Vof (see @Vaf in FIG. 4).

オフセットチャージ期間Tcが終ると、スイッチ13は
開放される。この場合すでに受信期間Trなので、スイ
ッチ15は短絡、スイッチ14は開放されているため、
等化増幅器toの入力信号S12とじては、第4図のS
+2の様に、受信期間Trで第4図の送受信信号Sll
から第4図のVofを差し引いたものとなる。
When the offset charge period Tc ends, the switch 13 is opened. In this case, since the reception period Tr has already started, the switch 15 is short-circuited and the switch 14 is open, so
The input signal S12 of the equalizing amplifier to is S in FIG.
+2, the transmission/reception signal Sll in FIG. 4 during the reception period Tr.
It is obtained by subtracting Vof in FIG. 4 from .

1、たがって等化増幅器1Bの入力には、第2図の階段
波S2aが見られなくなり、等化増幅器1Bの出力51
3は、これによる微分波形を生じない(第4図のSl:
(参傅のこと)。
1. Therefore, the staircase wave S2a in FIG. 2 is no longer seen at the input of the equalizing amplifier 1B, and the output 51 of the equalizing amplifier 1B
3 does not produce a differential waveform due to this (Sl in Fig. 4:
(About Sanfu).

〔発明の効果〕〔Effect of the invention〕

以ヒの如く本発明は、毎受信期間の初めに、オフセット
打消 セylが送信期間毎に違っても、打ち消すという効果が
ある。
As described below, the present invention has the effect of canceling out the offset cancellation signal at the beginning of each reception period even if it differs from transmission period to transmission period.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図は同上を説明するタイ
ミングチャートであり、第3図は本発明による一実施例
を示す回路図、第4図は第3図を説明するタイミングチ
ャートである。 ll:受信トランス(手段) 14.15:スイッチ 16:等化増巾器 17:オフセツト打消し回路 12:コンデンサ 13:スイッチ
FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is a timing chart explaining the same, FIG. 3 is a circuit diagram showing an embodiment according to the present invention, and FIG. 4 is a timing chart explaining FIG. 3. It is. ll: Receiving transformer (means) 14.15: Switch 16: Equalization amplifier 17: Offset cancellation circuit 12: Capacitor 13: Switch

Claims (1)

【特許請求の範囲】 1)送信ならびに受信を行なうために、二線を時間的に
2つに分割して双方向通信を行なう装置において、 該通信装置の受信トランス手段と等化増幅器手段との間
にオフセット打消し回路を配設したことを特徴とする二
線式時分割双方向の通信装置。 2)前記特許請求の範囲第1項において、上記のオフセ
ット打消し回路が、オフセット電圧をチャージするコン
デンサと、上記等化増幅器手段の入力を短絡するスイッ
チとで構成されることを特徴とした通信装置。
[Claims] 1) A device for bidirectional communication by temporally dividing two wires into two for transmission and reception, comprising: A two-wire time-division bidirectional communication device, characterized in that an offset cancellation circuit is provided between the two wires. 2) The communication according to claim 1, wherein the offset canceling circuit is comprised of a capacitor that charges an offset voltage and a switch that short-circuits the input of the equalizing amplifier means. Device.
JP19612184A 1984-09-19 1984-09-19 Two-wire time division bidirectional communication device Pending JPS6173443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19612184A JPS6173443A (en) 1984-09-19 1984-09-19 Two-wire time division bidirectional communication device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19612184A JPS6173443A (en) 1984-09-19 1984-09-19 Two-wire time division bidirectional communication device

Publications (1)

Publication Number Publication Date
JPS6173443A true JPS6173443A (en) 1986-04-15

Family

ID=16352586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19612184A Pending JPS6173443A (en) 1984-09-19 1984-09-19 Two-wire time division bidirectional communication device

Country Status (1)

Country Link
JP (1) JPS6173443A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007308117A (en) * 2006-05-22 2007-11-29 Honda Motor Co Ltd Vehicle seat
KR101527222B1 (en) * 2008-12-24 2015-06-10 두산인프라코어 주식회사 Seat base sliding apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007308117A (en) * 2006-05-22 2007-11-29 Honda Motor Co Ltd Vehicle seat
KR101527222B1 (en) * 2008-12-24 2015-06-10 두산인프라코어 주식회사 Seat base sliding apparatus

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