JPS6173441A - Synchronizing device - Google Patents

Abstract

PURPOSE:To optimize automatically the phase of synchronizing data and of a clock by providing an N-phase selecting part, phase comparing part, averaging part, phase advance/delay deciding part, and an UP/DOWN counting part. CONSTITUTION:A synchronizing clock demodulation part 2 outputs N clocks having different phases respectively and the N-phase selecting part 7 selects one of these clocks to read demodulated synchronizing data and detect synchronization. If synchronization can not be detected, a counter in the UP/DOWN counting part is counted up and the selection value of the selecting part 7 is changed to select the succeeding clock and detect its synchronization. When the synchronization coincides with a constant synchronizing pattern after the detection of the synchronization, the rise of the selected clock is compared with a time up to the changing point of the synchronizing data by the phase comparing part and a level AM selected on the basis of a value counted by an NCK is outputted from a level selecting part 13. If coincidence is not obtained, jitter is removed by the averaging pat 14 and the jitter-removed signal is inputted to the phase advance/delay deciding part 15. Then, the phase is optimized by the selecting part 7, the UP/DOWN counter 8 and a phase compensation counting part 11 on the basis of the decided result of the decision part 15.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a synchronization device in time division multiple access. For example, in a button telephone device consisting of a main device and a telephone, control data and digital information between each device are synchronized. It can be used in a device that transmits voice data converted into , using electric power lines.

A conventional synchronizing device using clock-based transmission will be described below.

FIG. 1 shows a block diagram of a synchronization detection section of a conventional synchronization device using clock-based transmission, and numeral 1 indicates a synchronization data demodulation section. 2 is a synchronous clock demodulator, 3 is a serial/
4 is a pattern comparison section, 5 is a synchronization pattern setting section, and 6 is a synchronization determination section. FIG. 2 shows a timing chart. 0 indicates the synchronous data demodulated by the synchronous data demodulator 1, and CKA indicates the clock demodulated by the synchronous clock demodulator 2. CKB indicates a demodulated clock that is out of phase with CKA. The operation of the conventional synchronizing device using clock-based transmission configured as described above will be described below.

First, synchronous data is demodulated by a synchronous data demodulator 1 and input to a serial/parallel converter 3.

On the other hand, the separately transmitted synchronous clock is demodulated by the synchronous clock demodulator 2, and the synchronous data is manually read into the serial/parallel converter 3.
9] The data is output to the pattern comparison section 4. The pattern comparison section 4 compares the synchronization pattern with the synchronization pattern set by the synchronization pattern setting section 5, and signals indicating coincidence or mismatch are inputted to the synchronization determination section 6 to perform synchronization detection.

In such a conventional configuration, when the serial/parallel converter 3 performs conversion, it is necessary that the phases of the synchronous data and the clock match.

1. That is, the phases of the DA and GK must match. For this reason, changes in the characteristics of the transmission line through which synchronous data and synchronous clock are transmitted, and changes in the load connected to the transmission line,
As the transmission distance changes, the phase relationship between the synchronous data input to the synchronous data demodulator 1 and the synchronous clock input to the synchronous clock demodulator 2 changes, resulting in a phase shift as shown in CKB in FIG. 2. Therefore, there is a drawback that the synchronous data demodulating section 1 or the synchronous clock demodulating section 2 requires adjustment every time the load on the transmission path changes or the transmission distance changes.

Purpose of the Invention The present invention eliminates the above-mentioned conventional problems, and uses clock-specific transmission that makes it possible to optimize the phase of synchronous data and synchronous clock regardless of the characteristics of the transmission path. The purpose is to provide a synchronization device.

Structure of the Invention The present invention comprises a phase comparison section that compares the phases of a demodulated clock and synchronization data, an averaging section that absorbs thick components of the synchronization data and clock output to the phase comparison section, and A phase lead/lag determining unit that determines the phase relationship between the synchronized data and the clock, and based on the determination result, if the phase is leading, the signal is moved in the direction of delay, if the phase is delayed, the signal is moved in the direction of progress, and if the phase is appropriate, the signal is moved in the direction of delay. To maintain that state,
an amplifier/down-counter that outputs a control signal for selecting a clock, and an N-phase clock (N
is a natural number) to optimize the phase of the synchronized data and the clock. can be established.

DESCRIPTION OF THE EMBODIMENT FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. 1 to 6 are similar to the conventional configuration.

7 is an N phase selection unit, which selects one from N clock inputs of different phases. 8 is an up/down count section which provides selection information for the N phase selection section 7. Reference numeral 9 denotes an OR circuit section which takes the OR logic of the output signals of the out-of-synchronization counting section 10 and the phase correction counting section 11 and outputs it to the up/down counting section 8. Reference numeral 12 denotes a phase comparator, which compares the phases of the clock and synchronization data with N times the clock and outputs the ratio of 1 to the level selector 13. The level selection unit 13 selects the set level according to the input comparison 1. 14 is an averaging section which averages the level selection values. 15 is a phase lead/lag determining section.

FIG. 4 shows a timing chart.

NCK has a frequency N times higher than the clock frequency, 5YNC indicates synchronization data, GK is the clock that has the optimal phase relationship with this 5YNC, and CKN is the timing/time to read 5YNC of N clocks with different phases. Indicates the PHC
is the time when the two phases are compared when clock N is selected by the N phase selection unit in FIG. 3, and NCK is counted during this time.

AM is the output of the level selection unit 13 when time is expanded, and is the level value selected based on the phase comparison value;
M indicates the average value of the level values, and the averaging unit 14
This is the output of HL indicates the high level of the reference voltage in the phase lead/lag determining section 15, and LL indicates the same low level.

The operation of the synchronization device using clock-based transmission according to the present embodiment configured as described above will be explained.

FIG. 6 shows the flow of operation of this embodiment. The synchronous clock demodulator 2 demodulates the synchronous clock, outputs N clocks with different phases, selects one of them in the 8 phase selector 7, and reads the demodulated data in the synchronous data demodulator 1. , performs synchronization detection. If synchronization cannot be detected, the process proceeds from step 16 to step 17, and after counting the time required for synchronization detection, the counter of the up/down count section 8 is advanced through the OR circuit section 9.
The selection value of the phase selection section 7 is changed, the next clock is selected, and synchronization detection is performed. If further synchronization cannot be detected, repeat steps 16 to 18 in the same manner as above,
Perform synchronous detection. As described above, the same 191 detection can be performed using any of the different N@ clocks. However, the selected clock does not necessarily have an optimal phase relationship with the synchronous data. Therefore, after synchronization detection is completed, a function is required to switch to the clock GK with the optimal phase. A detection unit 15 is provided to enable selection of a clock with an optimal phase.

Next, after synchronization is detected, the process proceeds to step 19, and if the output signal of the comparator of the pattern comparison section 4 matches the set synchronization pattern, the phase comparison section 12 detects the rising edge of the selected clock and the change point of the synchronization data. The level AM selected based on the value obtained by counting the time of
Output from 3.

On the other hand, if they do not match, it does not necessarily mean that the synchronization data has been demodulated correctly, so the process skips step 2Q and proceeds to step 21. The reason why averaging is performed in step 21 is because the value of λM is not constant due to jitter in the demodulated synchronization data.

In other words, it passes through a filter. The output of the averaging section 14 is input to a phase lead/lag determining section 15 . The phase lead/lag determining unit 15 sets the ``H'' level and the ``L'' level, and if the input average value is immediately between the settings, it determines that the synchronization data and the selected clock are at the optimal phase. judge. If the selected clock has a phase relationship such that it reads tFl from the center of the synchronized data, the output of the averaging section 14 will be at a high level, indicating that the clock is ahead of the synchronized data, and vice versa. If the phase relationship is such that the rear of the data is read, the selected clock is behind the synchronous data. The above operation goes to steps 22 and 23, and if the clock phase seems to be ahead, the up/down counter 8 is operated so as to be delayed by the selection of the 8 phase selection section A, and the phase of the clock is delayed. In this case, the phase lead/lag determining unit 15 operates to operate the up/down counter 8 so as to advance the phase. After the phase correction counting section 11 counts the time, the phase selection section 7
is switched. If the phase relationship is optimal, the state remains unchanged.

As described above, according to this embodiment, even if the phase relationship between the synchronous data and the clock changes due to fluctuations in the load on the transmission path or changes in the length of the transmission path, the phase relationship between the synchronous data and the clock is automatically adjusted. is optimized, and synchronization detection can be performed correctly.

Effects of the Invention The present invention automatically converts synchronized data and clocks by providing an N phase selection section, a phase ratio soft section, an averaging section, a phase advance/itch determining section, and an amplifier/down count section. It is possible to realize an excellent synchronization device using clock-specific transmission, which can achieve the effect of optimizing the phase of the clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronization detection section of a synchronization device using conventional clock-based transmission, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a block diagram of a synchronization detection section of a synchronization device in an embodiment of the present invention. , FIG. 4 is a timing chart showing the operation, and FIG. 5 is a flow chart showing the same operation. 1...Synchronized data recovery section, 2...Synchronized clock demodulation section, 3...Serial/parallel/
- Part 1, 4... Comparator, 6... Synchronization pattern setting value, 6... Synchronization detection section, 7... 8
Phase selection section, 8...Up/down count section,
9...OR circuit, 10...Out-of-synchronization counting section, 11...Phase correction counting section, 1
2...Phase comparison unit, 13...Level selection unit, 14...Averaging unit, 15...Phase lead/lag determining unit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure and Figure 2 KB

Claims (1)

[Claims] a phase comparison section that compares the phases of the demodulated clock and synchronous data; an averaging section that absorbs jitter components of the synchronous data and clock outputted to the phase comparison section; and a phase relationship between the synchronous data and the clock. Based on the phase lead/lag judgment unit and the judgment result, if the phase is leading, it will be moved in the direction of delay, if the phase is behind, it will be moved in the direction of advancement, and if the phase is appropriate, it will be kept in that state. The device further includes an up/down count section that outputs a control signal for selecting a clock, and a phase selection section that selects clocks having different phases according to the control signal to optimize the phases of the synchronized data and the clock. synchronizer.