JPS6172848U - - Google Patents
Info
- Publication number
- JPS6172848U JPS6172848U JP15690484U JP15690484U JPS6172848U JP S6172848 U JPS6172848 U JP S6172848U JP 15690484 U JP15690484 U JP 15690484U JP 15690484 U JP15690484 U JP 15690484U JP S6172848 U JPS6172848 U JP S6172848U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- pattern
- semiconductor device
- adhesive film
- conductive adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002313 adhesive film Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第1図は本考案の半導体装置の一実施例を示す
主要断面図。第2図は本考案のバンプ付回路基板
の断面図。第3図は本考案のハーフエツチによる
回路基板の断面図。第4図は従来の半導体装置の
主要断面図。
1…IC、2…ICの各端子、3…回路基板の
絶縁部分、4…回路基板パターンのバンプ部分、
5…異方性導電接着膜、6…異方性導電接着膜に
散在するハンダボール、7…回路基板パターンの
メツキによるバンプ部分、8…回路基板パターン
、9…回路基板パターンのハーフエツチ部分、1
0…ICのバンプ。
FIG. 1 is a main sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a sectional view of the circuit board with bumps of the present invention. FIG. 3 is a sectional view of a circuit board formed by half etching according to the present invention. FIG. 4 is a main cross-sectional view of a conventional semiconductor device. 1... IC, 2... Each terminal of IC, 3... Insulating part of circuit board, 4... Bump part of circuit board pattern,
5... Anisotropic conductive adhesive film, 6... Solder balls scattered on the anisotropic conductive adhesive film, 7... Bump part by plating of circuit board pattern, 8... Circuit board pattern, 9... Half-etched part of circuit board pattern, 1
0...IC bump.
Claims (1)
装する構造でICの各端子と相対応する回路基板
の各パターン部分を断面的にもり上げる様にし、
なおかつ、IC外部用部分と回路基板パターンと
の間隙を15μm以上とることを特徴とする半導
体装置。 The structure uses an anisotropic conductive adhesive film to mount an IC and a circuit board, and each pattern part of the circuit board corresponding to each terminal of the IC is raised in cross section.
Furthermore, a semiconductor device characterized in that the gap between the IC external portion and the circuit board pattern is 15 μm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15690484U JPS6172848U (en) | 1984-10-17 | 1984-10-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15690484U JPS6172848U (en) | 1984-10-17 | 1984-10-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6172848U true JPS6172848U (en) | 1986-05-17 |
Family
ID=30714910
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15690484U Pending JPS6172848U (en) | 1984-10-17 | 1984-10-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6172848U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999000842A1 (en) * | 1997-06-26 | 1999-01-07 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
-
1984
- 1984-10-17 JP JP15690484U patent/JPS6172848U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999000842A1 (en) * | 1997-06-26 | 1999-01-07 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
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