JPS6170652A - Parallel signal expanding circuit - Google Patents

Abstract

PURPOSE:To expand parallel input signals to more parallel signals by using some of the parallel input signals as the data signal of a decoder and an FF latch signal and the remainder as data signals of an FFs. CONSTITUTION:Some of the parallel input signals D0-D7, i.e. D4-D6 and D7 are used as the data signal of the decoder 1 and the flip-flop latch signal and the remaining input signals D0-D3 are used as data signals of flip-flops 6-13, so that the parallel input signals D0-d7 inputted from eight signals are expanded into 32 parallel signals and outputted from eight signals are expanded into 32 parallel signals and outputted from the flip-flops 6-13 as outputs 1Q-4Q. Therefore, even equipment for control which has a limited number of parallel output signal lines is connected to external equipment by expanding the signals to many parallel output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Uses of the Invention] The present invention relates to a parallel signal expansion circuit f for expanding parallel output signals of a control device such as a computer.

[Background of the invention]

Conventional control devices such as personal computers may not be able to have a sufficient number of parallel output signals for controlling external devices due to limitations in mounting space, which is inconvenient.

[Purpose of the invention]

An object of the present invention is to provide a parallel signal expansion circuit suitable for converting a large number of parallel signals from a limited number of parallel output signals of a control device such as a computer.

[Summary of the invention]

The present invention connects a plurality of flip-flops and a decoder that selects the flip-flops to an input parallel signal, uses a part of the input parallel signal as a data signal of the decoder and a flip-flop latch signal, and uses the remaining part as a flip-flop latch signal. This is a parallel signal expansion circuit that expands an input parallel signal into a larger number of parallel signals and outputs them from a flip-flop by using the parallel signal as a data signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to Figures 1 and 2.

Figure 1 is a circuit diagram showing an embodiment of a parallel signal expansion circuit according to the present invention. In Figure 1, 1 is a decoder that selects a flip-flop, and only when the input G is at a lightning pressure level (L level), the output is either 1Y or 8Y depending on the combination of 1 voltage level of inputs A, B, and C. The output becomes L level, but when input G is high voltage level (H level), input A
, B, and C, all outputs 1Y to 8Y remain at H level. 2 and 5 are buffer gates that amplify the signal, and the input state appears as is at the output.

6 or 615 is a plurality of eight 4-circuit D type flip-flops, and when the clock input CK signal rises, the input 1D
4D are latched and their states appear on outputs IQ and 4Q, respectively. Naori O to D7
is a parallel signal that is input from the parallel output of the control device to which this circuit is connected, and is a part of the input signal of this parallel input signal.

to D3 are connected to data inputs 1D to 4D of a plurality of eight 7-lip flops 6 to 13 via buffer gates 2 to 5, respectively. In addition, input signals D4 to D7 of other parts of the parallel input signal are input A of the decoder 1,
B, C and Gc are connected respectively. , l, and outputs IY to 8Y of the decoder 1 are connected to clock inputs CK of flip-flops 6 to 13, respectively.

Next, Figure 2 is an example of the time chart of Figure 1. This will explain the operation of Fang 1. First, among the parallel input signals DO to D7 in Figure 111, as shown in Figure 2, only the input signal D7 is at H level and the other input signals 1) 0
Therefore, it is assumed that D6 is indeterminate. In this state, input signals DO to D become data signals for flip-flops 6 to 13.
From a certain point on 3, the example is as shown in Figure '3F2)1. At the same time, D4 and D6, which become data signals for the decoder 1 that selects 13 items from the flip-flop 6, are all set to L level as shown in Figure 2.
Suppose it is set to level. Then 0 from input signal DO
After all D6 have stabilized, the input signal D7, which becomes the flip-flop latch signal of the decoder 1, is brought down to L level and then raised to H level again as shown in Figure 2, and the pulse of this input signal D7 is When the output 1Y of the decoder 1 goes to the L level and the flip-flop 6 is selected due to the L level of the data signals D4 to D6 of the decoder 1, the output 1Y of the decoder 1 becomes the L level and the flip-flop 6 is selected. At the rising edge of the pulse of the input signal D7, the outputs 1Q and 4Q of the flip-flop 6 go from the input signal DO to the input signal D3, H and L, respectively.

It is set to the H level state. This flip flop 6
The output state of is held until the next flip-flop 6 is selected. Similarly, by changing the H level setting of the input signals D4 to D6, which are the data signals of the decoder 1, any of the flip-flops 6 to 13 is selected and the outputs 1Q to 4Q are converted into the input signal DO.
It is possible to set the state from D to B, respectively.

As described above, part of the input signals D4 to D6 and D7 of the input parallel signals DO to D7 are used as data signals and flip-flop latch signals of the decoder 1, respectively, and the remaining input signals DO to D3 are input from the flip-flop 6. By using it as a data signal of 13, 8
The input parallel signal DO or g-)D7 is extended to 52 parallel signals and the output 1Q of flip-flops 6 to 13 is
It can be output from 4Q. It goes without saying that the number of input parallel signals and the number of flip-flops in the above embodiments are not limited to the above.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even a device such as a control device that requires only a limited number of parallel output signals can be expanded to a large number of parallel output signals and connected to an external device.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an embodiment of the parallel signal expansion circuit according to the present invention, and Figure 2 is an example of a time chart of Figure 1. 1...Decoder, 2~5...Buffer Kate, 6~
13...4-circuit D type flip-flop, DO~D7
... Parallel signals to be input.

Claims (1)

[Claims] It consists of a plurality of flip-flops and a decoder that selects the flip-flops, and a part of the input parallel signal is connected as a decoder data signal and a flip-flop latch signal, and the remaining part is connected as a flip-flop data signal. A parallel signal expansion circuit configured to expand a parallel signal into a larger number of parallel signals and output them from a flip-flop.