JPS6170650A - メモリアクセス制御方式 - Google Patents
メモリアクセス制御方式Info
- Publication number
- JPS6170650A JPS6170650A JP19156584A JP19156584A JPS6170650A JP S6170650 A JPS6170650 A JP S6170650A JP 19156584 A JP19156584 A JP 19156584A JP 19156584 A JP19156584 A JP 19156584A JP S6170650 A JPS6170650 A JP S6170650A
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- bus
- memory
- access request
- buffer device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19156584A JPS6170650A (ja) | 1984-09-14 | 1984-09-14 | メモリアクセス制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19156584A JPS6170650A (ja) | 1984-09-14 | 1984-09-14 | メモリアクセス制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6170650A true JPS6170650A (ja) | 1986-04-11 |
JPH0310976B2 JPH0310976B2 (enrdf_load_stackoverflow) | 1991-02-14 |
Family
ID=16276782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19156584A Granted JPS6170650A (ja) | 1984-09-14 | 1984-09-14 | メモリアクセス制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6170650A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6859614B1 (en) | 1996-06-24 | 2005-02-22 | Samsung Electronics Co., Ltd. | Apparatus and method for controlling priority order of access to memory |
-
1984
- 1984-09-14 JP JP19156584A patent/JPS6170650A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6859614B1 (en) | 1996-06-24 | 2005-02-22 | Samsung Electronics Co., Ltd. | Apparatus and method for controlling priority order of access to memory |
Also Published As
Publication number | Publication date |
---|---|
JPH0310976B2 (enrdf_load_stackoverflow) | 1991-02-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5901294A (en) | Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access | |
EP0535821B1 (en) | Method and apparatus for dynamically steering undirected interrupts | |
US7350005B2 (en) | Handling interrupts in a system having multiple data processing units | |
JPS58225432A (ja) | 要求バツフア装置 | |
JPS5938620B2 (ja) | メモリ−コントロ−ラ用優先順位指定装置 | |
US4800490A (en) | Buffer storage control system having a priority circuit | |
US6567908B1 (en) | Method of and apparatus for processing information, and providing medium | |
US6694410B1 (en) | Method and apparatus for loading/storing multiple data sources to common memory unit | |
JPS6170650A (ja) | メモリアクセス制御方式 | |
JPS594733B2 (ja) | キヨウツウバスセイギヨカイロ | |
US7240144B2 (en) | Arbitration of data transfer requests | |
US6192441B1 (en) | Apparatus for postponing processing of interrupts by a microprocessor | |
US6625678B1 (en) | Livelock avoidance method | |
JP2587586B2 (ja) | データ転送方法 | |
JP2731761B2 (ja) | ネットワーク制御装置 | |
JP2545936B2 (ja) | バスインターフェースユニット | |
JPH01305461A (ja) | バス使用権制御方式 | |
JP2826466B2 (ja) | 並列コンピュータシステムの性能測定方式 | |
JP2505021B2 (ja) | 主記憶制御装置 | |
JPH0376505B2 (enrdf_load_stackoverflow) | ||
JPS59165171A (ja) | マルチプロセツサシステムにおける個別リセツト方式 | |
JPS6257050A (ja) | 共有メモリ装置 | |
JPH0434629A (ja) | メモリアクセス制御装置のビジーチェック方式 | |
JPS63142456A (ja) | 情報処理装置 | |
JPS5999555A (ja) | エラ−処理装置 |