JPS6170596A - Digital scale shifter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is used in combination with, for example, a digital audio signal playback device having a variable playback speed adjustment function, and allows the pitch of the playback audio signal to be freely adjusted by digital signal processing. Digital pitch shift/measuring device that can be changed υ
In particular, the present invention relates to a device that compensates for pitch changes that are compatible with changes in playback speed without depending on variations K on the playback device side, and that has increased versatility.

[Technical background of the invention]

As is well known, a digital pitch shifting device is a digital audio signal reproducing device having a digital output, such as a C
A PC that is combined with a D (compact disc) type DAD (digital audio disc) playback device (hereinafter referred to as a CD playback device) and supplied from this CD playback device.
M (pulse code model) data signal
Notal processing can be used to arbitrarily shift the pitch of the reproduced music signal up or down. Furthermore, if the CD playback device has a variable speed playback function, it is possible to compensate for changes in pitch due to changes in playback speed, and it is possible to play music signals that maintain the pitch at the specified speed even when the playback speed is changed. It is. In this case, the digital pitch shift device performs the digital processing in accordance with the information on the amount of change in playback speed with respect to the specified playback speed from the CD playback device, thereby compensating for pitch changes due to changes in playback speed.

FIG. 4 shows a configuration in which a digital pitch shift device is combined with the CD playback device having the variable speed playback function.
11 in the figure is a CD playback device. That is, in this CD playback device 11, the disk 12ff is rotated by the disk motor 13 at a constant linear velocity. This disk 12
An information signal modulated by a digital modulation method capable of cell 7 clocking, such as the EFM method, 3PM method, or EFM method, is recorded on one side of the optical pickup 14, and this information signal is detected by the optical pickup 14. The signal is supplied to the big azo therme circuit 16 via the RF signal processing circuit 15.

As is well known, this big-up boolean 2 circuit 16 performs tracking servo and f-track servo on the pickup 14, and also performs feed servo on the pickup feed motor (not shown).

On the other hand, the information signal detected by the pickup 14 is R
After being converted into a digital information signal 8FFM in the F signal processing circuit 15, the signal is supplied to a self-synchronous clock recovery PLL circuit 17 and also to a digital signal processing circuit 18. Here, the self-synchronized clock regeneration PLL circuit 17 regenerates the self-synchronized clock signal 5pLct from the digital information signal SFF wing, and this self-synchronized clock signal 5PL (!r is supplied to the digital signal processing circuit 18). .

This r digital signal processing circuit 18 receives a clock signal supplied via a speed mode changeover switch 19 for selectively switching between a specified playback speed and a variable playback speed, which will be described later, and the self-synchronized clock signal 5PL (! section). The phase difference clock signal swycx and the frequency difference clock signal 5IFCK are generated by comparing the phase difference clock signal swycx and the frequency difference clock signal 5IFCK. The disk motor 13 has a disk 12
The rotation is controlled at a constant linear velocity. Further, this digital signal processing circuit 18 processes the digital information signal 5F.
FIil and self-synchronous clock signal 5PLCK to bit-synchronous clock signal smcx and PCM7'' of PCM data signal SPCM in serial format with PCM data signal SPCM% - word-synchronous clock (sandelta lock) signal indicating one sample period of evening signal 8PCM 5WDCK
This PCM data signal S de C
M% The pit synchronization signal 8m (!K) and the word synchronization signal swncx are outputted to the outside via terminals 21 to 23, respectively.

On the other hand, the speed mode selector switch 19 is used to switch between a specified playback speed mode and a variable playback speed mode for the playback audio signal.
is connected to the fixed terminal B, and a voltage controlled oscillation circuit (hereinafter referred to as V
A CO circuit (denoted as CO circuit) 25 is connected. That is, when setting the playback speed to the specified playback speed mode, connect the movable terminal C1kA side of this switch 19 to select the clock signal S from the crystal oscillator circuit 24 having a predetermined reference frequency /M. When setting the variable playback speed mode, connect the movable terminal C of the switch 19 to the B side and select the clock signal S of the set frequency fv from the VCO circuit 25. The signal is derived by the digital signal processing circuit 18. Above vCO circuit 2
A control voltage VC for setting the excavation frequency f of 5 is generated by a control voltage generation circuit 26 consisting of a variable resistor VR to which a reference voltage +V is applied and a /4 TFA ang Or. Finally, this control voltage generation circuit 26 has a variable resistor V.
By moving the sliding terminal R, the control voltage vc can be freely set. This control voltage v
c is outputted to the outside via the terminal 27 through the short-circuit protection resistor B.

A conventional digital pitch shifting device connected to the CD playback device 1 constructed as described above is constructed as shown by the reference numeral 30 in FIG. That is, in this digital pitch shifter 30, the PcM7J-event signal 8PCMs bit synchronized clock signal W'ssc* and the cylinder synchronized clock signal SWNE outputted from the terminals 21 to 23 of the CD playback device 1 are connected to the terminals. Input via 31-33. Of these, the PCM data signal 8PCM is once stored in the write buffer circuit 35 of the memory circuit 34 by the bit synchronization clock signal 5sct and the word synchronization clock signal swncx, and then stored in the write buffer circuit 35 of the memory circuit 34 by the write address counter 36.
AM 37 is written at a period (jfl.) equal to the word synchronization clock signal swnct. Here % RAM
:The PCM data signal written to the IF is expressed as a write sequence (Swi). RAM like this
The PCM data signal written in J7 is read out by switching the two systems of A successive address counter 38 and B successive address counter 39 alternately at regular intervals. Note that the write address counter 36, the A read address counter 38, and the B read address counter 39
Each address output ADDw) e ADDII) A *
ADDIDI is selected by the address multiplexer 41 controlled by the timing control circuit 4oK and applied to the RAM 3 F of the memory circuit 34.

Each address ADDmnAeADDRD of the above A read address counter 38 and B read address counter 39
RAM corresponding to I: 1 2 systems of reading P from F
If the CM data signal series are (S Homu) and (S Trap Fuji), then the above two systems of PCM data signals (St^).

(Sin) is digitally connected by a cross-fade circuit 42. The PCM data signal SCF outputted from the cross code circuit 42 has a sampling period (or beat frequency) different from that at the time of tone writing, except when the pitch shift amount is 0. That is, when the pitch is shifted up, it is shorter than the writing cycle, and when the pitch is shifted down, it is longer than the writing cycle. Then, the PCM data signal SCF is converted by a digital-to-analog conversion circuit (hereinafter referred to as a D/A conversion circuit) 43 into an anamigu signal SA' which has been subjected to pitch shift processing, and is sent to the audio reproduction device via a terminal 44. Output.

Here, the pitch shift amount setting mechanism of the pitch shift device 30 will be explained.

First, the word synchronized clock signal 5WDI: supplied to the terminal 33 is connected to the timing control circuit 4.
0 and is also supplied to a phase synchronized clock generation circuit (hereinafter referred to as a PLL circuit) 45. This PLL circuit 45 is synchronized with the word synchronized clock signal seaC and generates a clock signal 8CLKg having a frequency equal to that of the system clock S10 of the CD playback unit 11. Terminal AK is supplied, and when movable terminal C is connected, it is supplied to timing control circuit 40 as a mask clock. On the other hand, the reference clock signal Sl"L from the crystal oscillation frequency dividing circuit 41 is connected to the fixed terminal B of the changeover switch 46.
When Kl is supplied and the movable terminal C is connected, the clock signals SCI and lE1 are supplied to the timing control circuit 40 as a master clock. still,
Clock signal 8C also output from crystal oscillation divider circuit 47
1, the frequency of IC1 is equal to the oscillation frequency/MK of the crystal oscillation circuit 24 on the CD playback device 11 side.

The crystal oscillation frequency dividing circuit 41 generates the clock signal ScL, as well as a frequency divided clock signal 5CLK2 and a sampling clock signal 5ADCK.The frequency divided clock signal 5CLK2 is supplied to the system control circuit 48, and a sampling clock signal 5ADCK is generated. 5ADCF is supplied to the clock input terminal of an analog/digital switching circuit (hereinafter referred to as W conversion circuit) 49. This circuit 49 has a terminal 50
input the control voltage vc from the CD playback device 11 via
The sampling clock signal 5ADCK is converted into a digital data signal in accordance with the sampling clock signal 5ADCK, and this digital data signal is used as control voltage data DC, which is playback speed change information necessary for pitch change compensation during variable speed playback of the CD playback device 11, as control voltage data DC. - Supplied to the control circuit 48.

The system control circuit 48 is supplied with operation data owzr from an operation/display unit 51 having a mode changeover switch 511, a pitch shift amount selection button 512, and a display 513. fiL30 is switched by setting the mode selector switch 51 of the control/display unit 51 to the (NOItMAL) side when the CD playback device 11 is playing at a specified speed according to the system control circuit 48. The movable terminal C of the switch 46 is switched to the B side, and the clock signal SCLICg is supplied to the timing control circuit 40.
By varying the changeover switch 46, the movable terminal C is set to AL.
The clock signal SCL[1 is switched to the timing control circuit 40. Here, when playing at the specified speed, the operation/display section 51 shifts) f1
By arbitrarily selecting the selection button 512, the operation data 5cty is supplied to the system control circuit 48,
gy from the operation data D and control voltage data Dc from the conversion circuit 49 to control data DeN? is generated and supplied to the timing control circuit 40, where the pitch shift processing described above is performed. Note that the pitch shift processing described above can also be performed when the pitch change 81 is compensated.

Next, the principle of operation of the digital pitch shifting device will be explained with reference to FIGS. 5 and 6.

FIG. 5 shows the pitch shift down operation. As mentioned above, in the figure (Swx) is the write data series written to the RAM J7K, (SIIA) is the read data series by the A continuous address counter 38, (Sin)U
A readout sequence by the B readout address counter 39 is shown. That is, RAjrl s 7 contains the period of the word synchronized clock signal swncx (':'fio: CD
In the playback device, the period TWR is the same as 22.68Cμ8])
(= TtgO), the PCM 7"-evening signal (SWR) is written, but the period TW1L is constant regardless of downshift or upshift. Here, T in the figure is R
It is Qfd times the maximum delay time TDL of AM J 7, and is called the Glock length. - As an example, if a sampling clock frequency of 44.1 (kHz) and a 16-bit PCM data signal S is delayed by a RAM with a capacity of 64 bits, the maximum possible delay time TDL is approximately 90 (kHz).
ms).

During this pitch shift down, TM = m-TH, (m
"1 s 2 t 3 t...), the two systems of A and B continuous output address counters 38 and 39 are alternately switched, and the data block Wn+k ( k=...,
-2゜-1,0,1,2,...) write cycle TWI (= TIJ) ) has a longer cycle TILD
Read with WN・Here %tn+5t(0) is length T
At the starting point of data block M, the write address counter 36 starts from address 0 and τo (= tn(A
) −tn(0) ) After passing the time, t” tnC
A) clears the A continuous address counter 38, and R
Assume that data reading is started from address O of AM37.

If this read data block is Wn', then Wn
' is read out until t'''n++(B) (
tn++(B) -tn(A) = TM), and after clearing the B read address counter 39, the process is started, 10 pieces of data Wn+1 are read, and the data block WtI+1' in the data series (8111) is read.
becomes. Thereafter, data is read from the RAM 37 by switching the A and B read address counters 311 and 39 alternately at the TM period, and the data series (octad) is read with "n".
p W11+2' + Wn+4' p ”' t
Wn+21' e ``'' data block (Sin) K is wnH' l Wn+3' *
.= p Wy++(zl -1)' * = data blocks are obtained.

Thus obtained (Sim) # (Sum
) are connected by a cross-fade circuit 42 to form a new data series (SCF) with a sampling period TIIDWIf. Switching point tn(A) + tn+1(B) etn+z(
A) # tn+5 (B) # To smooth the close reading of the data block W11+, ', W, +,' at # ・= and prevent click noise in the analog signal Sm after D/A conversion, Digital data is connected during the period of τcy by fade processing. This cross-fade processing is equivalent to the diagonal cut sys-splicing in the magnetic tape collection F, and a multiplier as shown in FIG. This is done by digitally multiplying the data. PCM data atonement SC that has been subjected to pitch shift down processing as described above
The sampling period TIDWN of F is longer than the write period Twi to RAM J7, and Tw+a<T
Write data series (Swm) generated by 凰DWN
By skipping the excess data part (TM-TILOW) of D/TILOW, the time consistency is made.
In the music (analog) signal S restored by the A circuit 43, the tempo of the song does not change, and only the pitch decreases.

Figure 6 shows the operation of pitch shift up. During this pitch shift up, the write data series (5vna)
The data for the period -'ryAst of TM (= m-T
Dt, ) A and B continue to appear 71”V counter 3
11.39 is switched alternately, and data is read from the RAM J7 at a cycle T UP which is shorter than the write cycle Twl. This read data series when switching the read address counter (
5IIA) data booklet/Wn+p' and (S
in ) data block Wn+,'(lp-ql=1
) cross-fade processing is similar to the operation during pitch shift down described above.

In this way, when shifting up the pitch, Twi > TILO
Since it is W, a read data foot is generated in the write data series (Swm). For this data foot,
(TFAIτ−Tv of write data series (SWI)
) is read twice to ensure chronological consistency. Therefore, in the music signal S restored by the D/A circuit 43, only the pitch increases without changing the tempo of the song.

Incidentally, here, the switching point tn(A) P tn+t(B) l tH-1-s of the successive address counter 38°39
(A) a = is set after the time TD has elapsed from the start point (address θ) of the corrupt address counter 36.
However, this is Ta 寞<Tiow* or Tw+a>
This is to prevent the write address by Tios+ from overtaking the read address (Twi < Tanw*) or to prevent the read address from overtaking the write address. Therefore, the pitch shift device mentioned above? i! 3o, read address counter 311
．． The switching point of 39 is detected by monitoring the write address with the timing control circuit 4Q, and the starting address always follows the vowing address, and the switching point is adjusted according to the amount of pitch shift so that the two addresses do not intersect. By changing the block length TM and the cross-fade period τcy in addition to the period τD of the switching point, the audible discomfort is minimized as much as possible.

Further, FIG. 8 shows a specific circuit of the read address clock generation circuit in the timing control circuit 4°, and FIG. 9 shows the output waveforms of each main part, and its structure and operation will be explained.

That is, in the continuous address clock generation circuit, 8
Bit presettable synchronous Ag counter 60. The inverter 61 and D are composed of 7 lips 70f62, and the control data DCN? given from the system control circuit 48? The above counter is 60! This is used as reset data. Note that the signal 8CO output from the CO terminal of the counter 60 is a carry output. Here, the word synchronized clock signal Swn in the specified playback speed mode
If the frequency of c+c is /ls, the frequency conversion magnification in the PLL circuit 45 is M, and the 1O decimal conversion value of the 8-pit reset data given to this read address clock generation circuit is DCN, then the readout generated by this circuit is The frequency /ADCK of the address clock signal 5Aoct is
Eight DC! K 3n Ding ``Takumiπi''``'' (1
) is given by In general, pitch shifting is performed in a 0-equal-tempered equal-tempered scale, which shifts the pitch in 6 steps up or down in semitone steps (100-cent steps) over a range of 1 octave according to the equal-tempered equal-tempered scale. divides an octave interval into 12 equal intervals, and the frequency ratio of adjacent tones is 12-7T.
I am trying to make it so that Tsumashi, the frequency of the starting sound is fo
The frequency FN of a tone N semitones from the starting tone s is Fw −10(12w'T) ” =
(2) is given. Furthermore, the above-mentioned cent refers to the pitch of any two tones with a frequency ratio of 1200%/T. A semitone is equal to 100 cents, and the frequency Fn of h cents from the starting note is (2 ) As in the formula, assuming the starting tone is 10, Fn = 10 (1200%/ton")"
・Given by (3). From this, when the control data Dc)l is calculated from (1) using n as the shift amount, it becomes (INT: integer ratio). This control data DCIII? Since is an integer, the DCH with the minimum system control time is selected. Therefore, if only pitch shifting is required, it is possible to connect to equipment that outputs PCM7'-event signals SPCM of various sampling frequencies within the range in which the PLL circuit 45 can operate.

Next, when the reproduction speed of the music signal is changed, the pitch changes, and the pitch shift amount compensates for this pitch change as described below.

That is, when the playback speed of the music signal is changed by ±x% from the specified speed, the pitch change D cents based on the pitch at the specified speed is given as follows.

(120M')" -1 output L (However, when downshifting, use , ±
= 71m (1 samurai) - (7) Tona, j7
, - RAMJ when performing a pitch shift of D cents 7
The read frequency foN from is w/1,
...(8). After all, when performing pitch compensation, the read cycle from RAM J 7 is set to 1/f1. It would be sufficient to fix it to .

The conventional digital pitch shift device shown in Fig. 4 does not compensate for pitch changes (NORMAL), and when the sampling frequency of the input PCM data signal SPI:M is the specified frequency and the pitch shift amount is O. In order to keep the distortion rate of the output analog signal S low, cross-fade processing is stopped, and the memory circuit 34 and cross-fade circuit 42 are operated simply as a shift register that performs delay. Since it is necessary to synchronize writing and reading to the memory circuit 34, the read address clock s@o
The mask clock 5cLE of the timing control circuit 40 that generates ct (1 is the word synchronization clock 31
Although the clock S is generated by the PLL circuit 45 with 1FDCI as the reference input, the changeover switch 51
In the pitch change compensation mode in which 1 is set to the (COMP) side, the master clock of the timing number control circuit 40 changes to 1 in synchronization with the change in the playback speed of the CD playback device 11.
The signal 5PLI, whose frequency changes, is switched to the fixed frequency clock signal 5CL11 generated by the crystal oscillation frequency dividing circuit 47. This clock signal 5eL
Since the frequency of K1 is f, the frequency is fixed to /mD(!K #/g by supplying control data that satisfies equation (1) to the read address clock generation circuit.

In addition, in the pitch change compensation operation, the read address counter 38 degrees is changed according to one playback speed change in order to prevent the write address and read address from crossing each other due to the difference between the write cycle and the bladder release cycle for the RAM J7. Since it is necessary to set the switching point of 39, the famic TM, and the cross-fade period τcr, it is necessary to detect changes in the playback speed on the pitch shift device side in order to perform this operation. Therefore, in the pitch shift step #30, the control voltage Vc of the VCO circuit 25 is input from the CD playback VC device 11, and the control voltage We is inputted from the CD playback VC device 11 by the circuit 49.
The timing control circuit 40 obtains the playback speed information of the playback device 11 in digital quantity, generates control data Dcsr necessary for setting the address counter switching point, block length, and cross-fade period by the system control circuit 48. is giving to

[Problems with background technology]

However, in the conventional 5m Zotal pitch shift device as described above, the digital data obtained by the A/D conversion circuit 49 corresponds accurately to the moving position of the movable terminal of the variable resistor Va on the CD playback device 11 side. This does not necessarily correspond exactly to the change in the oscillation frequency of the VCO circuit 25, that is, the change in the playback speed of the CD playback device 11. This is due to variations K in the components that make up the vCO circuit 25. For example, as shown in FIG. Some IKs have bl or C characteristics that do not conform to this.

For this reason, depending on the combination with the CD playback device, when performing pitch compensation operation, the pitch shift device may have a read address counter switching point that does not match the actual playback speed.
It is necessary to set the block length, loss fade width, and in this case, the read address and the write address are mixed, causing audible discomfort in the music signal restored by the D/A conversion circuit 43. Even if the above problem could be avoided by making the parts constituting the VCO circuit 25 highly accurate, or by providing a control means to achieve the desired characteristics through adjustment, this would impair the economic efficiency of the CD playback device. Moreover, problems such as an increase in adjustment time will also arise. Also, depending on the model of the CD playback device, only a digital output is provided, or even if a vCO control voltage VC output is provided, the reference voltage +V for generating the control voltage VC may be different. It also has the disadvantage of being a device that lacks versatility in that it is possible to compensate for pitch changes with specific models. Furthermore, pitch change compensation lacks versatility in that it is effective only for digital audio playback equipment having a specific sampling frequency fO.

[Purpose of the invention]

This invention was made in order to improve the above-mentioned problems, and is capable of adapting to changes in playback speed, regardless of variations in the digital audio signal playback device, which is the source of the digital data signal and has a variable speed playback function. It is an object of the present invention to provide a versatile digital pitch shifting device that has a pitch change compensation function.

[Summary of the invention]

゛ That is, the digital pitch shifting device according to the present invention has a variable speed reproduction function of a digital audio signal recording medium, reproduces a digital audio signal from the recording medium, generates a word synchronized clock signal, and outputs each signal to the outside. This device is used in combination with a digital audio signal playback device that allows the digital audio signal to be written into a memory circuit according to the word synchronized clock signal, and then specified by external operation using a system control circuit. The timing and timing for generating control data and read address clock signals according to the shifted amount
The timing control circuit switches between two read address counters to sequentially output digital audio signals from the memory circuit, and cross-fade the two read digital audio signals. After connecting, it changes to analog signal,
A counter circuit for counting the period or frequency of the word synchronized clock signal is provided, and the output of this counter circuit is applied to the system control circuit to output the digital audio signal as the control data. By adding playback speed data, it is possible to compensate for pitch changes appropriately in response to changes in playback speed, and various digital audio signal playback devices have a variable speed playback function where the specified sampling frequency forms a simple integer ratio. This system is characterized in that it can also compensate for pitch changes.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3. However, in FIG. 1, the same parts as in FIG. 4 are designated by the same reference numerals, and only the different parts will be described here.

Figure m1 shows its configuration, and the word synchronized clock signal 5w111 input to this digital pitch shift device.
cK is supplied to the timing control circuit 40, a changeover switch 74 to be described later, and a frequency dividing circuit 71, and after being divided into VPt or 1/QK by the frequency dividing circuit 71, it is supplied to a period counter circuit 72Vc. As shown in FIG. 2, this period counter circuit 72 is a digital one-shot circuit 7 that generates a (constant) pulse signal SMM with a period τ from the frequency-divided signal SIN from the 1-frequency divider circuit 71.
21, delay circuit 722, m-bit counter 723, m-bit latch circuit 724, latch clock generation circuit 225
and an upper/lower detection circuit 726 that detects that the m-pit counter 723 has reached its upper limit and lower limit.
It inputs the count clock signal 5COJN outputted from the crystal oscillation frequency divider circuit 73 to perform period counting, and performs the counting according to the request signal S q from the system control circuit 48. The resulting counting data I) spo is sent to the system control circuit 4.
8.

Further, the period counter circuit 72 will be explained in detail. First, when the lock signal SIN is input as shown in FIG. 3(,), the digital one-shot circuit 721 starts H()・i) from the clock signal SIN for a certain period τM as shown in FIG. 3(b). Becomes level/# Luz signal SMM
generate. This signal SMM is sent to the delay circuit 722.
The signal is then delayed for a predetermined time and supplied to the clear terminal CLEAR of the m-bit counter 123, as shown in FIG. Tsumashi, this m-pit counter 723 is delay circuit 2.
When the output signal 5INOL of 22 is at the H level, the clear period te14AR is reached), and when it is at the L (low) level, the count period is tCO (78 pieces). Count clock signal 5COUNT from oscillation frequency divider circuit 73
〒 is counted only during the above-mentioned count period t (! Pit latch circuit 724
Here, the latch clock generation circuit 725
is the request signal S from the system control circuit 48
One cycle of the input clock signal Sty is detected in accordance with IA, and a rough clock signal SLT as shown in FIG. Therefore, the m-bit latch circuit 724 latches the count contents of the m-pit counter 723 every time the latch clock signal SLTE is input.

The data latched by this m-bit latch circuit 724 is sent to the system controller as count data DIIFD.
- is supplied to the circuit 48.

Further, the crystal oscillation frequency dividing circuit 73 is composed of an oscillation circuit using a crystal resonator with an oscillation frequency /M2 and a frequency dividing circuit,
The master clock signal 5CLKz is applied to the system control circuit 48, the count clock signal 5cotntt is applied to the period counter circuit 72, and the frequency is applied to the changeover switch 74.
m reference clock signals 5CLK4 are generated and outputted respectively.

The changeover switch 74 selectively outputs the word synchronized clock signal S'voc supplied to the fixed terminal X and the reference clock signal 5CLK4 supplied to the fixed terminal Y by switching the connection of the movable terminal 2. The clock signal selected by the switch 74 is supplied to the PLL circuit 45. This PLL circuit 45 receives a master clock signal 5CLKI synchronized with the human clock signal as described above.
), this master clock signal 5CLK
□ is supplied to the timing control circuit 40.

Here, reference numeral 76 in the figure is a sampling frequency changeover switch, and this changeover switch 76 controls the specified sampling frequency of a digital audio signal playback device having a variable speed playback function connected to the pitch shift device. It is for supplying the circuit 48. In other words, if the sampling frequency of the playback device is fs, (=P-f1), this will close to the H side, and fg2 (
=Q-fa), it is done by closing to the L side. Then, the system control circuit 48 reads the set position of the switch 76 to generate a switching control signal sPQ, and supplies this control signal SPQ to the frequency divider circuit 11 and the crystal oscillation frequency divider circuit 73 to obtain the frequency division ratio (
1/P.

1/Q) and the frequency (fsl, fm□) of the reference clock signal 5CLK2.
A switching control signal SN/C is generated in response to the operation of 1, and this control signal SN/C is supplied to the changeover switch 14 to select between the word synchronized clock signal 5WDCK and the reference clock signal 8CLK4. There is.

Further, display data DDIIF is supplied from the system control circuit 48 to the operation/display section 51.
The count display section 51a displays the amount of change in playback speed with respect to the specified speed again, and when this amount of change reaches the upper limit and lower limit, the W notification LED 5 J 5 , 52
g is lit.

The operation of the above configuration will be described below.

First, it is assumed that the reproduction speed of a digital audio signal reproduction device that is a supply source of a PCM data signal is a specified speed, and that the sampling frequency is P-fg. In this case, set the mode changeover switch 511 of the operation/display section 51 to (NORM
AL ) side. This (NORMAL) side is in the pitch shift mode, and at this time the switch 74 receives the switching control signal SN/
C is closed to the fixed terminal X side, so the PLL circuit 4
5 is a word synchronization clock signal 5Wtl with frequency p−/th
A master clock signal 5C1-Kat synchronized with CK is generated and outputted from the timing control circuit 40K. The pitch shifting operation in this case is the same as the conventional one, so a description thereof will be omitted here.

Next, the mode changeover switch 51 of the operation/display section 5
By setting this to the (COMP) side, pitch change compensation operation begins. During this pitch change compensation operation, the selector switch 76 is set in accordance with the specified sampling frequency of the digital audio signal reproducing device. here,
The sampling frequency set in the switch 76 is fI
i-P-fs, the system controller circuit 48 reads the state of the switch 76 and outputs the control signal SP.
Q is generated and output, the frequency division ratio of the frequency divider circuit 71 is switched to 17P, and the frequency of 4 is switched to P-fl for the reference clock signal ScL output from the crystal oscillation frequency divider circuit 73. At this time, the system control circuit 48 closes the selector switch 74 to the fixed terminal Y side based on the switching control signal sN/cK, so that the reference clock signal 5CLjC4 is supplied to the PLL circuit 45Vc.

Here, the timing control circuit 40 and P
Since the LL circuit 45 is similar to the conventional one, the master mic signal 5CLI[. frequency/eLK (1 and frequency fhDcl of read address clock signal 5ADeK
L is given as follows.

/CLt(1-M IIP・/a-”
(9)""""2255 fan t IIP"' ・
...Also, during pitch change compensation operation, /ADC1[=
fim-P-fm, the system control circuit M4J is Dcst m 255-T...
The control data DCN is αη. (integer) and supplies it to the timing/fund control circuit 40.

Incidentally, the period of the word synchronized clock signal swocx whose frequency has been divided by 1/P by the frequency dividing circuit 11 is counted by the period counter circuit 12. This period counter circuit 72 supplies its count value as m-bit data DIIFD to the system control circuit 48K. This system control circuit 48 calculates the amount of change in the playback speed of the current □ with respect to the specified speed from the data DIFD, and calculates the switching point of the read address counter 311.39 suitable for the playback speed, the block length, and the cross 7 processing period. The timing control circuit 4 generates control data DCNT of
0 to compensate for pitch changes.

The count range of the period counter circuit 12 is set so as to absorb variations in the playback speed variable range of digital audio signal playback equipment. Normally, the playback speed variable range is set to ±6- (change of ±1 semitone) or ±12 chi (change of ±2 semitone) in consideration of pitch change. That is, in a digital audio signal playback device, changes in playback speed exceeding the above range are rarely performed due to the reduction in the ability to read signals from the recording medium and the operating frequency limit of the digital signal processing section. The count range is set around ±20%. The amount of change in the playback speed with respect to the specified speed obtained from the count value of the period counter circuit 72 is displayed on the count display section 514, and when the upper limit and lower limit are reached, a warning LED 5 J is displayed.
5, 516 is lit and displayed.

Furthermore, when inputting a PCM data signal with a specified sampling frequency of Q-fs to operate pitch change compensation, switch the selector switch 76 to L fill K, switch the division ratio of the frequency divider circuit 11 to IA, and select PLL. The frequency of the reference clock signal SCI to the circuit 45 is set to Q-fm. Even in this operation, the center frequency of the input signal SIN of the period counter circuit 72 is the above-mentioned /Iscop −
As in the case of fI+, fIi "Q-fm", and from this K, the period counter circuit 12 outputs the playback speed change amount data DI by period counting without making any changes.
IFD can be obtained. Also, the read address clock signal 5AD (frequency of K/ADCI [is floc*
=Q-fs, which makes it possible to compensate for pitch changes. Note that even in the pitch change compensation mode, the frequency setting data of the read address clock generation circuit 5cNT1 read address counter 311.39
By manipulating the switching point, block length, and cross-fade period, it is also possible to shift the pitch while changing the playback speed in the same way as in the past.

Therefore, when the digital pitch shift device configured as described above performs a pitch change compensation operation, the input PCM
By counting the sampling period (or frequency) of the data signal, it is possible to accurately detect changes in the playback speed of the digital audio signal playback device that is the source of the PCM data signal. Compensation for pitch changes becomes possible. Also, by appropriately setting the period (or frequency) count range,
It becomes possible to ignore variations on the playback device side, specifically, variations in the variable frequency system clock generation iVCO circuit. Furthermore, the word synchronized clock signal 5WDCK to the 5-cycle counter circuit 72 is divided by 1/P or VQ so that it can be supplied to the PLL circuit 35 in two ways.
By making it possible to set the 40 frequency in two ways, p-/- or Q-fs and a small contribution ratio, different sampling frequencies fl, if the number of quantization bits is the same, can be set.
(=P-fm) and fm2 (=Q・fm), it is possible to compensate for pitch changes during variable speed playback for digital audio signal reproducing equipment having fm2 (=Q・fm). 1/P t 1/Q , 1/R
, . . . and by extending the frequency of the black signal to the PI, L circuit 45 to P-flI, Q-fs, R.fs+, etc., it is possible to correspond to three or more types of sampling frequencies. It is also possible.

〔Effect of the invention〕

As described in detail above, the present invention provides a pitch change compensation function that adapts to changes in playback speed, regardless of variations in the 7' audio playback device, which is the source of the digital data signal, and has a variable speed playback function. It is possible to provide a versatile digital pitch shifting device.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an embodiment of a digital pitch shifting device according to the present invention, FIG. 2 is a block circuit diagram showing the structure of a period counter circuit of the same embodiment, and FIG. 3 is a block circuit diagram showing the structure of a period counter circuit of the same embodiment. 4 is a block circuit diagram showing the configuration of a conventional digital pitch shifting device and a CD playback device, and FIGS. 5 to 7 each explain the operating principle of pitch shifting. FIGS. 8 and 9 are diagrams for explaining the configuration and operation of the read address clock generation circuit applied to the digital pitch shift device, respectively, and FIG. FIG. 3 is an oscillation characteristic diagram of the circuit. Jl...CD playback device, 18...digital signal processing circuit, 19...mode changeover switch, 24...crystal rooting circuit, 25...vCO circuit, 26...control voltage generation circuit, 30...Digital pitch shift device, 34.
...Memory circuit, 35...Write buffer circuit, 36
...Write address counter, 37...RAM. 38.39...Read address counter, 40...
Timing control circuit, 41...Address multi-function circuit, 42...Cross 7-way circuit, 43.
...D/A conversion circuit, 45...PLL circuit, A6...
・Selector switch, 47...Crystal oscillation frequency divider circuit, 48・
...System control circuit, 49...Line conversion circuit, 51...Operation/display unit, 511...Mode selection switch, 512...Pitch shift scene selection button, 513.
...Display unit, 514...Count display section, 515.5
16...Alarm LED, 60...Aggkakunta, 6
DESCRIPTION OF SYMBOLS 1... Inverter, 62... D-type 7-rig float, 71... Branch circuit, 72... Period counter circuit,
72 no...Digital one count circuit, 722...
Delay circuit, 723... m-bit counter, 724...
・m-bit latch circuit, 725...Latch "black and white generation circuit, 226...Ac/mother/lower detection circuit,"
23...Crystal oscillation frequency divider circuit, 74...Selector switch, Spcw-PCM data signal, 5WDCK...Word synchronization clock signal, vc...♂ control voltage, 1)s
pa...Counter data, next...Control data. Applicant's agent Patent attorney Takehiko Suzue Figure 2
71.7□ pa Figure 3

Claims (1)

[Claims] Used in combination with a digital audio signal playback device that has a variable speed playback function for digital audio signal recording media, plays back digital audio signals from the recording medium, plays back word synchronized clock signals, and outputs each signal to the outside. means for writing the digital audio signal into a memory circuit in synchronization with the word synchronization clock signal, a system for generating control data according to a shift amount specified by an external operation, a control circuit, and the control circuit. a timing control circuit that inputs data and generates a read address clock signal; a means for sequentially reading digital audio signals from a memory circuit by switching two systems of read address counters using the timing control circuit; In the digital pitch shifting device, the digital pitch shifting device has means for cross-fading and connecting two systems of digital audio signals, converting the resulting signals into analog signals, and outputting the analog signals to the outside as playback audio signals. A digital pitch shifting device comprising: a counter circuit for counting; and means for applying the output of the counter circuit to the system control circuit and adding playback speed data of a digital audio signal to the control data.