JPS616923A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To operate the titled circuit surely and stably with simple constitution by applying an edge detection pulse to two delay circuits with a fixed delay time and using two delay pulses obtained from the delay circuits so as to invert alternately an output of an FF. CONSTITUTION:A pulse (a) to be modulated is fed to an edge detecting circuit 2. A high frequency oscillating pulse from an oscillator 8 is fed to clock terminals of DOFF26, 27. Thus, a pulse (b) risen in phase locking with both edges of the pulse (a) and having a period share of pulse width of an output pulse of the oscillator is extracted from an exclusive OR circuit 28 and fed to a gate circuit 3 and a condition set circuit 4. An output pulse (c) of the circuit 3 is fed to retriggerable monostable multivibrators 29, 30 operated as the delay circuits and is triggered at the leading edge. Pulses d, e extracted from monostable multivibrators 29, 30 with a delay are inputted to a reset/set terminal of the FF23, which generates a window pulse WP.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse generation circuit, and more particularly to a circuit for generating wind pulses necessary for demodulating time codes in a bi-phase modulation system for VTR editing.

Conventional Technology Traditionally, when performing electronic editing on a VTR, various speed playbacks are performed, such as image search using high-speed playback and scene recognition using low-speed playback, but the time code is recorded as an absolute address on the magnetic tape. If so, the accuracy and reliability of automatic editing can be improved. This VTRTR editing chrome code is from the Society of Motion Picture and Television Engineers (SI).
A bi-phase mark modulation time code is used that is standardized by VjPTE and is recorded and played back on the audio cue track and audio track on the magnetic tape. Here, in the biphase mark modulation method, when the bit information (data) is "1", the polarity is reversed at half the bit period T, and "o", "1"
In either case, the modulation method always inverts once at the beginning of each bit period, and the minimum reversal interval of magnetization is T/2,
It is well known that this is a modulation method in which the maximum inversion interval is the key.

Therefore, in the above time code, a transition (level change) occurs at least at the beginning of each bit, and the clock component is extracted from the pulse (transition pulse or edge detection pulse) generated by detecting the transition using a wind pulse. Furthermore, bit information can be demodulated by detecting the presence or absence of a transition in the middle of the clock.

Conventionally, two methods have been considered for demodulating the above-mentioned time code: a method of processing it as an analog signal and a method of processing it as a digital signal. The former method detects a wind pulse from a serially transmitted time code to generate a sawtooth wave, determines whether there is a transition in this waveform, and demodulates bits "O" and "1". On the other hand, the latter samples the time code at a sufficiently high frequency, generates a wind pulse through this processing, detects the presence or absence of a transition in the wind pulse, and demodulates the bits 0"" and "1". This is a method to do so. Among these two methods, currently,
The latter method, which utilizes digital signal processing, is often used because it provides high accuracy.

FIG. 7 shows a circuit system diagram of an example of a pulse generating circuit that utilizes the above-mentioned digital signal processing and was previously proposed by the applicant in Japanese Patent Application No. 106485/1985. In the figure, the time code input to input terminal 1 is supplied to edge detection circuit 2, where both the rising and falling edges are detected and then supplied to gate circuit 3 and condition setting circuit 4, respectively. Ru. The gate circuit 3 is supplied with the output signal of the condition setting circuit 4 as a gate pulse, and in an initial state (for example, a state before the magnetic tape of a VTR reaches a predetermined running speed), the output edge detection pulse of the edge detection circuit 2 is ignored. The edge detection pulse is selectively outputted depending on the conditions, and in the steady state, except during the dropout occurrence period, the edge detection pulse is gated out based on the output wind pulse.

The edge detection pulse taken out from the gate circuit 3 has its polarity inverted by the inverter 5 and is supplied to the clear terminal of the counter 6, while being supplied to the latch circuit 7 as a latch pulse. On the other hand, the high frequency oscillation pulse extracted from the oscillator 8 is sent to the edge detection circuit 2. are supplied to counters 6 and 9, respectively.

The digital signal indicating the count value of the counter 6 is supplied to the latch circuit 7, where it is latched, and then output from its output terminal to the LSB (Lease 1 to Significance).
The digital signal shifted by 2 bits in the n-bit direction is taken out and supplied to the comparator 10.

Therefore, the output signal of the latch circuit 7 does not indicate 1/4 of the count value of the counter 6. The comparator 10 compares the count value of the counter 6 and the output signal of the latch circuit, and when the two match, generates a T/4 delay pulse that goes to low level, for example, and clears the counter 9. 11 to the latch circuit 12, which causes the latch circuit 12 to latch the decremented value of the J counter 9 immediately before being cleared.

From the latch circuit 12, an n-by-n digital signal obtained by shifting the input n-bit digital signal by one bit in the LSB direction, that is, a signal representing 1/2 of the count value of the counter 9 is taken out.

The comparator 13 is supplied with both signals from the counter 9 and the latch circuit 12, and when the two signals match, outputs a low level signal for a certain period of time, for example. RS flip-flop 1
4, the comparator 10.13's Ryokawa force signal is supplied to its reset terminal and set terminal. This allows flip 70
The output from the Q output terminal of the knob 14 falls after T/4 (where the peak is the bit period of the input time code of the input terminal 1) from the leading edge of the output edge detection pulse of the gate circuit 3, and 37 from the leading edge of the output edge detection pulse
/4 (= (T/4) + (T/2 >), a substantially symmetrical square wave with a periodicity that rises after (T/4) + (T/2 >) is extracted and output to the output terminal 15 as a wind pulse WP, while being sent to the condition setting circuit 4. Supplied.

Problems to be Solved by the Invention In the above pulse generating circuit, the repetition frequency of the output oscillation pulse of the oscillator 8 is twice the upper limit frequency of the input time demand.
It is necessary to select a frequency that is at least double that of the oscillation frequency, and it is desirable that the oscillation frequency be higher in order to improve accuracy. However, if the above-mentioned oscillation frequency is short, the counts of counters 6 and 9 within the same period T will be large, so counters 6 and 9 will need to be able to count many counts, and the counters will be Since two circuits are required, the circuit scale becomes large, which poses a problem in terms of circuit simplification and future large-scale integration (LSI).

SUMMARY OF THE INVENTION Therefore, the present invention provides a pulse generation circuit which solves the above problems without losing the basic performance or circuit stability of the proposed pulse generation circuit by providing a delay circuit with a fixed delay time. With the goal.

Means for Solving the Problems FIG. 1 is a block system diagram showing the configuration of the present invention, and the same components as in FIG. 7 are given the same reference numerals.

The input pulse train (modulated pulse) modulated by the biphase modulation method that enters the input terminal 1 is sent to the edge detection circuit 2.
The signal is supplied to the gate circuit means 20 through the gate circuit 20, where it is unconditionally gated and output in the initial state (for example, in the case of R, the period from when the magnetic tape running speed starts running until it reaches approximately the normal speed), and is output in the steady state. The gate output is performed based on the wind pulse output to the terminal 24. The output pulse of the gate circuit means 20 is branched into two, one being supplied to a first delay circuit 21 and delayed there by a certain time To, and the other being supplied to a second delay circuit 22 and delayed by a certain time T+. will only be delayed.

The first delay pulse from the first delay circuit 21 is applied to the reset terminal of the RS control flop 23, while the second delay pulse from the second delay circuit 22 is applied to the set terminal of the flip-flop 23. be done. When the first and second delayed pulses are received alternately, the flip-flop 23 generates and outputs an output pulse whose polarity is alternately inverted as a wind pulse WP from its Q output terminal. This wind pulse WP is output to the output terminal 24 and is also supplied to the gate circuit means 20.

Function: Here, the delay 0.1 interval 0 of the first delay circuit 21 is approximately 1//1 of the hit period T of the input pulse train, and the delay time 'I + tri of the second delay circuit 22 is approximately 1//1 of the hit period T of the input pulse train. The delay time 310 is selected to be three times the delay time To. Therefore, the output from the Q output terminal of the flip-flop 23 falls at about T/4 from the leading edge of the input pulse train.
And approximately 3 T/4 f from the leading edge of the incoming horn pulse train
The pulse that rises at the point in time is extracted. The 0111 power width of this flip-flop 23 (pulses from the child are at high level at the leading edge of the input pulse train and the phase around it, and at the leading edge of exactly 1/2 of the bit period T of the input pulse train and its 4 Since it is at a low level in the nearby phase, it can be used for the wind pulse WP.
and the delay time 1-o of the second delay circuit 21.22.

]-1 has a fixed delay time, but can be realized by a simple circuit. Hereinafter, the present invention will be described in more detail along with examples.

Embodiment FIG. 2 shows a circuit system diagram of an embodiment of the pulse generation circuit according to the present invention. In the figure, the same components as in FIG. 1 are given the same reference numerals. In FIG. 2, a modulated pulse (time code signal) a as shown in FIG. 3 (Δ) that has entered the input terminal 1 is supplied to the data input horn terminal of the D flip-flop 26 in the edge detection circuit 2. . Here, the input modulated pulse is a carrier wave of 2.4 kHz, which is a symmetrical square wave with a period of 2 times as shown in FIG. )
This is a pulse train as shown in . As shown in FIG. 4(B), this modulated pulse has data shown at the top of its waveform of '1'.
'', the transition from 1 to transition (
level change), and when the data is '0', no transition occurs within the bit period T, and the data is '0'.
o”.

Regardless of "1", a transition always occurs at each start position of each bit period -'.

As shown in FIG.
The configuration is such that each input terminal is connected to the input terminal of the manual disjunctive sum circuit 28. Further, a high frequency oscillation pulse (for example, 4Ml-1z) from the oscillator 8 is supplied to each clock terminal of the flip-flops 26 and 27. Konini J:
U1 and other outputs from the Tsuribe logic and sum circuit 28 rise in phase synchronization with both the rising and falling edges of the input modulated pulse a of the input terminal 1, and the pulse of one period of the output oscillation pulse of the oscillator 8. An edge (transition) detection pulse 1) having a pulse width as shown in FIG. 3 (E3) is taken out,
The signal is supplied to the gate circuit 3 and the row A'1 setting circuit 4, respectively.

The condition setting circuit 4 has a triggerable circuit configuration as long as it is triggered by the edge detection pulse b, and the condition setting circuit 4 has a triggerable circuit configuration as long as it is triggered by the edge detection pulse b. When an out occurs, a high-level signal is always generated and output, and the gate circuit 3 is kept in the gate "open" state, allowing the edge detection pulse to pass unconditionally. However, for example, suppose that the edge detection pulse shown in FIG.
If the edge detection pulse does not come in for a period of at least twice as long, the terminal voltage of the charging/discharging capacitor of the time constant circuit in the condition setting circuit 4 will be below the threshold level L as shown in FIG. 5(B). Therefore, at the point when this level is below LD, the article is ready! As shown in FIG. 5(C), the switching signal in the l setting circuit 4 becomes low level, its output signal becomes high level, and the gate circuit 3 is brought into the gate "open" state.

On the other hand, when the VTR is in a steady state, the terminal voltage of the charging/discharging capacitor is equal to or higher than the threshold level L, so that the internal switching signal is As shown in the previous waveform, it is always at a high level, thereby avoiding passing the wind pulse WP as shown in FIG. 3 (F), which will be described later.
Hedetsuno-cl-ru.

Therefore, in the steady state, the gate circuit 3 is in the gate "listening" state only during the high level period of the wind pulse WP, and blocks the passage of the input edge detection pulse b during the low level period of the wind pulse WP. Therefore, when a modulated pulse (time code signal) a as shown in FIG. 3 (Δ) enters the input terminal 1 in a steady state, the output number 3 of the setting circuit 4 is Hakushu as shown in Figure 3 (G).

When this is the case, the output signal of the gate circuit 3 becomes a pulse train as shown by C in FIG.

Output pulse C beam of gate circuit 3 1 ~ Regregable monostable multi-by-break (hereinafter referred to as "mono multi") 29
and 3o, respectively, and triggers them with its rising edge. The delay circuit 29 is connected to the first delay circuit 2.
In the circuit corresponding to 1, when triggered by the rising edge of pulse C, it remains low for a time T/4 (= TO) from white (7 bells, and becomes high 1 novel when T/4 elapses) Outputs a pulse.Therefore, monomulti 29
The output pulse of is as shown by d in FIG. 3<D). On the other hand, the monomulti 30 L; L is a circuit corresponding to the second delay circuit 22, and remains at a low level for a period of 3T/4 (=3TO) from the time when it is triggered by the rising edge of the pulse C, Outputs a pulse that becomes high level after 3T/4 has elapsed. However, the mono multi 30 has a retriggerable configuration.
When pulse C enters within the period of metastable state 4, it is re-triggered by the rising edge of pulse C, and from this point on, a low level signal is output again for a period of 3T/4. Therefore, when the pulse C enters the monomulti 30 with a cycle smaller than 31-o, the output pulse of the monomulti 3o remains at a low level. As a result, the output pulse of the monomulti 30 becomes as shown by e in FIG. 3(E).

The first delayed pulse d, which is delayed by the time To and taken out by the monomulti 29, is applied to the reset terminal of the flip-flop 23, and the rising edge thereof puts it in the reset state. In addition, the time 3To by mono multi 30
The second delayed pulse e taken out after being delayed by N is applied to the set terminal of the flip-flop 23, and sets it to the set state at its rising edge. Therefore, as shown in FIG. 3(F), the Noribu flop 23 has a high level from its Q output terminal at the time corresponding to the rising to F edge of the input modulated pulse a, and the output of the input modulated pulse a is high. It generates and outputs a wind pulse WP which is at a low level at and around the time of overturning corresponding to the half of the bit period T.

Next, a demodulation circuit for demodulating the biphase mark modulated pulse using the wind pulse generated in this manner will be explained. FIG. 6 shows a circuit diagram of an example of this demodulation circuit.

In the figure, a biphase mark modulated time code signal inputted to an input terminal 34 is supplied to one input terminal of each of two-manual AND circuits 36 and 37 through an edge detection circuit 35. On the other hand, the wind pulse generated by the above-mentioned pulse generation circuit enters the input terminal 38, is further inverted in polarity by an inverter 39, and then applied to the other input terminal of the input N+) circuit 36, and is also inverted in polarity. The signal is directly applied to the other input terminal of the AND circuit 37 and the clock terminal of the shift register 41, respectively.

As a result, when there is a transition in the middle of the pitch period T of the incoming corner time code signal, an edge detection pulse that is phase-synchronized with the transition is extracted from the AND circuit 36, and the edge detection pulse is output from the RS flip-flop 40.
state. 7C: The edge detection pulse (clock component) at each start position of the bit period T of the input time code signal is taken out from the AND circuit 37 and the flip-flop 40 is reset. A binary signal corresponding to the data of the input time code signal is taken out from the Q output terminal and is serially input to the data input terminal of the shift register 41 at the next stage.

The shift register 41 sequentially shifts the data obtained by rimbling the signal applied to its data input terminal with the rising edge of the wind pulse applied to its clock terminal to the incoming wind pulse 1j4, and stores the m bits of the data. The data of 11 rounds is output in parallel from the output terminal of. The digital signal of n1 pin 1- which is serial-parallel converted and taken out by the shift register 11'1 is output 9 as a demodulated signal.
ii output to the child 43, while the sync word detection circuit 4
1, the sync word detection signal is supplied to the shift register 41, where the sync word is detected.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and is not limited to \Nel-B, but is applicable to tapes, discs, etc., such as digital audio systems that record and play music signals using i' digital signals as well as video signals. It can also be applied to timecode. Furthermore, it can be applied to modulated pulses modulated by other bi-phase modulation methods such as bi-phase space modulation method.

Effects of the Invention As described above, according to the present invention, the edge detection pulses outputted from Go 1 are supplied to two delay circuits with fixed delay times, and the two delayed pulses obtained by the edge detection pulses are used to output the flip-flop. Since the circuits are alternately inverted, it is possible to eliminate the need for counters, latch circuits, magnitude comparators, etc., resulting in an extremely simple circuit configuration.Also, since the delay 114 is fixed, it can be used only in steady state. However, it is possible to generate wind pulses with an extremely inexpensive and compact circuit configuration, and in particular, it is possible to generate wind pulses by operating the time code signal demodulation circuit stably and reliably. It has certain characteristics.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing the configuration of the circuit of the present invention, Fig. 2 is a circuit system diagram showing an embodiment of the circuit of the invention, and Figs. 3 to 5 are respectively the circuit systems shown in Fig. 2. FIG. 6 is a circuit system diagram showing an example of a time code signal demodulation circuit, and FIG. 7 is a circuit system diagram showing an example of a pulse generation circuit previously proposed by the applicant. 1.34...Time code input terminal, 2.35...
Edge detection circuit, 3... gate circuit, 4... article f1
Setting circuit, 6... Counter, 7, 12... Latch circuit, 8... Oscillator, 10.13... Comparator, 1/I
, 23°40...RS flip-flop, 15.2=
1... Wind pulse output terminal, 20... Gate I-
Circuit means: two... first delay circuit, 22... second
Delay circuit, 29. 30... Monostable multivibrator (± normalization), 38... Wind pulse human power 1 Mizuko, 43... Demodulated data output terminal.

Claims (1)

[Claims] A pulse generation circuit that generates a window pulse for extracting a clock component of an input pulse train with a bit period T modulated by a bi-phase modulation method, which is obtained by detecting both rising and falling edges of the input pulse train. Gate circuit means to which an edge detection pulse is supplied, which unconditionally passes the edge detection pulse in an initial state and gate-outputs the edge detection pulse based on the wind pulse in a steady state; and an output of the gate circuit means. a first delay circuit which outputs a first delayed pulse which is supplied with a pulse and delayed by a fixed time of approximately T/4; and a first delay circuit which is supplied with an output pulse of the gate circuit and which is delayed by a fixed time of approximately 3T/4; a second delay circuit that outputs a second delayed pulse, and a circuit that generates and outputs an output pulse whose polarity is alternately inverted by being alternately supplied with the first and second delayed pulses as the window pulse. A pulse generation circuit characterized by: