JPS60261213A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To make a repeat frequency of a clock pulse high without damaging a basic performance and a stability of a pulse generating circuit by constituting a counter of a single circuit. CONSTITUTION:A clock from an oscillator 8, and a pulse to be modulated are inputted to a clock input terminal of an edge detecting circuit 2 of a pulse generating circuit, and an input termial 1, respectively, and a pulse of a clock width whose phase has been synchronized with rise and fall edges of the pulse to be modulated is outputted from the circuit 2. This output is provided to a gate circuit 3 and a condition setting circuit 4, gates the gate 3 by an output of the circuit 4 until the pulse with becomes stable, and passes through a detecting pluse. An output of this circuit 3 is inputted to a counter 21 through an invertor 5 and an AND circuit 20, and also inputted to the first and the second delaying circuits 22, 23. The detecting pulse is counted in an input period of a clock by this counter 21, and its output is processed by the circuits 22, 23 and an FF24. An output of this FF24 is inputted to the circuit 4, also outputted to an output terminal, and an operation of the circuit is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse generation circuit, and more particularly to a circuit for generating wind pulses necessary for demodulating time codes of a pie-phase modulation method for VTR editing.

Conventional technology When performing electronic editing on a VTR, various speed playbacks are used, such as image search using high-speed playback and scene confirmation using low-speed playback, but the time code is recorded as an absolute address on the magnetic tape. In this case, the editing accuracy and reliability of automatic editing can be improved. The time code for VTR editing is the American Society of Motion Picture and Television Engineers (SM).
An audio cue track on a magnetic tape and a time code based on the Baila-Nese mark modulation method, which is recorded and played back on an audio track, are used, as standardized by PTE. Here, the biphase mark modulation method is
When the bit information (data) is '1', the polarity is reversed at half the bit period T, and in the case of either '0' or '1', it is always reversed once at the beginning of each bit period. It is well known that the modulation method has a minimum reversal interval of magnetization of T/2 and a maximum reversal interval of T/2.

Therefore, in the above time code, a transition (level change) occurs at least at the beginning of each bit, and a clock component is extracted from the pulse (transition pulse or edge detection pulse) obtained by detecting the transition using a wind pulse. Furthermore, bit information can be demodulated by detecting the presence or absence of a transition in the middle of the clock.

Conventionally, two methods have been considered for demodulating the above-mentioned time code: a method of processing it as an analog signal and a method of processing it as a digital signal. The former detects a wind pulse from a serially transmitted time code to generate a sawtooth wave, determines the presence or absence of a transition in this waveform, and detects the bit II Q II, 1111.
This method demodulates +. On the other hand, the latter samples the time code at a sufficiently high frequency, generates a wind pulse through this processing, detects the presence or absence of a transition in the wind pulse, and determines the IQIZ1 of the bit.
This is a method for demodulating '1''. Of these two methods, the latter method that utilizes digital signal processing is currently often used as it provides high accuracy.

FIG. 7 shows a circuit system diagram of an example of a pulse generating circuit that utilizes the above-mentioned digital signal processing and was previously proposed by the applicant in Japanese Patent Application No. 106485/1985. In the figure, the time code input to input terminal 1 is supplied to edge detection circuit 2, where both the rising and falling edges are detected and then supplied to gate circuit 3 and condition setting circuit 4, respectively. Ru. The gate circuit 3 is supplied with the output signal of the condition setting circuit 4 as a gate pulse, and in the initial state (for example, before the magnetic tape of a VTR reaches a predetermined running speed), the output edge detection pulse of the edge detection circuit 2 is ignored. The edge detection pulse is selectively outputted depending on the conditions, and in the steady state, except during the dropout occurrence period, the edge detection pulse is gated out based on the output wind pulse.

The edge detection pulse taken out from the gate circuit 3 has its polarity inverted by the inverter 5 and is supplied to the clear terminal of the counter 6, while being supplied to the latch circuit 7 as a latch pulse. On the other hand, the high frequency oscillation pulse extracted from the oscillator 8 is sent to the edge detection circuit 2. are supplied to counters 6 and 9, respectively.

The n-bit digital signal indicating the count value of the counter 6 is supplied to the latch circuit 7, and after being latched there, the n-bit digital signal shifted by 2 bits in the SB (least significant bit) direction from its output terminal is output. The signal is taken out and supplied to the comparator 10. Therefore, the output signal of the latch circuit 7 indicates 1/4 of the count value of the counter 6. The comparator 10 compares the count value of the counter 6 and the output signal of the latch circuit, and when the two match, the signal becomes low level, for example, T/4i1! A delay pulse is generated to clear the counter 9, and is also supplied to the latch circuit 12 through the inverter 11, causing the latch circuit 12 to latch the count value of the counter 9 immediately before being cleared.

From the latch circuit 12, an n-bit digital signal obtained by shifting the input n-bit digital signal by 1 bit in the LSB direction, that is, a signal representing 1/2 of the count value of the counter 9 is taken out.

The comparator 13 is supplied with the 100 output signals of the counter 9 and the latch circuit 12, and when the two match, outputs a low level signal for a certain period of time, for example. RS flip-flop 1
4, both output signals of comparators 10 and 13 are supplied to its reset and set terminals. As a result, the Q output terminal of the flip-flop 14 falls after T/4 (where ■ is the bit period of the input time code of the input terminal 1) from the leading edge of the output edge detection pulse of the gate circuit 3, and 37 from the leading edge of the output edge detection pulse of gate circuit 3
rises after /4 (= (T/4)+-(T/2)),
A substantially symmetrical square wave with a period T is extracted and the wind pulse W
It is output as P to the output terminal 15 and is also supplied to the condition setting circuit 4.

Problems to be Solved by the Invention In the pulse generating circuit described above, the repetition frequency of the output oscillation pulse of the oscillator 8 must be selected to be at least twice the upper limit frequency of the input time code, and in order to improve accuracy. It is desirable that this oscillation frequency be higher. However,
If the above oscillation frequency is short, the counts of counters 6 and 9 within the same period T will be large, so counters 6 and 9 that can count many counts are required.
Furthermore, since two counter circuits are required, the circuit scale becomes large, which poses a problem in terms of circuit simplification and future large-scale integrated circuit (LSI) implementation.

Therefore, the present invention provides a pulse generating circuit that solves the above problems without losing the basic performance and circuit stability of the pulse generating circuit proposed above by configuring the counter with a single circuit. The purpose is to

Means for Solving the Problems FIG. 1 is a block system diagram showing the configuration of the present invention, and the same components as in FIG. 7 are given the same reference numerals.

In the figure, an input pulse train modulated by the pie-phase modulation method that enters an input terminal 1 is supplied through an edge detection circuit 2 to a gate circuit 3 and a conditional stage/constant circuit 4, respectively. The gate circuit 3 and the condition setting circuit 4 constitute gate circuit means, and as described above, in the initial state, the edge detection pulse is passed unconditionally, and in the steady state, the edge detection pulse is passed based on the output wind pulse. Gener output.

do. The output pulses of the gate circuit 3 are supplied as latch pulses to first and second delay circuit means 22 and 23, which will be described later, respectively, while being supplied to the clear terminal CL of a single counter 21 through an inverter 5 and an AND circuit 20, respectively. is applied to and clears it.

The AND circuit 20 logically ANDs the output pulse of the first delay circuit means 22 and the polarity inversion edge detection pulse from the inverter 5, and outputs the pulse to the clear terminal C of the counter 21.
, L. Here, in a steady state, when the output pulse of the inverter 5 is at a high level, the output pulse of the first delay circuit means 22 is at a high level as described later, so at least the polarity inversion edge detection pulse from the inverter 5 The counter 21 is cleared by this.

The counter 21 counts high frequency pulses from the oscillator 8 and supplies an n-bit digital signal representing the counted value to the first and second delay circuit means 22 and 23, respectively.

When the first delay circuit means 22 reaches a steady state, it generates a first delay pulse delayed by approximately 0.2 times the bit period T of the input pulse train at the input terminal 1, and outputs a first delay pulse to the reset terminal of the RS flip-flop 24. R and the AND circuit 20, respectively. At this time, in the steady state, the inverter 5
Since the output pulse of is at a high level, the above first
The delayed pulse is applied to the clear terminal OL of the counter 21 through the AND circuit 20 to clear it.

Further, when the second delay circuit means 23 enters a steady state, it generates a second delay pulse that is delayed for a period approximately 0.6 times the bit period T of the input pulse train of the input terminal 1, and transfers it to the flip-flop 24. while applying the voltage to the set terminal S of the first
It is also supplied to the delay circuit means 22 as an inhibit release signal. As a result, the Q output terminal of the flip-flop 24 falls when, for example, approximately 0.2T has elapsed from the leading edge of the output edge detection pulse of the gate circuit 3, and at the time when approximately 0.67 has elapsed from the leading edge. A square wave rising at is extracted, and this square wave is output as a wind pulse to the output terminal 25, and is also supplied to the condition setting circuit 4.

Operation The first delay circuit means 22 latches the counted value of the counter 21 at the leading edge of the output edge detection pulse of the gate circuit 3, and outputs an n-bit digital signal indicating the latched counted value to L.
A digital signal with a count value 1/4 times the latched count value obtained by shifting 2 bits in the SB direction and the inverter 5
The comparators compare the digital signals from the counter 21 after being cleared by the output pulse of , and when the two match, a match signal is generated and output as the first delayed pulse. The counter 21 is cleared at the trailing edge of the output edge detection pulse of the gate circuit 3, and is also cleared at the first delayed pulse. Further, the second delay circuit means 23
is 1 of the latched M value obtained by latching the count value of the counter 21 at the leading edge of the output edge detection pulse of the gate circuit 3, and shifting the n-bit digital signal indicating the latched count value by 1 bit in the LSB direction. The digital signal of /2 times the count value and the digital signal from the counter 21 are compared by respective comparators, and when the two match, a match signal is generated and output as a second delayed pulse.

As a result, the time interval from the time when the first delay pulse is output to the time when the edge detection pulse is output from the gate circuit 3 is stored in the counter 21 as the output pulse of the oscillator 8 even when the VTR is in fast forward mode 9 rewind mode or steady running mode. The signal is constantly measured by counting (sampling) the latch pulse, and the first delay circuit means 22 outputs the signal for a period of 1/4 times this time interval (approximately 0.2T period in a steady state) from the time when the latch pulse arrives. The delayed first delay pulse is taken out from the second delay circuit means 23 at 3/3 of the time interval.
A second delayed pulse delayed from the time of input of the latch pulse is taken out for a period of 4 (='(1/2>+ (1/4)) times (approximately 0.6 period in a steady state). As a result, there is only one counter 21 and the flip-flop 2
4, the required wind pulse can be generated and output. Hereinafter, the present invention will be described in more detail along with examples.

Embodiment FIG. 2 shows a circuit system diagram of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In Figure 2, Figure 3 (A) that has entered input terminal 1
A modulated pulse (time code signal) as shown in FIG.
For example, 2.
The pulse train shown in FIG. 2B is obtained by bi-phase mark modulating a 4 kHz carrier wave with digital data. As shown in Figure 4 (B), this modulated pulse causes a transition (level change) at the center below the bit period when the data shown at the top of the waveform is "1", and the data changes to "o". When no transition occurs within the bit period T, and the data is IQI+, 1
1111, a transition always occurs at each start position of each bit period T.

As shown in FIG. 2, the edge detection circuit 2 includes two stages of D flip-flops 26 and 27 connected in cascade, and
Each of the Q output terminals of the flip-flops 26 and 27 is connected to the input terminal of a two-man exclusive OR circuit 28, respectively. In addition, flip-flops 26 and 27
A high frequency oscillation pulse (for example, 4 MHz) from an oscillator 8 is supplied to each clock terminal. As a result, the exclusive OR circuit 28 outputs a pulse that is synchronized in phase with both the rising and falling edges of the modulated pulse input to the pano terminal 1, and a pulse corresponding to one cycle of the output oscillation pulse of the oscillator 8. An edge (transition) detection pulse having a width as shown in FIG. 3(B) is taken out and supplied to the gate circuit 3 and the condition setting circuit 4, respectively.

The condition setting circuit 4 has a reconfigurable circuit configuration as triggered by the edge detection pulse, and the condition setting circuit 4 maintains the initial state until a steady state is reached in which the pulse interval of the edge detection pulse becomes normal, or drops. When an out occurs, a high-level signal is always generated and output to set the gate circuit 3 in the "open" state and allow the edge detection pulse to pass unconditionally.However, for example, if the edge detection pulse shown in FIG. Assuming that the edge is missing at the position indicated by the broken line, even in a steady state, if the edge detection pulse does not arrive for a period of, for example, twice the bit period T or more, the time constant circuit in the condition setting circuit 4 Since the terminal voltage of the charging/discharging capacitor becomes below the threshold level L as shown in FIG. As shown in (C), the output signal becomes low level and the output signal becomes high level, causing the gate circuit 3 to be in the "open" state.

On the other hand, when the VTR is in a steady state, the terminal voltage of the charging/discharging capacitor is above the threshold level LiX, so the condition setting circuit 4 has an internal switching signal as shown in FIG. 5(C). As shown in the waveform before to, it is always at a high level, which causes
A wind pulse as shown in the figure is passed through and output to the gate circuit 3. Therefore, in the steady state, the gate circuit 3 is in an "open" state only during the high level period of the wind pulse, and blocks the passage of the input edge detection pulse during the low level period of the wind pulse. Therefore, when a modulated pulse (time code signal) as shown in FIG. 3 (A>) enters the input terminal 1 in a steady state, the output signal of the gate circuit 3 becomes as shown in FIG. 3 (C). .This gate circuit 3
The output signal of the latch circuit 2 in the first delay circuit means 22
9 and the latch circuit 31 in the second delay circuit means 23 as latch pulses, and is applied to the clear terminal CL of the counter 21 through the inverter 5 and the AND circuit 20, respectively.

The counter 21 is in the clear state when the signal applied to its clear terminal C becomes low level, and immediately after that, the oscillation pulse from the oscillator 8 entering the clock terminal rises from low level to high level. After that, the clear state is maintained while a low level signal is input to the clear terminal CL. Therefore, the counter 21 is kept in a clear state during the high level period of the edge detection pulse of the gate circuit 3 shown in FIG. 3(C). The counter 21 counts the output oscillation pulses of the oscillator 8 and outputs an n-bit digital signal (count value) to the latch circuits 29.31. Comparator 3
0 and 32, respectively.

The latch circuit 29 indicates the count value of the counter 21 latched at the rising edge of the edge detection pulse shown in FIG. 3(C).
An n-bit digital signal with a count value 1/4 times the latched count value obtained by shifting the bit digital signal by 2 bits in the LSB direction is output. On the other hand, the latch circuit 31 shifts the n-bit digital signal from the counter 21 latched at the rising edge of the edge detection pulse shown in FIG. Outputs an n-bit digital signal of /2 times the count value.

Comparators 30 and 32 are each constructed, for example, by a magnitude comparator. The comparator 30 outputs 1/4 of the count value of the counter 21 taken out from the latch circuit 29.
is compared with the value currently being counted by the counter 21, and when the two match, a low-level match signal is generated, which is supplied to its own inhibit terminal ■, and the flip-flop 24 outputs a low-level match signal. Reset terminal and AND circuit 2
0 respectively. Therefore, the comparator 30 enters the inhibited state immediately after the coincidence signal is output, and the inhibited state is canceled when a low-level set signal is input to the set terminal S, and thereafter, the input values of the two terminals match. At times, the match signal is output again, but in the inhibit state, even if the input values of the two terminals match, the match signal is not output, and the output signal remains at a high level. has been done.

The comparator 32 is the counter 2 latched by the latch circuit 31.
The value of 1/2 of the count value of 1 is compared with the value currently being counted by the counter 21, and when the two match, a low level match signal is generated, which is sent to the set terminal of the 7 soft-flop 24. S and also to the set terminal S of the comparator 30. The comparator 30 together with the latch circuit 29
The output coincidence signal is output as a first delayed pulse delayed by a period corresponding to approximately 0.2 times the value latched by the latch circuit 29. Similarly, the comparator 32 constitutes the second delay circuit means 23 together with the latch circuit 31, and the output coincidence signal is delayed for a period corresponding to approximately 0.6 times the value latched by the latch circuit 31. It is output as a second delayed pulse.

To explain the above delay time in more detail, it is assumed that the count value of the counter 21 is latched by the latch circuits 29 and 31, respectively, at the bit period T of the input time code signal. It is also assumed that a steady state time code is input to the input terminal 1. As a result, a digital signal with a value of T/4 is supplied from the latch circuit 29 to the comparator 30, and a digital signal with a value of T/4 is supplied from the latch circuit 31 to the comparator 3.
2 is supplied with a digital signal having a value of T/2.

Immediately after the latch circuit 29.31 latches, the counter 21 is cleared, and when a period of T/4 has elapsed from the first clearing point, a match signal is output from the comparator 30 and the counter 21 is cleared again. Ru.

When T/4 has elapsed since the second clearing of the counter 21, the values of the two input signals of the comparator 30 match, but since the comparator 30 is in the inhibited state, it does not output a matching signal, and the second clearing When T/2 has elapsed from the point in time (first
Comparator 32
A match signal is output, and the comparator 30 is released from the inhibited state. And 1. 3T from the second clear point
/4 (T from the first clear time), an edge detection pulse is output from the gate circuit 3, and the count value 3T/4 of the counter 21 at that time is latched by the latch circuits 29 and 31. Counter 21 is cleared. Therefore, from the latch circuit 29 to the comparator 30, 3T/1
A digital signal with a value of 6 is supplied, and a digital signal with a value of 3T/8 is supplied from the latch circuit 31 to the comparator 32. As a result, in the same manner as described above, a match signal is output from the comparator 30 and the counter 21 is cleared at the time point when 37/16 (→ρ, 19 frames) have elapsed from the third clear time point. A match signal is output from the comparator 32 at a time point when 3T/8 has elapsed from the fourth clearing time of the counter 21 (9T/16, that is, about 0.56 T has elapsed from the third clearing time). Then, since the edge detection pulse is output from the gate circuit 3 at the time when 13T/16 (from the third clear time) has elapsed from the fourth clear time, the latch circuits 29 and 31 calculate the current value of the counter 21. The value 13T/16 is latched, and immediately after that, the counter 21 is cleared by the edge detection pulse.

Thereafter, the same operation as above is repeated, and the value of the digital signal supplied from the two latch circuits to the comparator 30 finally converges to about 0.2T, and the value of the digital signal supplied from the latch circuit 31 to the comparator 32 is The value of the digital signal is approximately 0.4T
converges to. As a result, the comparator 30 outputs
), a first delayed pulse delayed from the output point of the edge detection pulse is extracted for a period approximately 0.2 times the pulse interval T of the output edge detection pulse of the gate circuit 3, while the comparator 32, as shown in FIG. 3(E), a second delayed pulse is delayed from the output point of the edge detection pulse by a period approximately 0.6 times the pulse interval T of the output edge detection pulse of the gate circuit 3. taken out.

As a result, this first. A second delay pulse is supplied to its reset and set terminals of the flip 70 knob 24.
From the output terminal, as shown in FIG. 3(F), from the time when the edge detection pulse is taken out from the gate circuit 3, the output voltage is about 0.
The pulse falls after 2T, and a pulse (square wave) with a period T having a low level period of about 0.4T and a high level period of about 0.6T is extracted. This pulse is output to the output terminal 25 as a wind pulse, and is also output to the condition setting circuit 4. This wind pulse is shown in Figure 3 (A).

As shown in (F), there is a phase relationship in which the rising edge of the input modulated pulse (time code) exists within the high level period.

Next, a demodulation circuit that demodulates a modulated pulse subjected to biphase mark modulation using the -C generated wind pulse will be described. FIG. 6 shows a circuit diagram of an example of this demodulation circuit.

In the figure, a biphase mark modulated time code signal inputted to an input terminal 34 is supplied to one input terminal of each of two-manual AND circuits 36 and 37 through an edge detection circuit 35. On the other hand, the wind pulse generated by the above-mentioned pulse generation circuit enters the input terminal 38, and after its polarity is inverted by the inverter 39, it is connected to the AND circuit 3.
6, and directly applied to the other input terminal of the AND circuit 37 and the clock terminal of the shift register 41, respectively, without polarity inversion.

As a result, when there is a transition in the middle of the bit period T of the input time code signal, an edge detection pulse that is phase synchronized with the transition is extracted from the AND circuit 36, and the RS flip-flop 40 is set. Further, edge detection pulses (clock components) at each start position of the bit period T of the input time code signal are taken out from the AND circuit 37, and the flip-flop 40 is reset. Therefore, the Q of flip-flop 40 is
A 2111i signal corresponding to the data of the input time code signal is taken out from the output terminal and is serially input to the data input terminal of the shift register 41 at the next stage.

The shift register 41 sequentially shifts the data obtained by sampling the signal applied to its data input terminal at the rising edge of the wind pulse applied to its clock terminal every time a wind pulse arrives, and stores the m bits of data. Output m pieces of data in parallel from the output terminal. The m-bit digital signal taken out after serial-to-parallel conversion by the shift register 41 is output as a demodulated signal to an output terminal 43, and is also supplied to a sync word detection circuit 42, where the sync word is detected. The sync word detection signal clears the shift register 41.

Note that the present invention is not limited to the above-described embodiments, and can be applied to time codes on tapes, disks, etc., such as digital audio systems that use digital signals to record and play back music signals, as well as video signals. can do. Furthermore, it can be applied to modulated pulses modulated by other biphase modulation methods such as biphase space modulation.

Effects of the Invention As described above, according to the present invention, since a single counter is configured to generate wind pulses, the repetition frequency of the clock pulse from the oscillator applied to the counting input terminal can be increased. However, compared to conventional circuits that use two counters, it can be constructed more easily and inexpensively, and it is therefore easier to implement into future large-scale integrated circuits. It has features such as being able to generate wind pulses that can operate the signal demodulation circuit stably and reliably.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of the circuit of the present invention, Figure 2 is a block diagram showing the configuration of the circuit of the present invention.
The figure is a circuit system diagram showing an embodiment of the circuit of the present invention, FIGS. 3 to 5 are signal waveform diagrams for explaining the operation of the circuit system shown in FIG. 2, and FIG. 6 is an example of a time code signal demodulation circuit. FIG. 7 is a circuit diagram showing an example of a pulse generation circuit previously proposed by the applicant. 1.34...Time code input terminal, 2.35...
Edge detection circuit, 3... Gate circuit, 4... Condition setting circuit, 6, 9.21... Counter, 7.12, 29
゜31... Latch circuit, 8... Oscillator, 10, 13
゜30.32...Comparator, 14,24.40...R
S flip 70 tube, 15.25... Wind pulse output terminal, 22... First delay circuit means, 23...
Second delay circuit means, 38... Wind pulse input terminal, 43... Demodulated data output terminal.

Claims (1)

[Claims] A pulse generation circuit that generates a wind pulse for handling a clock component of an input pulse train modulated by a pie-phase modulation method, the edge detection pulse being obtained by detecting both rising and falling edges of the input pulse train. is supplied, gate circuit means for passing the edge detection pulse unconditionally in an initial state and gate-outputting the edge detection pulse based on the wind pulse in a steady state; a single counter that is cleared by an inverted output; an oscillator that supplies a clock signal to the counter; and an output pulse of the gate circuit means to latch the output count of the counter, and approximately 1/1/2 of the latched count. The value of 4 is compared with the output count value of the counter after being cleared by the inverted output of the output pulse of the gate circuit means, and when the two match, the value is an abbreviation of the pulse interval immediately before the latch of the input pulse train. a first delay circuit means for outputting a first delay pulse delayed by 0.2 times the period to clear the counter; and a first delay circuit means for latching the output count value of the counter by the output pulse of the gate circuit means; Approximately 1/2 of the latched count value and the output count value of the counter are compared, and when the two match, the input pulse train is delayed for a period approximately 0.6 times the pulse interval immediately before the latching. second delay circuit means for outputting a second delayed pulse; and generating and outputting an output pulse whose polarity is alternately inverted when the first and second delayed pulses are alternately received as the wind pulse. A pulse generation circuit characterized by consisting of a circuit.