JPS59230354A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To absorb a counter error and a delay in a window pulse by generating the window pulse from a delay pulse being below and 3/4 in the biphase mark modulating system. CONSTITUTION:A prescribed high frequency signal is outputted from an oscillator 20 as a sample signal and an edge detection pulse passing through a gate circuit is impressed to clear terminal of a counter 21. Thus, a delay pulse outputted from a 1/4 delay circuit 24 is delayed from the edge detection pulse by <1/4 time and the pulse delayed by <3/4 time is outputted from a 1/2 delay circuit 26. Thus, a pulse waveform of opposite phase to that of the window pulse obtained by phase-inverting a Q output of an FF25 at an inverter is obtained and when the window pulse is at a high level and an edge detection pulse input exists, a decoding circuit outputs ''1'' level and when no pulse input exists, the decoding circuit outputs ''0'' level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse generation circuit, and more particularly to a circuit for generating wind pulses necessary for demodulating time codes of a pie-phase modulation method for VTR editing.

BACKGROUND TECHNOLOGY Conventionally, when performing electronic editing on a VTR, various speed playbacks are performed, such as image search using high-speed playback and scene confirmation using low-speed playback, but the time code is recorded as an absolute address on the magnetic tape. If so, the accuracy and reliability of automatic editing can be improved. The time code for this VTRg collection is the American Society of Motion Picture and Television Engineers (S.
A bi-phase mark modulation time code, which is recorded and played back on an audio cue track on a magnetic tape, is used, as standardized by MPTE.

Here, the biphase mark modulation method uses bit information (
When the data) is "1", the polarity is reversed at half the bit period T, and it is also reversed once between bits.The minimum reversal interval of magnetization is T/2, and the maximum reversal interval is the king. It is well known that this is a modulation method. Therefore, in the above time code, a transition (level change) occurs at least at the beginning of each bit, and a clock component is extracted from the pulse (transition pulse or edge detection pulse) obtained by detecting the transition using a wind pulse. Furthermore, bit information can be demodulated by detecting the presence or absence of a transition in the middle of the clock.

Conventionally, two methods have been considered for demodulating the above-mentioned time code: a method of processing it as an analog signal and a method of processing it as a digital signal. The former method detects a wind pulse from a serially transmitted time code to generate a sawtooth wave, determines the presence or absence of a transition in this waveform, and demodulates the pid IQIZI "1". On the other hand, the latter samples the time code at a sufficiently high frequency, generates a wind pulse through this processing, detects the presence or absence of a transition in the wind pulse, and determines the bit l Q I+, "1'". This is a demodulation method. Among these two methods, currently,
The latter method, which utilizes digital signal processing, is often used because it provides high accuracy.

FIG. 1 shows a circuit diagram of an example of a conventional demodulation circuit based on a digital signal processing method. In the same figure, Figure 2 (A
The time code (input signal) shown in ) is modulated using the bi-phase mark modulation method, and is sent to the edge detection circuit 2.
, where each of its rising and falling edges (
transition) is detected and converted into a detection pulse as shown in FIG. 2(C), which is then supplied to a gate circuit 3 and a decoding circuit 4, respectively. The gate circuit 3 is configured to generate a gate output by a pulse having a phase opposite to the wind pulse from the inverter 5, and the output pulse from the inverter 5 is applied to the clear terminal of the counter 7 through the inverter 6.

On the other hand, a high frequency sampling signal from an oscillator (not shown) enters the input terminal 8 and is supplied to the counter 7. Counter 7 counts the number of sampling signals after clearing, detects the count output, and wind pulse generation circuit 9
Output to. The detection and wind pulse generation circuit 9 calculates 1 of the maximum inversion interval T of the input signal from the count output of the counter 7.
A pulse train delayed by a time of /3 and a pulse train delayed by a time of 2/3 are generated, and a signal as shown in FIG. 2(B) is generated and output from these pulse trains. The output signal of this circuit 9 is supplied as a wind pulse to the decoding circuit 4, and is also supplied to the gate circuit 3 through the inverter 5. As a result, when the edge detection pulse from the edge detection circuit 2 comes in from the decoding circuit 4 during the window pulse incoming period, it is 1" data, and when it does not, it is decoded as 10" data. The (demodulated) signal is output to the output terminal 10.

6- Problems to be Solved by the Invention However, the detection and wind pulse generation circuit 9 in the above circuit calculates the pulse interval, extracts the time interval, and outputs a delay time of 1/3.2/3 of the time interval. Since a circuit is required to generate the , there are problems in that the circuit becomes large-scale and at the same time becomes relatively expensive.

Therefore, the present invention solves the above problem by generating delayed pulses that are less than 1/4 times the pulse interval of the input signal and delayed pulses that are less than 3/4 times the pulse interval of the input signal, and generating wind pulses from these. The purpose is to provide a pulse generation circuit that solves the problem.

Means for Solving the Problems The present invention is a wind pulse generation circuit used for detecting the clock interval of an input pulse train modulated by a bi-phase modulation method, which detects the rising and falling edges of the input pulse train. An edge detection pulse obtained by detecting both edges is supplied through a gate circuit, the pulse interval immediately before the edge detection pulse is measured, and a pulse delayed by less than 1/4 times the measured value is generated and output. 1 delay circuit, the output delay pulse of the first delay circuit is supplied, the pulse interval of the immediately preceding delay pulse is measured, and the pulse interval of the immediately preceding delay pulse is further measured for a time less than 1/2 of the measured value with respect to the input delay pulse. A second delay circuit generates and outputs delayed pulses, and both output delay pulses of the first and second delay circuits are supplied, and when these two delay pulses come in and out alternately, the polarity of the output signal alternates. The device is constructed of a pulse state shift circuit that inverts the pulse state, and one embodiment thereof will be described below with reference to FIG. 3 and the subsequent drawings.

Embodiment FIG. 3 shows a circuit system diagram of an example of a time code demodulation circuit that corresponds to the circuit of the present invention. In the figure, the time code inputted to the input terminal 11 and modulated by the bi-phase mark modulation method is detected by an edge detection circuit 12 at both its rising and falling edges (transitions), and is converted into an edge detection pulse. After being converted, the gate circuit 13. The signal is supplied to an initial operation circuit 14 and a decoding circuit 18, respectively. The initial operation circuit 14 is connected to the gate circuit 1 by the inverter 17, which will be described later.
At the initial stage until the pulse that makes the gate "open" state is taken out, the edge detection pulse generates a gate pulse to allow it to pass through the gate circuit 13 unconditionally, and the output gate pulse is passed through the OR circuit 15 to the gate circuit 13. 13.

The edge detection pulse taken out from the gate circuit 13 is supplied to the wind pulse generation circuit 16, where it is converted into the above-mentioned wind pulse. The polarity of the wind pulse is inverted by the inverter 17 and ORed as a gate pulse.
The signal is supplied to the gate circuit 13 through the circuit 15, and is also supplied to the decoding circuit 18, where it is used to extract the clock component of the edge detection pulse from the edge detection circuit 12. The decoding circuit 18 further discriminates whether or not there is a transition during the pulse interval of this clock, decodes (demodulates) the bit information, and outputs the decoded signal to the output terminal 19. It is assumed that the gate circuit 13 is controlled to be in the gate "open" state during the high level period of the output pulse of the OR circuit 15, and to be in the gate "closed" state during the low level period.

The present invention relates to a circuit related to the wind pulse generating circuit 16 shown in FIG. 3, and FIG. 4 shows a block diagram of an embodiment of the present invention. In the figure, a predetermined high frequency signal is taken out from an oscillator 20 as a sampling signal, and this sampling signal is sent to a first counter 21 and a second counter 2.
2 is applied to each count input terminal and counted as 4. On the other hand, the counter 21 is cleared by applying the edge detection pulse that has passed through the gate circuit 13 to its clear terminal via the input terminal 23. The count value output signal of the counter 21 is supplied to a 1/4 delay circuit 24, which generates and outputs a delayed pulse delayed by a certain period of time less than 1/4 times the pulse interval of the immediately preceding edge detection pulse. This delayed pulse is applied to the clear terminal of counter 22 while flip 70
It is applied to the set terminal of knob 25, and its rising edge puts it in the set state.

Further, the count value output signal of the counter 22 is transmitted to the 1/2 delay circuit 2.
6. The 1/2 delay circuit 26 generates and outputs a pulse that is further delayed with respect to this delayed pulse for a certain period of time less than 1/2 of the pulse interval immediately before the output delayed pulse of the 10-1/4 delay circuit 24, and An output delay pulse is applied to the reset terminal of flip-flop 25. As a result, the flip-flop 25 is connected to the 1/4 delay circuit 24.
is set at the rising edge of the 1/2 delay circuit 26 and reset at the rising edge of the 1/2 delay circuit 26, thereby generating pulses in which the polarity of the output signal is alternately inverted, and this pulse is outputted to the output terminal 27 as a wind pulse. .

Here, "set" means the rising edge of a pulse, and "reset" means the falling edge of the pulse.

Here, the delay period of the 1/4 delay circuit 24 is set to 1/4 of the pulse interval of the input edge detection pulse, and the delay period of the 1/2 delay circuit 26 is set to the pulse interval of the output delay pulse of the 1/4 delay circuit. It is also conceivable to make the interval 1/2, and in this case, the circuit configuration can be simplified compared to the case where each delay circuit of <1/3.2/3 is used as in the circuit shown in FIG. can. However, in this case, there is a problem that the frequency may be locked to a predetermined frequency. That is, if the time code input to the input terminal 11 shown in FIG. 3 has a waveform as shown in FIG.
In the case shown by bl in Fig. 5(C), a pulse having a phase opposite to the wind pulse at the output end of the inverter 17 occurs as shown in Fig. 5(C).
As shown in the figure, there are cases where the signal does not rise, and instead rises with a delay of time τ from time t1.

This is a problem that almost always occurs when a delay of 1/4 or 1/2 times the exact pulse interval is obtained due to delays in the circuit's output circuit, detection circuit, etc. In such a case, the edge detection pulse b1 is blocked by the gate circuit 12, and the next edge detection pulse b2 is
is output from the gate. As a result, the 1/4 delay circuit 24
If it is assumed that the pulse output is delayed by exactly 1/4 times the edge detection pulse interval, the counter 21 will be cleared when the next edge detection pulse b3 is generated, so the edge detection pulse b2 and A pulse delayed by a period 1/4 times the pulse interval with b3 is output as shown by dl in FIG. 5(D). As a result, the output of the delay circuit that is delayed by 1/2 the pulse interval of the delay pulse is the fifth pulse.
As shown in figure (E), flip 70 knob 25
As a result, the pulses taken out to the output terminal of the inverter 17 become pulses locked to a period equal to the maximum inversion interval of the time code, as shown in FIG. 5(C).

Further, if the count value immediately before the counters 21 and 22 are cleared is, for example, "15", the value of 1/4 thereof is "3".

The value of 1/2 is "7", which is "3" respectively.

The occurrence of an error of "1" may also be a problem,
This jitter becomes a problem.

Therefore, in the present invention, as described above, the 1/4 delay circuit 24
The delay time is 1/4 of the pulse interval of the edge detection pulse.
The delay time of the 1/2 delay circuit 26 is set to a constant value less than 1/2 times the pulse interval of the 1/4N extended pulse. FIG. 6 shows a 13-block system diagram of an embodiment of the main part of FIG. 4. In the figure, the counter 22 counts the high frequency sampling signal inputted from the input terminal 28, and counts the 1/4 delay circuit 24 inputted to the input terminal 29.
Cleared by output delay pulse. In addition, the latch circuit 30 and the -number output circuit 31 are each 1/2 Takumi Nobu circuit 26
It consists of

The latch circuit 30 is configured to latch the counted value output signal of the counter 22 by a delayed pulse inputted to the input terminal 29. Latch.

The latch circuit 30 also sets the latched 7-bit count value to 1.
Bit L S, bit shift towards B direction and 0 to MSB
Out of a total of 8-bit count value to which is added, a 5-bit count value output excluding the most significant bit (MSB), LSB, and 1 bit above the most significant bit (MSB) is supplied to the coincidence detection circuit 31. - In the number output circuit 31, the 2 bits on the LSB side of the 8-bit input from the latch circuit 30 are always logic 110.
It is configured so that the I+ signal is applied, and the 5-bit count value excluding these 214- bits and the MSBI bit, and the corresponding 5-bit count value of the 8-bit count value output signal from the counter 22. and when they match, a match detection signal, that is, 1/2N, is sent to the output terminal 32.
Outputs extended pulses.

This will be explained in more detail with reference to FIG.
From the top to the bottom of FIG. 7, the 8-bit count value output of the counter 22 sequentially increases by 1, and when the 40th sampling signal comes in, the count value becomes 1-00100111J.
Assuming that a delayed pulse enters the input terminal 29 at the time when Immediately after, the counter 22 is cleared and becomes all rOJ. Here, the latch circuit 30 latches (directly, it becomes 1/2 of the count value immediately before the counter 22 is latched, which is 1/2 of the pulse interval of the delay pulse immediately before the 1/4 delay circuit 24). It shows the period.

The coincidence detection circuit 31 detects the 2 bits on the LSB side of the count value latched by the latch circuit 30, and also the MS81
The 5-bit r 00100J with the bit removed is compared with the corresponding 5 bits of the 8-bit count from the counter 22. As a result, the - number construction circuit 31 outputs the counter 2.
A delay pulse is generated when the count value of 2, which is the upper 2 bits on the MSB and LSB sides, becomes 00100J.

Therefore, in this embodiment, the 8-bit count value [0001
Compared to January 00 (shown by the arrow and 1/2 in Figure 7), the delay pulse is generated earlier by three sampling signal valves, and a delayed output can be obtained for less than 1/2 the period. .

This means that the predetermined 5 bits shown in FIG.
This means that errors (jitter) within the count value range of 00100J and delays in the timing of wind pulse generation can be absorbed.

Similarly, the 1/4 delay circuit 24 can also be constituted by a circuit section corresponding to the latch circuit 30 and the -number output circuit 31 in FIG. However, in that case, the latch circuit is latched by the output edge detection pulse of the gate circuit 13, and the upper 6 bits r001001J of the count value immediately before clearing of the counter 21 are shifted 2 bits toward the LSB, and the upper 2 bits are set as rOJ. Count value [0000100
Latch 1J (or latch the lower 6 bits excluding the upper 2 bits "0"). This count value corresponds to a period of 1/4 of the pulse interval of the immediately preceding edge detection pulse.

Then, the - number construction circuit outputs at least the 4-bit value r0OIOJ excluding the lower 2 bits of the above-mentioned 6-bit count value latched by the latch circuit, and the corresponding 4-bit value of the output count value of the counter 21. (a 4-bit value excluding the upper 2 bits and lower 2 bits), and when they match, that is, the count value of the counter 21 is f' 0000.
When it reaches 1000J, a 1/4 delay pulse is generated as shown in FIG.

The 1/4 delayed pulse is output from the above coincidence detection circuit because the 8-bit count value of the counter 21 [00<
Compared to 1o1001J (indicated by an arrow and 17-1/4 in FIG. 7), a delayed pulse can be obtained earlier by one sampling signal. In this way, a delayed pulse with a period less than 1/4 times as long as that shown in FIG. 6 can be obtained. In addition, in this case, the coincidence output can be obtained in the negative number construction circuit by the upper two of the 8-bit count value output of the counter 21.
The value of the 4 bits excluding the total of 4 bits, ie, the bit and the lower two bits, is "0010", which is within the count value range shown by ■ in FIG. 7, so that jitter and the like can be absorbed.

In the embodiment shown in FIG. 6, in order to output the delayed pulse at a time timing earlier than the exact 1/2 (or 1/4) period detection point by the sampling signal, the lower two of the count value output is Although bits are discarded and coincidence detection is performed at a frequency 1/4 times the sampling signal frequency f, it is also possible to discard the lower three or more bits. Furthermore, the sampling signal should be at least 100 times as accurate as the modulation signal.

In this manner, according to this embodiment, when a pulse (time code) modulated by the biphasic modulation method as shown in FIG. 8(A) is input to the input terminal 11, the edge The detection circuit 12 outputs edge detection pulses that are phase-synchronized with both the rising and falling edges of the time code, as shown in FIG. 2B. When the output delay pulse of the 1/2 delay circuit 26 is generated and the output of the inverter 17 becomes high level, the gate circuit 13 is turned on.
8 (C) from the gate circuit 13.
) is output from the gate.

As a result, the output delayed pulse of the 1/4 delay circuit 24 is delayed for a period less than 1/4 times the pulse interval of the edge detection pulse and is taken out, as shown in FIG. 8(D). Further, as shown in FIG. 8(E), the output delayed pulse of the 1/2 delay circuit 26 is further delayed with respect to the 1/4 delayed pulse for a period less than 1/2 of the pulse interval of the 1/4 delayed pulse. It is taken out. As a result, a pulse waveform having a phase opposite to that of the wind pulse obtained by inverting the phase of the 6 outputs of the flip 70 or the Q output by the inverter 17 becomes as shown in FIG. 8(F). The decoding circuit 18 outputs bit information 11111. when there is an edge detection pulse input from the edge detection circuit 12 while the wind pulse is at a high level. When there is “
A demodulated signal of 'O'' is output.

In addition, in the above embodiment, an example in which the present invention is applied to a bi-phase mark modulation method has been described, but the present invention is not limited to this, and can be applied to other bi-phase modulation methods (for example, a bi-phase space modulation method). can.

Effects As described above, according to the present invention, the first delayed pulse is delayed for a period less than 1/4 of the pulse interval immediately before the edge detection pulse, and the first delayed pulse is delayed for a period less than 1/4 of the pulse interval immediately before the first delayed pulse.
We tried to generate a more wind pulse with a second delayed pulse delayed for less than twice the period, so exactly 1/4 times the pulse interval.

A delay pulse can be generated at a time timing earlier than the delay point of 1/2 the period, which can absorb the counter error (jitter) and the delay of the wind pulse, and locks to a frequency other than the specified one. In addition, the coincidence detection circuit can be configured so that it is not necessary to detect the signal of the lower two or more bits of the output count value of the latch circuit. Therefore, the circuit configuration is not complicated, and the size is reduced to 1/3. Compared to conventional circuits having a 2/3 delay circuit, this circuit has the advantage of having a simpler circuit configuration.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a time code demodulation circuit having a conventional pulse generation circuit, and Figures 2 (A) to (C)
are a timing chart for explaining the operation of FIG. 1, FIG. 3 is a circuit diagram showing an example of a time code demodulation circuit having the circuit of the present invention, and FIG. 4 is a block diagram showing an embodiment of the circuit of the present invention. 5(A) to 5(E) are timing charts for explaining the operation when a malfunction occurs, FIG. 6 is a block system diagram showing an embodiment of the main part of the circuit of the present invention, and FIG. 7 is a diagram showing the count value of the counter. 8A to 8F are timing charts for explaining the operation of FIG. 321 and FIG. 4, respectively. 1.12...Time code input terminal, 4,18...
Decoding circuit, 8, 28... sampling signal input terminal,
9...Detection and wind pulse generation circuit, 10°19
... Demodulation signal output terminal, 16 ... Wind pulse generation circuit, 20 ... Oscillator, 21 ... First counter, 22 ... Second counter, 23 ... Edge detection pulse input terminal , 24...1/4 delay circuit, 25...
Flip 70 tube, 26...1/2 delay circuit, 27.
... Wind pulse output terminal, 29 ... Delay pulse input terminal, 30 ... Latch circuit, 31 ... Coincidence detection circuit, 32 ... Delay pulse output terminal. 22-

Claims (1)

[Claims] (1) A wind pulse generation circuit used to detect the clock interval of an input pulse train modulated by a bi-phase modulation method, which generates wind pulses obtained by detecting both rising and falling edges of the input pulse train. a first delay circuit to which a detection pulse is supplied through a gate circuit, measures a pulse interval immediately before the edge detection pulse, and generates and outputs a pulse delayed by a time less than 1/4 of the measured value; A second circuit that is supplied with the output delayed pulse of the delay circuit, measures the pulse interval of the immediately preceding delayed pulse, and generates and outputs a pulse that is further delayed by a time less than 1/2 of the measured value with respect to the input delayed pulse. a delay circuit, and a pulse state shift circuit to which both output delay pulses of the first and second delay circuits are supplied, and the polarity of the output signal is alternately inverted when the two delay pulses are received alternately. A pulse generating circuit comprising: a pulse generating circuit configured to output an output pulse of the pulse state shift circuit to the gate circuit as a gate pulse and also as the window pulse. (2) The first delay circuit includes a first counter that is cleared by the edge detection pulse and counts a constant frequency sampling signal from the oscillator, and a count output value of the first counter that is cleared by the edge detection pulse. a first latch circuit that latches the count value of the first counter and the first latch circuit;
and a first value that is less than 1/4 times the output value of the latch circuit, respectively, and generates a first delayed pulse when the counted value becomes equal to the first value. The second delay circuit includes a second counter that is cleared by the first delay pulse and counts the sampling signal, and a second counter that is cleared by the first delay pulse and counts the sampling signal. A second latch circuit that latches the count output value compares the count value of the second counter with a second value that is less than 1/2 of the output value of the second latch circuit, and 2. The pulse generation circuit according to claim 1, further comprising a second coincidence detection circuit that generates a second delayed pulse when the numerical value becomes equal to the second value.