JPS616921A - Digital filter device - Google Patents

Abstract

PURPOSE:To decrease the memory capacity by setting a filter characteristic of a digital filter circuit with a multiplication coefficient read from a coefficient memory so as to reduce the calculation and write job of the multiplication coefficient stored in the memory in advance. CONSTITUTION:A bus 2 is connected to a main miroprocessor 1. A memory (RAM) 3 is an accessory of the main microprocessor 1. The operation of a coefficient table memory 5 and a microprocesor 6 for coefficient operation are controlled by the main microprocessor 1. A coefficient memory 7 stores a coefficient obtained from the memory 5 and the microprocessor 6. A digital audio signal processing circuit 8 incorporates a digital filter circuit, the frequency characteristic of a signal fed to an input terminal 9 is changed and a digital audio signal is obtained at output terminals 10L, 10R. Then the multiplication coefficient stored in the coefficient memory 7 is read and given to the multiplier of the digital filter circuit section.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital filter device suitable for application to professional digital mixing consoles and the like.

BACKGROUND TECHNOLOGY AND PROBLEMS In a conventional digital mixing console for business use, a plurality of multiplication coefficients for each multiplier of the digital filter circuit of the digital filter device of the equalizer section are stored in memory in advance, and the desired The multiplication coefficients stored in the memory are selected and read out according to the filter characteristics, and the read multiplication coefficients are applied to each multiplier.

However, if the configuration of the digital filter circuit is complex and a large number of filter characteristics can be arbitrarily selected, the calculation and writing of the multiplication coefficients to be stored in memory in advance becomes extremely complicated, and the multiplication coefficients A memory with a large storage capacity is required to store the information.

Purpose of the Invention In view of the above, the present invention reduces the work of calculating and writing the multiplication coefficients to be stored in the memory in advance, even though a large number of filter characteristics can be selected. This paper attempts to propose a digital filter device that requires less capacity.

Summary of the Invention A digital filter device according to the present invention includes: a digital filter circuit formed by connecting a plurality of types of digital filter circuit units; a coefficient memory that stores multiplication coefficients to be applied to each multiplier of the plurality of types of digital filter circuit units; A main microprocessor, a coefficient calculation microprocessor that calculates the multiplier coefficients of each multiplier in the second-order or lower filter circuits among the plurality of types of digital filter circuits, and a third-order multiplier among the plurality of types of digital filter circuits. It has a coefficient table memory in which the multiplication coefficients of each multiplier of the filter circuit section are stored, and a filter characteristic control input device. The multiplication coefficients calculated by the coefficient calculation microprocessor and the multiplication coefficients read from the coefficient table memory are stored in the coefficient memory, and the multiplication coefficients read from this coefficient memory are applied to each multiplier of the digital filter circuit. Accordingly, the filter characteristics of the digital filter circuit are set.

According to the present invention, although a large number of filter characteristics can be selected, the work of calculating and writing the multiplication coefficients stored in the memory in advance can be reduced, and the capacity of the memory for storing the multiplication coefficients can be reduced. A digital filter device can be obtained.

EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an outline of an embodiment in which a digital filter device according to the present invention is applied to a professional digital mixing console (11 is a main microprocessor;
(2) shows a bus connected to this main microprocessor (1). (3) is a memory (RAM) attached to this main microprocessor. (4) is a filter characteristic control input device, which has a switch and a volume as described later. (5) is the coefficient table memory (R
OM (but also RAM) whose reading is controlled by the main microprocessor (1). (6) is a microprocessor for calculating coefficients, and its calculations are controlled by the main microprocessor (1).

(7) is a coefficient memo IJ (RAM) that stores the coefficients written by the coefficient table memory (5) and the coefficient calculation microprocessor (6), and has two storage areas (7A), ( 7B), under the control of the main microprocessor (1), a changeover switch (7Si)t
By switching (7S2), when writing is being performed in one area, reading is performed from the other area.

These memories (3), filter characteristic control input device (4)
The coefficient table memory (5), the coefficient calculation microprocessor (6), and the coefficient memo (January 7) are all manufactured by Nokusu (
2).

(8) is a digital audio signal processing circuit.

This digital audio signal processing circuit (8) has a built-in digital filter circuit, which will be described later, and an input terminal (9).
A digital or analog media signal fed to the
The frequency characteristics of the left and right audio signals (including the left and right audio signals) are changed, and the output terminals (IOL) and (IOR) are provided with the digital audio signals of the left and right channels with the desired frequency characteristics.
It is designed so that a radio signal can be obtained. Then, the multiplication coefficients stored in the coefficient memory (7) are read out and applied to each multiplier of each digital filter circuit section of the digital filter circuit (described later) of this digital audio signal processing circuit (8).

Note that the coefficient calculation microprocessor (61) can also be used as the main microprocessor (1).

In the digital audio signal example of FIG. 1 described above, FIG. 2 shows a low-frequency cut filter section LCF and a high-frequency cut filter section H.
CF, high band equalizer filter section HBF, low band equalizer filter section LEF, mid band equalizer filter section MEF
It consists of In this example, for example, the low-pass cut filter LCF is replaced with a third-order filter, and the high-pass cut filter H is replaced with a third-order filter.
The CF is made up of a fourth-order filter, and the high-pass, low-pass, and middle-pass equalizer filters HEF, LEF, and MEF are all made up of second-order filters.

(9) are input terminals for digital or analog audio signals; input terminals (91) + (92) to which two types of digital audio signals are supplied, input terminals (93) to which line input audio signals are supplied, and a microphone. It consists of an input terminal (94) to which an input audio signal is supplied. 02) is connected to these input terminals (91) to (
A selector for selecting an input signal supplied to the filter characteristic control input device (94), which is controlled by the filter characteristic control input device (41) shown in FIG. By selectively pressing the switch buttons C2 to (c) provided on the panel (211), a signal from any one of the input terminals (91) to (94) is selected by the selector a21, and the input terminal (
It is supplied to I31. In addition, an input terminal (93).

(94) and selector 0Z, there is an A/D converter (1,
13).

(114) has been inserted.

The input digital audio signal from the input terminal (131) is supplied to a multiplier 04 with a multiplication coefficient of 2, and its output is outputted by the switch button 26+ of the filter characteristic control input device panel (211) of FIG. Each time it is pressed, it is supplied to a multiplier a9 which cuts it to 1, -1.1, -1.Then, the output of this multiplier (15) is supplied to a low-pass cut filter section LCF.

The multiplication coefficients of the multipliers (141, Q51) are stored in the memory (5
) is stored in advance.

This low-pass cut filter section LCF is a multiplier M+.

~M17, delay/delay circuits D1o~D14 with a delay amount of one sampling period, and an adder AlO+AlI, and each multiplication coefficient of the multipliers M16~M17 is stored in advance in the memory (5). has been done. The output of the low cut filter LCF is supplied to the high cut filter HCF.

This high-frequency cut filter HCF has a multiplier M2 (1 to M
2g and a delay circuit D20 with a delay amount of 1 sampling period.
~D24, and adder A20. Similarly, the multiplication coefficient of the multiplier M2 o = Mz 9 is stored in advance in the memo January 5).

By switching SW2 in FIG. 3, it is determined whether the output of the high-frequency cut filter HCF is supplied to the continuation circuit of the multi-plate, low-frequency and middle-frequency equalizer filters HEF', LEF, and MEF, which will be described later. Ru. When the output of the high-frequency cut filter HCF is not supplied to the equalizer filter section, the switches rl and S'w2 are switched to the opposite state as shown in the figure, and the output is transferred to the multiplication coefficient via the changeover switch item 1. It is supplied to the multiplier (16) of 2-6, and its output is further supplied to the channel A fader volume heir (4) of FIG. 3 via the changeover switch Sw2.
Multiplication in which the volume is increased by 8flJ II and the multiplication coefficient is varied by operating G+, '2:'i [t8
1. The output of the multiplier X unit a81 is supplied to the multipliers o1 and (20) whose coefficients are changed so that the level ratio of the left and right channels is varied by the operation of the panpot volume knob (49) shown in FIG. Each output has left and right audio signal output terminals (IOL), (IO
R). Furthermore, these multipliers (LEA, G
IN, (11 and Kan's coefficients are stored in advance in the memo 51. Also, when the switches SW1 and SW2 are switched as shown in the figure, the output of the high-frequency cut filter section HCF is transferred via the changeover switch Sv1. High frequency equalizer filter section HEF K is supplied.

This high frequency equalizer filter section HEF includes a multiplier M3. ″
- M34 and a delay circuit D3o with a delay amount of one sample period.
~D33, and adder A3. It consists of

Multiplier M3. Each of the multiplication coefficients .about.M34 is calculated by the microphone processor f6+ of FIG. The output of this high frequency equalizer filter section HEF is supplied to the low frequency equalizer filter section LEFK.

This low-pass equalizer filter section LEF includes a multiplier M40
% M44 and delay circuit D with delay amount of 1 sample period
40 to D43 and an adder A40.

The multiplication coefficients of multipliers M4o-M44 are calculated by the microprocessor (6) of FIG. The output of the low-pass equalizer filter section LEF is the mid-pass equalizer filter section M.
Supplied to EF.

This mid-range equalizer filter section MEF is a multiplier 60)
~6a and the delay circuit D50 whose delay is 1 sample period
~D53, and an adder A50. Multiplier M
The multiplication coefficient of so-M54 is calculated by the microprocessor (6) of FIG.

Next, the operation panel G of the filter characteristic control input device (4)!
11 will be explained. Switch button (2) has already been explained, so we will omit it, and press the remaining switch buttons (2) to ().
35) will be explained.

The filter characteristics of the above-mentioned low-pass equalizer filter section LEF can be switched between a shelving type and a presence type, and this is done by pressing the switch buttons Zeng and Han. Similarly, the filter characteristics of the high frequency equalizer filter section HEF can be switched between shelping type and presence type.
This is done by pressing the switch buttons ■ and Ot+wo. Note that since the filter characteristics of the mid-range equalizer filter section MEF are only of the presence type, no changeover switch is provided.

In addition, the high-frequency cut filter section HCF controls the degree of inclination of the inclination part of the filter characteristic by pressing the switch button (3'1le).
nf) -12dB10CT and -18dBl by operation
I am trying to switch to oCT. Similarly, the slope of the filter characteristic of the low-frequency cut filter section LCF can be changed by 12 dB by operating the switch button (341, (to)).
It is designed to switch between 10CT and 18dB/1)CT.

Next, volume will be explained. Since the volume heirs (c) and (c) have already been explained, the remaining volume heirs 06) to (44) will be explained. The volume heir is for varying the cutoff frequency of the low frequency cutoff section LCF in the range of 30Hz to 960Hz. The volume controller c3D sets the cutoff frequency of the high-frequency cut filter section HCF to 0.55)G(z~1
It can be varied within a range of 8.0 KHz. The volume heirs C3S and C31 each have a center frequency of 2O-100O in the low-pass equalizer filter section LEF.
I-(variable between z, level from -12dB to +12dB
It is variable within a range of dE3. Also, the volume control (to).

In G, the center frequency is varied in the range of 0.5 KHz to 16 KHz, and the level is varied in the range of -12 to +12 dB in the high frequency equalizer filter section HEF. The volume heirs (42 to 0 (A) each have a center frequency of 0 in the mid-range equalizer filter section MEF.
．． Variable in the range of 1KHz to 100-, level -12
It can be varied in the range of ~ +12 dB, and the Q can be varied from 0.25 to 8.
It is made to be variable within a range of 0. The details of the scale of the volume 441 that varies the Q of this mid-range equalizer filter section MEF are shown in FIG. 5
97, 1.424, and 3.398 at equal intervals.

I will briefly explain how to scale the Q value. That is, the scale is attached so that it is linear with respect to og (q), the maximum value of Q is Qm, a x, the minimum value is Qmin, and the relative distance of a certain position with the scale is When the value is 1), the value Qv of Q at the distance vQ is obtained by the following equation.

Thus, as shown in FIG. 4 above, QrrLin
is 0.25 and 0.25 is 8, and the space between them is divided into four equal parts, and a value of Q is assigned to each divided point to form a scale.

Next, the operation and function of the digital filter device shown in FIGS. 1, 2, 3, and 4 will be explained with reference to the flowchart in FIG. 5. First, on the panel (211) of the filter characteristic control input device in FIG. 3, the flow is divided into left and right depending on whether the switch button is pressed or the volume heir is operated. If none of them are operated, the process returns to point A next to the "start" and it is determined whether the switch button has been pressed again or whether the volume heir has been operated.

First, when the switch button is pressed, the flow shifts to the right side. First, 12dB10CT is selected as the filter characteristic of the low-pass cut filter section LCF, or 18dB
Depending on whether 10cI' is selected, or whether -12dB/l)O'r or -1saB10CT is selected as the filter characteristic of the high-cut filter section HCF, the corresponding basic multiplication coefficient is B is selected and read from the coefficient table memory (5) in Figure 1.
transition to a point.

Also, whether the shelping type or the presence type was selected as the filter characteristic of the low frequency equalizer filter section LEF, and whether the shelping type was selected as the filter characteristic of the high frequency equalizer filter section HEF, or the presence type was selected. The corresponding basic multiplication coefficient is calculated depending on whether the point B is reached or not.

In addition, the input mode is set depending on which input selection switch button q9 in FIG. 3 is pressed, and the above-mentioned A
transition to a point. Phase switch button white in Figure 3)
Each time you press , 1 and -1 are alternately output from the device (41) and written into the coefficient memory (7) in Figure 1. Each time you press equalizer switch button C7 in Figure 3,
The output terminal (1a) of the main microprocessor (1) in Figure 1
) switch flags ``1'' and ``0'' are alternately output and supplied to the processor (8) to select the changeover switch SWI.
, After SW2 is switched, it moves to point A.

The next time the volume control is operated, the left 70
-Move to. Channel fader volume control (
46) is operated, a corresponding multiplication coefficient is selected and read from the memory (5) in FIG. 1, transferred to the coefficient memory (7), and then returned to point A. When the panpot volume controller (451) is operated, the corresponding multiplication coefficient is selected and read from the memory (5) in FIG. 1, and then transferred to the coefficient memory (7), and then returns to point A. Low When the volume operator (to) for varying the cutoff frequency of the band cut filter section LCF is operated, the corresponding multiplication coefficient is selected and read from the memory (5) in Fig. 1, and the process moves to point B. .High cut filter section H
Volume control for varying the CF cutoff frequency (3
When n is operated, a corresponding multiplication coefficient is selected and read out from the memory (5) in FIG. 1, and the process moves to point B. Controls for varying the level or varying the center frequency of the low-pass equalizer filter section LEF (to), C'l! When N is operated, the coefficient calculation microprocessor (6) calculates a corresponding multiplication coefficient, and B
Move to point. Controls (401, (4) for varying the level or center frequency of the high frequency equalizer filter section HEF
11, the coefficient calculation microprocessor (6) calculates a corresponding multiplication coefficient, and the process moves to point B. Volume controllers other than the above-mentioned volume controllers, that is, the mid-range equalizer filter section MEF
When the volume controllers (42 to 44J) for varying the level, center frequency, or Q are operated, the coefficient calculation microprocessor (6) calculates a corresponding multiplication coefficient, and the process moves to point B. Then, all the multiplication coefficients gathered at point B are collectively transferred to the coefficient memory (7), and then transferred to point A.

Next, an example of the frequency characteristics of each filter section will be explained.

FIG. 6 shows the frequency characteristics when the filter characteristics of the low-pass equalizer filter section LEF are of the shelping type, and the center frequencies are, for example, IIIG (z, 170H, z, and 30
This is a case where the frequency is set to Hz and the respective levels are varied.

FIG. 7 shows the frequency characteristics when the frequency characteristics of the low-pass equalizer filter section LEF are presence type, and the center frequencies are set to, for example, IKHz, 170Hz, 30Hz.
This is the case where K is selected and the level is varied.

FIG. 8 shows a frequency characteristic when the frequency characteristic of the high-pass equalizer filter section HEF is a shelping type, and the center frequency is, for example, 15 KHz or 2°6 KHz.

This is a case where the frequency is set at 500 Hz and the levels are varied.

FIG. 9 shows the frequency characteristics when the frequency characteristics of the high frequency equalizer filter section HEF are presence type, and the center frequencies are set to, for example, 15 KHz, 2.6 KHz, 50 KHz, etc.
This is a case where the frequency is set to 0 Hz and the respective levels are varied.

FIG. 10 shows the frequency characteristics when the frequency characteristics of the mid-range equalizer filter section MEF are of the presence type, where Q is fixed and the center frequency is 10 KHz.

1) G(, 100Hz) and the respective levels are varied.

Figure 11 shows the frequency characteristics (presence type) of the mid-range equalizer filter section MEF, where the center frequency is set to IKHz, the level is set to the maximum value of 12 dB, and the Q is set to, for example, 0.
．． 250, 0.597, 1.424, 3.398
, 8.000.

FIG. 12 shows the overall characteristics of the digital filter circuit of FIG. 2, and the song ffja shows the overall characteristics. The curve s represents the frequency characteristic of the low-pass cut filter section LCF, the curve C represents the frequency characteristic of the high-pass cut filter section HCF, the curve d indicates the frequency characteristic (presence 'm) of the low-pass equalizer filter section LEF, e indicates the frequency characteristic (presence type) of the high-frequency equalizer filter section HEF, and f
indicates the frequency characteristic (presence type) of the mid-range equalizer filter section MEF. The characteristics shown by curve a above and 1. Cru.

Next, a method of calculating the multiplication coefficients of the multipliers in each equalizer section will be explained. Figure 13 shows the configuration of a second-order presence type equalizer filter section, where TI+T2 are input and output terminals, M1 to M5 are multipliers, D1 to D4 are delay circuits with a delay amount of one sample period, and A is an adder. The multiplication coefficients of the multipliers M1 to M5 are respectively Kt Al + A2
p BI HB2. FIG. 14 shows the frequency characteristics of the equalizer filter section of FIG. 13, where the horizontal axis shows the frequency f1, the vertical axis shows the response (dB), and Fo is the center frequency. And the center frequency F. The gain G corresponding to I Q + response is the multiplication coefficient K + AI
+ A2 + Bl + B2. First, fa is defined as shown in the following equation. However, F is the sampling frequency.

When k is a coefficient, the absolute value of gain G is expressed as follows.

IG l = 20 gog (1 + k) Next, al l bl 1 C1 $ B21 C2 is defined as in the following equation.

b+ = b2= -2(1-fa)C12 1-
"'・(1+k)+fa"a221+'-(1
+k) 10 fa Thus, when G) is 0, the above coefficient is expressed as the following equation.

When G(O), the above coefficients are expressed as follows.

Figure 15 shows the configuration of a first-order shell pink high-frequency equalizer filter section, where T1 and T2 are input and output terminals, M
1 to M3 are multipliers with respective coefficients A.

B+Dl+D2 is a delay circuit whose delay amount is one sample period, and A is an adder. FIG. 16 shows the frequency characteristics of such a high frequency equalizer filter section.

Thus, the center frequency F. , G is the coefficient i(, A , B
Selected by.

G corresponding to the response is expressed as in the following equation.

G=20gogk The frequency fa is defined as follows.

Thus, when G) is 0, the coefficient is expressed as follows.

A=-□ F5+2πfa When G(O), the coefficient is expressed as follows.

1 +A Figure 17 shows the configuration of a first-order shelling type low-pass equalizer filter section, where T1+T2 are input/output terminals, M1 to
M3 is a multiplier whose coefficient is K.

DI+D2 is a delay circuit whose delay amount is one sampling period, and A is an adder.

Thus, the center frequency F. , the gains G corresponding to the responses are selected as coefficients A and B, respectively.

G and fa are defined as in the following equations.

G = 20gog k Thus, when G>0, each coefficient is expressed as in the following equation.

K21 When G(O), the coefficient is expressed as follows.

K=1 According to the present invention described above, the high-pass equalizer filter section, the low-pass equalizer filter section, and the mid-pass equalizer filter section HEF each include a second-order filter.

Since the multiplication coefficients of the LEF and MEF multipliers are easy to calculate, they are calculated by the coefficient calculation microprocessor (6), and a low-pass cut filter section consisting of a third-order filter and a high-pass cut filter section consisting of a fourth-order filter are calculated. Since the multiplication coefficients of each multiplier in the section are calculated in advance and stored in the memory (5), the work of calculating and writing the multiplication coefficients to be stored in the memory (5) is reduced, and this memory ( 5) A digital filter device that requires less capacity can be obtained.

Note that even when a first-order filter is used, this can be calculated by the coefficient calculation microprocessor (6). Also,
Since calculation of multiplication coefficients for filters of fifth order or higher is also complicated, these multiplication coefficients are also calculated in advance by a computer and written in the ROM+51.

Effects of the Invention According to the present invention described above, although a large number of filter characteristics can be selected, the work of calculating and writing the multiplication coefficients to be stored in the memory in advance is reduced, and the capacity of the memory for storing the multiplication coefficients is reduced. It is possible to obtain a digital filter device that requires less.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire digital filter device according to the present invention, FIG. 2 is a block diagram showing the specific configuration of the digital audio signal processing circuit, and FIG.
A layout diagram showing the panel of the filter characteristic input control device shown in the figure,
FIG. 4 is a line diagram showing the volume heirs of a part of the panel of the third section and their scales, FIG. 5 is a flowchart for explaining the operation and function of the present invention, and FIGS. 6 to 12 are each digital filter. Characteristic curve diagram showing the frequency characteristics of the part, No. 13
14 is a characteristic curve diagram showing its frequency characteristics. FIG. 15 is a block diagram showing the configuration of a shelping-type high-frequency equalizer filter section. FIG. 16 is a characteristic curve diagram showing its frequency characteristics, FIG. 17 is a block diagram showing the configuration of a shelping type low-pass equalizer filter section, and FIG. 18 is a characteristic curve diagram showing its frequency characteristics. (1) is the main microprocessor, (4) is filter '1
Human control device, (5) coefficient table memory, (6) coefficient calculation microprocessor, (71 coefficient memory,
(8) is a digital audio signal processor, DFK is a digital filter circuit, LCF is a low frequency cut filter section, HCF is a high frequency cut filter section, HEF is a high frequency equalizer filter section, LEF is a low frequency equalizer filter section,
MEF is a mid-range equalizer filter section. Same Hidemori Matsukuma −・・−1
1.1) εMonishi' Figure 4

Claims (1)

[Claims] a digital filter circuit formed by connecting a plurality of types of digital filter circuit units; a coefficient memory that stores multiplication coefficients to be applied to each multiplier of the plurality of digital filter circuit units; a main microprocessor; and a main microprocessor; A coefficient calculation microprocessor that calculates a multiplier for each multiplier in a second-order or lower-order filter circuit among the filter circuit sections, and each multiplier in a third-order or higher-order filter circuit among the plurality of types of digital filter circuit sections. has a coefficient table memory storing multiplication coefficients of The calculated multiplication coefficient and the multiplication coefficient read from the coefficient table memory are stored in the coefficient memory, and the multiplication coefficient read from the coefficient memory is applied to each multiplier of the digital filter circuit. , A digital filter device characterized in that filter characteristics of the digital filter circuit are set.