JPS6168663A - Input/output controlling device - Google Patents

Abstract

PURPOSE:To immediately detect the access to an incorrect memory address at each input/output address by fixing the mapping of memory so that the number to be allotted will become a part of memory address of a work area. CONSTITUTION:An address and size of work area is fixed for each input/output control routine. Next, a number allotted beforehand for input/output control routine is set to an erroneous address detection circuit 30, before a basic processing routine makes a program branch to appropriate input/output routine by the interruption of high-order device processing request signal 200 or input/ output adaptor processing request signal 210. And, an erroneous address interrup tion occurrence circuit 31 is set at an interruption generation capable state, and the detection circuit 3 retains the number set for input/output control rou tine. Then a microprocessor 10 compares the information address lines of address bus 102 which is used when the processor 10 access a ROM11 or RAM12 by other than instruction fetch, and informs the system of this abnormality.

Description

TECHNICAL FIELD The present invention relates to an input/output control device, and more particularly to a microprogram-controlled input/output control device that can control a plurality of input/output devices simultaneously in a time-sharing manner.

It is connected to the host device via the interface, and is also connected to multiple input/output adapters via the input/output adapter interface to simultaneously control the input/output devices connected to the input/output adapters in a time-sharing manner. It looks like this.

A microprogram for such an input/output control device usually consists of one basic processing routine and a plurality of input/output control routines depending on the type of input/output adapter, each having an independent work area.

The basic processing routine and each input/output control routine have a predetermined program interface, and processing requests from a host device or input/output adapter to the input/output control device are first determined by the basic processing routine to which input/output control routine. The program branches to the appropriate input/output control routine according to the program interface. When the input/output control routine completes the processing required at that time, the program branches to the basic processing routine according to the program interface. In this way, the input/output control device processes processing requests from the host device and the input/output adapter in a time-sharing manner, thereby controlling and operating a plurality of input/output devices simultaneously.

The basic processing routine performs common processing for each input/output control routine in a time-sharing manner, so it needs to access the work area of all input/output control routines, but each input/output control routine can access only the work area that belongs to it. Access to other areas is not necessary.

However, if there is a programming error in the input/output control routine and it accesses a work area other than its own and reads or writes from that address, conventional input/output control devices will not be able to access such a wrong address. Since there is no access detection means, an erroneous access may cause one input/output control routine to write to a work area belonging to another input/output control routine. Furthermore, if the control memory in which the microprogram is stored is made up of RAM, if the microprogram itself is destroyed, even if an abnormality occurs in a certain input/output control routine, that input/output control routine must be suspected. Furthermore, malfunctions may occur due to hardware failures, so it is extremely difficult to find the cause of the abnormality.

Purpose of the Invention The present invention focuses on the fact that an input/output control routine without a program error accesses only the memory area allocated as the work area of the input/output control routine, and the number assigned to each input/output side routine. By fixing the mapping of memory so that it becomes part of the memory address of the work area as it is, it is possible to immediately prevent each input/output control routine from accessing an invalid memory address outside the work area belonging to the input/output control routine. The purpose is to provide an input/output control device that can be detected by

The input/output control device according to the present invention is used as a storage area in a memory, and in the input/output control routine of a program, only a specific area of the storage area is accessed as a work area, so that multiple input/output devices can be operated simultaneously. A microprogram-controlled input/output control device that enables the use of a microprogram-controlled input/output control device that responds to an interruption of a processing request from one of multiple input/output devices to enable the use of a storage means for storing in advance an area range of a work area; and address abnormality detection means for detecting that an address when accessing the work area from a processor other than an instruction fetch is outside the area range stored in the storage means. When this address abnormality is detected, an interrupt request is generated to the processor to handle the failure.

Example Hereinafter, the present invention will be explained in detail using the drawings.

In FIG. 1 showing an embodiment of the present invention, a bidirectional data bus 101 and a unidirectional address 102 of a microprocessor 10 in an input/output control device 1 are connected to a ROMII,
RAM12. The host interface circuit 20゜I/O adapter interface circuit 211 is connected to the abnormal address detection circuit 30 and abnormal address interrupt generation circuit 31 of the interrupt control circuit 22, and the microprocessor 10 is connected to the host device interface circuit 20. It is also connected to a plurality of input/output adapters via an input/output adapter interface circuit 21, respectively. Upper-level device processing request signal 200 outputted by the higher-level device interface circuit 20. The input/output adapter processing request signal 210 outputted by the input/output adapter interface circuit 21 and the abnormal address interrupt request signal 320 outputted by the abnormal address interrupt generation circuit 32 are connected to the interrupt control circuit 22. The output, microprocessor interrupt signal 220, is connected to microprocessor 10. Abnormal address detection signal 30 which is the output of the abnormal address detection circuit 30
0 is connected to the abnormal address interrupt generation circuit 32.

In this embodiment, it is assumed that the basic processing routine of the microprogram is stored in both the ROM II and the RAM 12, and the input/output control routine is stored in the RAM 12. Therefore, a part of the basic processing routine, a plurality of input/output control routines, and their work areas coexist in the RAM 12. In particular, the work area for the input/output control routines is allocated to a predetermined fixed area. There is.

FIG. 2 shows that in this embodiment, the number of input/output adapters that the input/output control circuit 1 can operate simultaneously is 16, the maximum work area used by each input/output control routine is 256 bytes, and the address bus There are 16 address information lines for 102 bits, and out of the 64 byte (K=1ρ24=2'', same below) memory space defined by these 16-bit addresses, F 000 (+s ) to FF'FF (16) This is a memory mapping diagram when bytes are allocated to the work area of the input/output control routine.
000 (I6) indicates a hexadecimal number.

FIG. 3 shows the memory address structure of the work area of each input/output control routine in the case of the memory mapping shown in FIG. 2. That is, the upper 4 bits correspond to the most significant "'F" of the mapping address in Figure 2, and in this example, °'1.
'', and the next 4 bits represented by R3 to R0 are numbers representing the work area of each input/output control routine allocated in advance to each input/output device, and the highest address of the address in FIG. The 8 pits represented by T7 to To indicate the byte number within the work area assigned to each input/output control routine.This memory address corresponds to the 16 address information of the address bus 102. line A+s
-Ao as shown in the figure. Note that An(n=1
5 to O), n corresponds to the bit weight for the address. For example, A1. corresponds to the 215th pit of the address information line.

Microprocessor 10 reads ROM from address 102.
II or RAM 12 for fetching an instruction, and executes the instruction word read onto the data bus 101. Microprocessor 10 is ROM11 or RAM1
When the microprocessor reads an instruction word that requires memory access to operation data by instruction fetch from ROM II or RAM 12, the microprocessor reads or writes operation data to ROMII or RAM 12. When the microprocessor 10 accesses the RAM 12 in the ROM III, it controls whether the access is a memory read or a memory write, and whether it is an instruction fetch or a read operation data at the time of the memo IJ17-code. Signals are included on address bus 102.

Microprocessor 10 is usually ROMII or HRAM1
It executes the basic processing routine stored in 2 and waits for some kind of processing request interrupt.

In this state, if there is a processing request from the host device or any input/output adapter, it is transmitted to the interrupt control circuit 22,
This interrupt control circuit uses the microprocessor interrupt request signal 2
20 generates an interrupt to the microprocessor 10. When the microprocessor 10 receives an interrupt, it receives detailed processing request information from the host device interface circuit 20 or the input/output interface circuit 21 in an interrupt processing routine according to the interrupt cause in the basic processing routine, and requests processing. The program branches according to the program interface predetermined for the input/output control routine that is being executed.

In the input/output control routine, after controlling the input/output adapter belonging to itself using the work area assigned to it via the input/output adapter interface circuit 21,
The program branches to the basic processing routine according to the defined program interface. In the basic processing routine, the interrupt control circuit 22 is controlled so that interrupts can be generated again by the host device processing request signal 200 and the input/output adapter processing request signal 210.

In this way, the input/output control device 1 prioritizes processing requests from the host device and each input/output adapter using the interrupt control circuit 22, and executes appropriate input/output control routines according to the priority order. operate the input/output adapters simultaneously in a time-division manner.

In the input/output control device according to the present invention shown in FIG.
The address and size of the work area for each input/output control routine are fixed as shown in FIG. 2, and in addition to the above-mentioned control, the basic processing routine is
0 or the input/output adapter processing request signal 210, and before the program branches to an appropriate input/output control routine, the number previously assigned to this input/output control routine is sent to the abnormal address detection circuit 30, and the abnormal address is assigned. The interrupt generation circuit 31 is set to an interrupt generation enabled state. The abnormal address detection circuit 32 holds the set input/output control routine number and compares it with the address information line of the address bus 102 when the microprocessor 10 accesses the ROM 11 or RAM 12 for purposes other than fetching instructions.

When the logical expression for this comparison is described using the symbols shown in FIG. 3 for the memory mapping diagram shown in FIG. 2, it becomes the following equation.

P = (A15■1)■(A14■1)(A13■1
) V (Al2O2) (A11■R3) (n◎■R
,) (Ae ■Rt) V (A, ■Ro) = Ats V A14A13A12 (A11 ■R3) V
(A+o■R,)V(A,■R+)■(A,OR,,)
Here, ■ and ■ are symbols representing a logical sum and an exclusive logical sum, respectively, and A15 and the like are symbols representing negation.

If the above P is 1, it indicates that the microprocessor 10 has accessed an area of ROMII or RAM 12 other than the work area belonging to the input/output control routine that is being executed at that time, so the condition that this P is not an instruction error or a failure is required. The signal obtained by performing the AND operation is the abnormal address detection signal 300.

When the abnormal address interrupt generation circuit 31 is notified of the detection of an abnormal address by the abnormal address detection signal 300 from the abnormal address detection circuit 30, if interrupt generation is permitted by the microprocessor 10, the abnormal address interrupt generation circuit 31 generates an abnormal address interrupt request signal. 310 generates an interrupt to the microprocessor 10 via the interrupt control circuit 22. This interrupt request is set by the interrupt control circuit 22 so that the microprocessor 10 can be interrupted even while the microprocessor 10 is processing an interrupt based on the host device processing request signal 200 or the input/output adapter processing request signal 210. A priority is assigned.

The abnormal address interrupt processing routine of the basic processing routine performs appropriate fault processing such as notifying the host device.

Note that when the input/output control routine returns normally to the basic processing routine, the basic processing routine sets the abnormal address interrupt generation circuit 31 to the interrupt generation disabled state so that an abnormal address interrupt will not be generated by mistake due to its own processing. Set to .

When an abnormal address is detected, an abnormal address interrupt is generated to the microprocessor, but the point is to detect the abnormal address and notify the system of this abnormality in some way. It is something.

As described above, the present invention has the advantage that unauthorized access to memory in an input/output control routine can be detected easily, reliably, and instantaneously.

In particular, as shown in Figure 2, by fixing the address in the memory of the work area of the input/output control routine, it is easy to make a mismatch between the fixed address and the address at the time of memory access. There is an advantage that the configuration of the address abnormality detection circuit is also simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of memory mapping of the memory in FIG. 1, and FIG.
This figure shows the structure of memory addresses of the work area of the input/output control routine of FIG. 2. Explanation of symbols of main parts 1... Input/output control device 10... Microprocessor 11, 12...
Memory 22...Interrupt control circuit

Claims (3)

[Claims] (1) At least a part of the storage area in the memory is used as a work area for a program, and in the input/output control routine of the program, only a specific area of the storage area is accessed as a work area, so that multiple A microprogram-controlled input/output control device that enables the simultaneous use of input/output devices, and in response to an interruption of a processing request of one of the plurality of input/output devices, storage means for storing in advance an area range of a work area within the allocated specific area; and an address outside the area range stored in the storage means when accessing the work area from a processor other than instruction fetch; An input/output control device comprising address abnormality detection means for detecting an abnormality in an address. (2) All work areas of the input/output control routine are specified by the upper n bits of all addresses of the storage area,
Also, m bits following the above n bits (n and m are positive integers)
Memory addresses are set so that each work area assigned to each of the input/output devices is specified respectively, and the storage means stores (n+m) bits of the address, and the address abnormality detection The means is the upper address (n+m) at the time of access from the processor.
2. The input/output control device according to claim 1, wherein the input/output control device is configured to detect a coincidence or mismatch between a bit and (n+m) bits of the storage means. (3) The input/output control device according to claim 2, wherein the address abnormality detection means is configured to generate an interrupt request signal to a processor when an address mismatch is detected.