JPS6168566U - - Google Patents
Info
- Publication number
- JPS6168566U JPS6168566U JP1984153198U JP15319884U JPS6168566U JP S6168566 U JPS6168566 U JP S6168566U JP 1984153198 U JP1984153198 U JP 1984153198U JP 15319884 U JP15319884 U JP 15319884U JP S6168566 U JPS6168566 U JP S6168566U
- Authority
- JP
- Japan
- Prior art keywords
- pixel
- interest
- circuit
- absolute value
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/405—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
Description
第1図は本考案の動作を示す図、第2図は本考
案の回路を示す図。
1……文書、2……CCDセンサ・アレイ、3
……A−D変換回路、4……ライン・バツフア、
5,9,16,16……比較回路、6……平均化
回路、7……減算回路、8……付加閾値幅設定回
路、10……オア回路、11,13……選択回路
、12……ラツチ、14,15……閾値発生回路
。
FIG. 1 is a diagram showing the operation of the present invention, and FIG. 2 is a diagram showing the circuit of the present invention. 1...Document, 2...CCD sensor array, 3
...A-D conversion circuit, 4...line buffer,
5, 9, 16, 16...Comparison circuit, 6...Averaging circuit, 7...Subtraction circuit, 8...Additional threshold width setting circuit, 10...OR circuit, 11, 13...Selection circuit, 12... ...Latch, 14, 15...Threshold value generation circuit.
Claims (1)
信号レベルを上記注目画素に対する閾値として用
いて上記注目画素の2値レベル信号を発生する回
路と、上記注目画素及び上記閾値の差の絶対値を
所定の値に比較し上記絶対値が上記所定の値より
も大きい時に制御信号を発生する回路と、上記制
御信号の存在に応答して上記注目画素の2値レベ
ル信号を出力線にゲートし、上記制御信号の不存
在に応答して上記注目画素に先行する画素の2値
レベル信号を上記出力線にゲートする選択回路を
備えたことを特徴とするイメージ処理装置。 A circuit that generates a binary level signal of the pixel of interest using the average signal level of a plurality of pixels surrounding the pixel of interest on a document as a threshold for the pixel of interest, and an absolute value of the difference between the pixel of interest and the threshold. a circuit that compares the absolute value with a predetermined value and generates a control signal when the absolute value is greater than the predetermined value; and a circuit that gates the binary level signal of the pixel of interest to an output line in response to the presence of the control signal. . An image processing device comprising: a selection circuit that gates a binary level signal of a pixel preceding the pixel of interest to the output line in response to the absence of the control signal.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984153198U JPS6168566U (en) | 1984-10-12 | 1984-10-12 | |
KR2019850009307U KR890007509Y1 (en) | 1984-10-12 | 1985-07-23 | Devices for processing colour picture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984153198U JPS6168566U (en) | 1984-10-12 | 1984-10-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6168566U true JPS6168566U (en) | 1986-05-10 |
Family
ID=15557184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984153198U Pending JPS6168566U (en) | 1984-10-12 | 1984-10-12 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS6168566U (en) |
KR (1) | KR890007509Y1 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56102161A (en) * | 1980-01-18 | 1981-08-15 | Nec Corp | Binary encoding circuit |
-
1984
- 1984-10-12 JP JP1984153198U patent/JPS6168566U/ja active Pending
-
1985
- 1985-07-23 KR KR2019850009307U patent/KR890007509Y1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56102161A (en) * | 1980-01-18 | 1981-08-15 | Nec Corp | Binary encoding circuit |
Also Published As
Publication number | Publication date |
---|---|
KR890007509Y1 (en) | 1989-10-26 |
KR860005434U (en) | 1986-06-11 |
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