JPS6167182A - Coder of image data - Google Patents

Abstract

PURPOSE:To reduce an amount of digital data, to compact an amount of items to be memorized, to reduce the amount of transmitting data and to improve the transmitting speed by assuming bit below '1' in an image date of N bits as effective data. CONSTITUTION:Input analog signals 9 are converted into signals of N bits through a converter 1 and discriminated as '0' or '1' signals in the order from the first bit through a circuit comprising an inverter 7 and an AND gate 8. The outputs are converted serially 2 and unnecessary '0' data are cut off by shifting the converted outputs leftwards using a shift registor 4 as the clock signal and the number of cut-off bit of '0' cut-off by a counter 3 is counted by a counter, thereby providing an effective data output 13 for the '1' data from the first bit of '1' to a required number of bits and the number of cut-off bits is obtained as a counter output 12.

Description

[Detailed description of the invention] [Technical field of % Ming] This invention relates to an image data encoding device for encoding image data acquired from a remote sensor mounted on an artificial satellite, and is an extremely high-speed image data encoding device. This image data encoding device is characterized in that it attempts to reduce the amount of data transmitted from the nine artificial satellites by cutting out eight unnecessary pits in the image data, which is the dog's data.

The analog original data collected by the Senna onboard the satellite is A
/D converted and encoded data is input to a computer as digital image data.

Image processing is being performed.

[Prior art]

First, a conventional image data encoding method will be briefly explained. Conventionally, image data was converted into N by an A/D converter.
When encoding into bits, all N bits of the converter output were input and processed as digital uSul & data, or in the case of @1 speed data, there was a large amount of data, so 9 normal encoding was performed. , in subsequent storage and transmission, etc.

Large-scale equipment was required. h/Df: A single volatile signal encoded into N bits is not always valid, and the content of the N bits is not necessarily valid, and it may be difficult to detect signals on the earth's surface, such as active microwave sensors such as synthetic aperture radar. If the reception level at the satellite changes greatly depending on the reflection coefficient and a wide dynamic range is required, one piece of data can be expressed using only the lower few bits.

[Summary of the invention]

Therefore, in this invention, when encoding analog original data in order to reduce the amount of processing of image data obtained in large quantities by artificial satellites.

Instead of converting all N bits into digital image data as they are, we look at them sequentially starting with the most significant bit, and then move from the bit with a 1' to the lower bits, extracting only the necessary pits as valid data, and at the same time.

A code that outputs data indicating the number of bits of "0" data that was truncated before the first "1", and can represent the content of the original N-bit signal with fewer bits than N bits using these two pieces of data. This paper aims to improve the conventional technology by proposing a digital image data processing system and reducing the amount of digital image data handled by computers.

[Embodiments of the invention]

An embodiment of this invention will be shown below.

As shown in Fig. 1, in an A/D converter (1), an A/D converter (1), a counter (3), and a shift register (4) are used.
The analog signal input to the
In order to identify which one is, the signal passes through an identification circuit consisting of an inverter circuit (7) and an AND circuit (8).

The conversion end signal from the A/D converter (1) is made into a monopulse with an appropriate pulse width by the seven-point pulse generator (5), and the A/D output of the most significant bit is inverted through the inverter circuit Mt71. AND circuit (8)
If the input of the inverter circuit (7) is "0", the output of the AND circuit (7) becomes "1".

Further, if the input power of the inverter circuit (6) is "1", then the AND output becomes "0" and all outputs of the AND circuit W6+7+ for the following bits become "0".

This N-bit parallel data is converted into serial data by a parallel/serial converter (2).

As a clock signal for a shift register.

By shifting the A/D output to the left, unnecessary “
0" data is truncated. Also, at the same time, the counter (3
) is also used as an input pulse, and the number of bits of truncated "0" data is counted. '0''.

FIG. 2 shows a timing chart of the input Mα of the inverter circuit as the "1' identification circuit and the output N"fil of the AND circuit. In this way, discrimination between "0" and 1 is performed, and as a result, the input of the counter (3) and the clock signal of the shift register (4) are obtained as the output of the parallel/serial converter as shown in the figure. At this time, it is necessary to control the single pulse width in the monopulse generator (5) so that there are at most N clock signals of the parallel/serial conversion output within the pulse width of the single pulse output from the monopulse generator (5). .

Shift register and counter timing chart Yi
Shown in Figure 3. (1) is the N-bit input LlO to the shift register, (b) &'! Parallel/serial converter (2
), that is, the clock signal and counter input of the shift register. -For example, when the data shown in (a) and (+3) are given, the output II3 of the shift register shown in (C) and the output Ua of the counter shown in (d) are obtained as shown in the figure. .

As you can see, as long as "0" continues from the most significant bit by the shift register, that "O" will be truncated by left shift, and from the first bit of "1", it will be shifted down by one digit for the required number of bits. An output l11) of valid data is obtained. At the same time, the number of truncated bits is obtained as a color output ilG.

The counter output uI and shift register output uυ are shown in Figure 4 (
-) can be expressed in the format shown below. (
1)) shows an example.

The signal that is first encoded into N bits by A/D & Wisdom in this way is the sum of the maximum number of shifts, log, N1 bits expressed as 2kJ, and the necessary bits ffN2 bits, which can be considered as valid data, (N+10N2) Since it can be expressed in bits as N)Nl-)-N2, it can be said that the digital image data can be reduced by this image data encoding device.

〔Effect of the invention〕

As is clear from the above description, the present invention is applicable to converting digital data obtained from two artificial satellites into analog original data for input into a total of n devices for image processing when encoding the data as digital image data. It is possible to significantly reduce the ``kk'', compress the data storage cover, or improve the transmission error and transmission speed during data transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the m-image data encoding device according to the present invention, FIG. 2 is a timing chart of the "0" and '1" identification circuit, FIG. 3 is a timing chart of the shift register and counter, and FIG. The figure is a diagram showing bit formats of encoding by a conventional device and encoding by the device of the present invention. In the figure, (1) is an A/D converter, (2) is a parallel/serial converter, ( 3) is a counter, (4) is a shift register, (5) is a monopulse generator, (6) is a clock generation port M, 17) is an inverter circuit, +
81 is an AND circuit. (9) is the input analog signal, ([I is the A/D converter output, αυ is the AND circuit output, +13 is the counter output, +
13 is a shift register output. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In an encoding device that encodes analog original data acquired for computer processing of a large amount of image data acquired by a remote sensor mounted on an artificial satellite, the encoded N-bit data is An image data encoding device comprising a shift register for truncating unnecessary high-order "0" data and extracting valid data, and a counter for outputting the number of bits of the discarded high-order "0" data. .