JPS6165453A - Insulation substrate for semiconductor - Google Patents
Insulation substrate for semiconductorInfo
- Publication number
- JPS6165453A JPS6165453A JP18766284A JP18766284A JPS6165453A JP S6165453 A JPS6165453 A JP S6165453A JP 18766284 A JP18766284 A JP 18766284A JP 18766284 A JP18766284 A JP 18766284A JP S6165453 A JPS6165453 A JP S6165453A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- semiconductor
- sapphire
- sapphire substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulating Bodies (AREA)
Abstract
Description
【発明の詳細な説明】 （産業１の利Ｉ１１分野） 本発明は、゛１′傅本川絶縁基板に関する。[Detailed description of the invention] (Industry 1 benefits I11 fields) The present invention relates to a ``1'' Fumotokawa insulating substrate.
（従未扶術）
サファイアレｌ、板は、たどんはＳＯ３技術において、
ＳＩ入１−仮の代わりに半導体用絶縁基板として用いら
れる。８０８枝術は、す７アイ７基板の上に８１薄膜を
エピタキシで成長させＭＯＳテ゛ハ′イスをｔ＋ｖｉ成
し、Ｒ本問題となっていｔこ配線容量とフィブレー＞’
３７とを解決し、＼’ＩＯＳデバイスの高速化をはかる
しのである。(Junifujutsu) Sapphire l, board, tadon in SO3 technology,
SI-containing 1 - Used as an insulating substrate for semiconductors instead of temporary. In the 808 branch technique, an 81 thin film is grown by epitaxy on a 7-eye 7 substrate to form a MOS device in t+vi, and the problem becomes t+vi, which is the wiring capacitance and fibre.
37 and speed up IOS devices.
（発明の１１イ決ｒべき問題点）
サファイア１．ＩＨ根板上高温度でシリコン等の半導体
をエビタキンヤル成長させると、原料ブスに使用してい
る水素によってサファイア基板の母体表面の一部が還元
され、サファイア基板上に形成したシリコンのエピタキ
シャル層の中には還元された金ＪＡＡρらしくは／１ｉ
２桑がドープされ、汚染されていることか知られている
。したがって、サファイア基板上にエピタキシャル成長
した半４本層の電気的特性や結晶性が、としく低下する
。このため、サファイア基板は、災用基板としての性能
か阻害されていて、１−０実用化されていないのが実情
である。(11 Problems to be resolved in invention) Sapphire 1. When a semiconductor such as silicon is grown epitaxially at high temperature on an IH base plate, a part of the base surface of the sapphire substrate is reduced by the hydrogen used in the raw material bus, and the inside of the silicon epitaxial layer formed on the sapphire substrate is reduced. It seems that the gold returned to JAAρ is /1i
It is known that mulberries are doped and contaminated. Therefore, the electrical properties and crystallinity of the semi-quadruple layer epitaxially grown on the sapphire substrate are significantly degraded. For this reason, the performance of the sapphire substrate as a disaster substrate is hampered, and the reality is that it has not been put into practical use.
一方、人ビネルＪ１（板は、水素に対して耐性か高くシ
リコンとの格子整合性も高い。しかし、高価て′あるこ
とと、ｋ［Ｉ径つェハか１１１に（いことなどの難点を
（ｉｌ−１実用化されていない。On the other hand, vinyl J1 (plate) is highly resistant to hydrogen and has high lattice matching with silicon.However, it is expensive and has drawbacks such as the fact that the (IL-1 has not been put into practical use.
本発明の目的は、゛１１佇１本デバイスに影響を１＞え
ない半導体１１１ ！、！：板を提（Ｊｌ、することで
ある。The object of the present invention is to create a semiconductor 111 that has no effect on the 11 devices! ,! : To present a board (Jl, to do something).
（問題点をガイ決するｊこめの手段）
本イｃ明（−係ろ゛］雪ｆ１（、ＩＩ＋絶縁基板は、サ
ファイア基板の＜！、’ （ｆｌｌに、々ビトル層を、
または、スピネル層と酸化マク五／ウム層を順次形成し
てなる。(Measures to resolve the problem) In this case, the snow f1 (, II + insulating substrate is a sapphire substrate <!,' (fll, a bit layer,
Alternatively, a spinel layer and a pentium oxide layer are sequentially formed.
（作 用）
本発明に係る１”、導本用絶縁基板を用いて半呑本テ゛
バイスを１，９造Ｖろ」、じ会においては、たとえ、高
Ｚ是瓜（−・ｌ ：、’ ＋１１１ ”Ｃ）（二」二げ
て、シリコン等の半導本村料を水素からなる雰囲気中で
エピタキシャル成長させてら、内部のサファイアは安定
なスピネルｊ員（こ￥’４ｈＩＶζいるｒこハ、直接活
性な水素；こ（１１１ｉされることもなく、安定である
。(Function) At the same meeting, even if a high-Z product (-・l:,' +111 ``C) (2'') Furthermore, when a semiconductor material such as silicon is grown epitaxially in an atmosphere consisting of hydrogen, the sapphire inside is a stable spinel member (this is directly active). This hydrogen is stable without being converted into 111i.
更に、入面の１１１結晶酸化マグネシウム膜やスピネル
層は活性な水素にス・１しても安定であるため、シリコ
ン’４；；ｙ＋ ’ｌ’：尋１本エピタキシャルや酸素
−ｑＪ＋ｉり染を１ノえることらなく、高純度のエピタ
キシー・ル膜か１１１ら１する。Furthermore, since the 111-crystalline magnesium oxide film and spinel layer on the entrance surface are stable even when exposed to active hydrogen, silicon '4; A high purity epitaxy film is produced without any change.
しｒこかー，で、１・発明に係る絶縁基板をシリコン等
の゛１−等ＩＣテ・・（２．を二進用させることｔこよ
Ｉ）、素子間分離か１″１，鴇となり、しからラッチア
ップフリーとなるｒこめ、超Ｉ１１，速で・高密度、高
集積化のバイポーラＦ ７ ’７ ／スタや（ハ１（い
餐・ｉの＼ＬＳＩの１゛を成か町１１ヒである４
（実施例）
以下、添附の図面に店づいて本発明の実施例をΩτ細に
説明する。So, 1. The insulating substrate according to the invention is made of silicon, etc., as an IC chip...(2. should be used in binary form), and the isolation between the elements becomes 1"1. Since it is latch-up free, it is super I11, fast, high-density, and highly integrated bipolar F7'7/star. 11H4 (Embodiment) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
サファイアｊ，ｌ板１の針面に彼蕩する単結晶酸化マグ
、不ンウム１１位２１ま、ｌ，ｊ、板温度〜９ Ｌｌ
Ｌｌ °Ｃでスバ。Single-crystal oxide mag covering the needle face of sapphire j,l plate 1, unum 11th place 21ma, l, j, plate temperature ~9 Ll
Suva at Ll °C.
タヤＭ Ｏ Ｃ Ｖ ｌ’）、ＩｃＢ．ＡＬＥ、イオン
プレーテング、Ｉ， ｉｃにより膜厚か（）、２〜１０
μの範囲で・第１図（ｄ）１こ示す」、ｊにサファイア
基板ｌ：こ重畳して汗勿友される。Taya M O C V l'), IcB. Film thickness depending on ALE, ion plating, I, ic (), 2 to 10
In the range of .mu., as shown in FIG.
次１ユ第１図（ＩＪ）に示すように、この基板を真空中
らしくは１■素雰囲ｒ．（中でｉ，、！）文力弓Ｉｌ＋
０ ０ Ｃ−２（）（月１’Ｃの・ｉＧ囲内で熱処理
すると、サファイア基板材料の４八ト０，と酸化マグネ
シウム膜２のλ・ＩｇＯ とか固化反応を起し、中間
には、スピネル層（ＭｇＵ・ＡＩ−←）、＋３か形成さ
れ、第１図（ＩＪ）の構造のらのか出現する。・題こ負
時間の熱処理を嘉′ｒ〕とに上り入ビイ、ル層は表面全
トドにまで達し第１図（ｃ）め（、νＩ造のらのか得ら
２する。反応時間を制御することにより、■口重（ｂ）
または第１図（Ｃ）の構造の絶縁〕１１八を１：するこ
とかできる。Next, as shown in FIG. 1 (IJ), this substrate is placed in a vacuum atmosphere of 1. (Inside i,,!)Bunryoku Il+
0 0 C-2 () (When heat-treated within the range of 1'C/iG, a solidification reaction occurs between 4800 of the sapphire substrate material and λ/IgO of the magnesium oxide film 2, and the spinel is formed in the middle. A layer (MgU・AI−←), +3 is formed, and a layer of the structure shown in Figure 1 (IJ) appears. When all the sea lions reach the size shown in Figure 1 (c), νI-shaped sea lions are obtained. By controlling the reaction time, ■ Mouth weight (b)
Alternatively, insulation of the structure shown in FIG. 1(C)] 118 can be made 1:1.
本発明に係る絶縁基板を用いたシリコン基板は、次のよ
うに１１成ｒ′きる。第２図と第３図にそれぞれ示す１
つに、第１図（＋１）、 （ｃ）に示した半導体用絶縁
基板１；に、モノンラン（ＳｉＨ．）、４塩化硅素（Ｓ
ｉＣ （’，ｌ”、） ’Ｉ りＯＣｌｚラン（ＳｉＨ
Ｃ！ｈ）などの〃スを使用し、基板温度を９５０°Ｃ〜
１ ２ ０ ０°Ｃに加熱して、シリコン等の半導体エ
ピタキシャル膜４を（）、３〜２０μの範囲内の厚さに
形成する。A silicon substrate using an insulating substrate according to the present invention can be formed into 11 layers as follows. 1 shown in Figures 2 and 3 respectively.
In addition, monolan (SiH.), silicon tetrachloride (S
iC (', l”,) 'I OClz run (SiH
C! h), etc., to raise the substrate temperature to 950°C or more.
The film is heated to 1200° C. to form a semiconductor epitaxial film 4 made of silicon or the like to a thickness within the range of 3 to 20 μm.
前述の理由がら、サファイア基板からのＡ（”や酸素等
の汚染らなく、良好な電気的特性や結晶性を示゛ｒ゛１
″．導田川絶縁基板を実現することか出来る。For the reasons mentioned above, the sapphire substrate exhibits good electrical properties and crystallinity without contamination by A('' or oxygen, etc.).
″．Is it possible to realize a Dotagawa insulated substrate?
特１こ第１しｌ（Ｉｌ＋のように基板表面が単結晶の酸
化マクネンウム面か１，なる状況においては、酸化マグ
十／パ〕ｌ、白身の熱１云４率が酸化ベリリウムに次い
で大きく、少なくとらサファイア基板より５倍は高いの
で． Ｊｌ常に放熱性の良い半導体用絶縁基板をなして
いる。したがって、パイポーラトランノスタを含めた比
較的消費電力の大きいデバイスに信頼性を高める効果を
提供するものである。In particular, in situations where the substrate surface is a single-crystal machinenium oxide surface such as Il+, the heat ratio of the white body is the second highest after that of beryllium oxide. It is at least 5 times more expensive than a sapphire substrate.JlAlways serves as an insulating substrate for semiconductors with good heat dissipation.Therefore, it has the effect of increasing reliability in devices with relatively high power consumption, including bipolar trannostars. This is what we provide.
なお、これ−９のノ，（仮は、シリコン半導体デバイス
だけでなく、（ｉ ａ Ａ ｒ．やＩ ｎ Ｐなどの化
合物半導体デバイスにら適用出来ることは言うまでもな
い。It goes without saying that the present invention can be applied not only to silicon semiconductor devices but also to compound semiconductor devices such as (ia Ar. and InP).
（発明の効果）
本発明によれは、半４体デバイスの性質１こ感１シ響を
与えない゛１″導体用絶縁基板を提供できる。(Effects of the Invention) According to the present invention, it is possible to provide an insulating substrate for a ``1'' conductor that does not exhibit the characteristics of a half-quad device.
・１。図面の簡ｌｉｔな説明
第１図（ａ’ｌ，（ｌ＋）、（ｃ）は、本発明に係る半
導木用絶縁！！：＋Ｊｉの製作工程の各段階を図式的に
示す断面図である。・1. Brief explanation of the drawings Figure 1 (a'l, (l+), (c) is a sectional view schematically showing each step of the manufacturing process of the semiconductor wood insulation!!:+Ji according to the present invention. be.
第２図と第：）図とは、本発明に係る絶縁基板を用いて
作＋ｌｊ．されたシリコン基板を示す図式的な断Ｉｆｉ
ｉ図である。FIG. 2 and FIG. Schematic cross-section showing a silicon substrate
This is a diagram.
１・・・サファイアＪ，ｊ；板、
２・・・酸化マク不シウム膜、 ３・・スピネル層、
ト・・ンリフ／のエビタキ／ヤルＪｔｉ。1... Sapphire J, j; plate, 2... Macunium oxide film, 3... spinel layer,
To Nrif/Ebitaki/Yaru Jti.
４、？ ５１ 出 願 １１ ノヤーブ株
式会１［代 埋 ）（ 弁理上 Ｓ１″山 イ゛・
２ ほか２名第１図
第２図
第３図4.? 51 Application 11 Noyab Co., Ltd. 1
2 Other 2 people Figure 1 Figure 2 Figure 3
Claims (2)
シウム層とを順次形成してなる半導体用絶縁基板。(1) An insulating substrate for semiconductors, in which a spinel layer and a magnesium oxide layer are sequentially formed on the entire surface of a sapphire substrate.
る半導体用絶縁基板。(2) An insulating substrate for semiconductors formed by forming a spinel layer on the entire surface of a sapphire substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18766284A JPS6165453A (en) | 1984-09-06 | 1984-09-06 | Insulation substrate for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18766284A JPS6165453A (en) | 1984-09-06 | 1984-09-06 | Insulation substrate for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6165453A true JPS6165453A (en) | 1986-04-04 |
Family
ID=16209981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18766284A Pending JPS6165453A (en) | 1984-09-06 | 1984-09-06 | Insulation substrate for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6165453A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007256725A (en) * | 2006-03-24 | 2007-10-04 | Shimonishi Giken Kogyo Kk | Display monitor opening/closing device for projector system |
-
1984
- 1984-09-06 JP JP18766284A patent/JPS6165453A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007256725A (en) * | 2006-03-24 | 2007-10-04 | Shimonishi Giken Kogyo Kk | Display monitor opening/closing device for projector system |
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