JPS6163039A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6163039A JPS6163039A JP59184595A JP18459584A JPS6163039A JP S6163039 A JPS6163039 A JP S6163039A JP 59184595 A JP59184595 A JP 59184595A JP 18459584 A JP18459584 A JP 18459584A JP S6163039 A JPS6163039 A JP S6163039A
- Authority
- JP
- Japan
- Prior art keywords
- input
- terminal
- drain
- semiconductor device
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000007599 discharging Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000003491 array Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、０ＭＯ８論理ＬＳＩゲートアレイ全般に係り
、特にＬＳＩの性能改善に好適な半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates generally to 0MO8 logic LSI gate arrays, and particularly to a method of manufacturing a semiconductor device suitable for improving the performance of LSI.
従来のＣＭＯＳゲートアレイが例えば３人力のＮＡＮＤ
回路を構成する場合、このうち２人力のみ使用するとき
゛でも性能の点では３人力使用時と同一の性能しか得ら
れないという欠点があった。なおこの種の論理回路の例
として、特開昭５７−１０６２３５号公報「論理回路」
がある。 。For example, a conventional CMOS gate array can be converted into a NAND by three people.
When constructing a circuit, there is a drawback in that even when only two of these people are working, the performance is the same as when three people are working. As an example of this type of logic circuit, Japanese Patent Application Laid-Open No. 57-106235 "Logic Circuit"
There is. .
本発明の目的は、ＣＭＯＳゲートアレイの性能改善対策
として、未使用入力端子があるとき性能改善がはかれる
ような半導体装置の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device that can improve performance when there are unused input terminals as a measure to improve the performance of a CMOS gate array.
本発明は、従来技術の欠点をなくすため、ＣＭＯＳ ケ
ー）プレイにおいて、ル入力ゲートのうちｎ−１ゲート
のみ使用する場合に、性能改善のために未使用ＣＭＯＳ
ゲートの片方のトランジスタのドレインとソースを製造
上短絡できるようにしたものである・
すなわち、本発明は、未使用入力に高または低レベルの
空ピン処理を施した状態で、該未使用人力に対応するＰ
あるいはＮ型トランジスタのドレインとソースとを短絡
する半導体装置の製造方法を特徴とする。In order to eliminate the drawbacks of the prior art, the present invention provides an unused CMOS chip to improve performance when only n-1 gates among the input gates are used in CMOS playback.
The drain and source of the transistor on one side of the gate can be short-circuited during manufacturing.In other words, the present invention enables unused inputs to be connected to unused inputs with high or low level empty pin processing. Corresponding P
Alternatively, the present invention is characterized by a method of manufacturing a semiconductor device in which the drain and source of an N-type transistor are short-circuited.
また本発明は、未使用入力に高また低レベルの空ビン処
理を施した状態で、未使用入力に対応するＰあるいはＮ
型トランジスタの片方のゲート唄域部分を取り除く半導
体装置の製造方法を特徴とする。Furthermore, the present invention provides a method for processing P or N corresponding to unused inputs while performing high-level empty bottle processing on unused inputs.
The present invention is characterized by a method for manufacturing a semiconductor device in which a gate region portion of one side of a type transistor is removed.
以下本発明の実施例を第１図および第２図によシ説明す
る。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第１図（α）はＣＭＯ８３人力ＮＡＮＤ回路であるが、
この３人力ＮＡＮＤを２人力ＮＡＮＤとして図のＡ、Ｂ
入力のみ使用する場合、Ｃ入力が未使用端子となる。第
１図（ｂ）および（Ｃ）は、このＣ入力の処理として、
Ｃ入力をスルホール２を通じて電源ＶＤＤに接続し高レ
ベルに固定するものであるが、このままであると、負荷
容量ＯＬを放電するのにＮ型トランジスタＮｌ、Ｎ２．
Ｎ３を用いるため、実際は２人力ＮＡＮＤとして使用し
ているのにもかかわらずトランジスタ３個分のインピー
ダンスが関与し、性能上立下り時間が遅くなる。本実施
例は、（ｂ）図に示すようにアルミ配線１（第１図（α
）の１に相当する）によってＮ型トランジスタＮ１のソ
ースとドレインとを接続し、２人力Ｎ Ａ Ｍ Ｄ Ｉ
ｔ成とするものである。Figure 1 (α) shows a CMO83 human-powered NAND circuit.
A and B in the diagram convert this three-man power NAND into a two-man power NAND.
When only the input is used, the C input becomes an unused terminal. Figures 1(b) and (C) show the processing of this C input.
The C input is connected to the power supply VDD through the through hole 2 and fixed at a high level, but if this continues, the N-type transistors Nl, N2 .
Since N3 is used, the impedance of three transistors is involved even though it is actually used as a two-man NAND, and the fall time is delayed in terms of performance. In this embodiment, aluminum wiring 1 (Fig. 1 (α
), which corresponds to 1 of ), connect the source and drain of the N-type transistor N1.
It shall be made up of t.
第１図（Ｃ）は、入カゲートｃｔ−Ｐ型トランジスタＰ
１のみ残すように製造するものであり、こうすれば第１
図（ｈ）に示すアルミ配線１と同等なものとなシ、２人
力ＮＡＮＤの構成を実現できる・
第２図は本発明の他の実施例を示すものである。第２図
（α）はＣＭＯ８３人力ＮＯＲ回路であり、この３人力
ＮＯＲを２人力ＮＯＲとして図のＡ、Ｂ入力のみ使用し
、Ｃ入力が未使用端子となる場合を示す。第２図＜ｈ＞
？よび（Ｃ）は、このＣ入力の処理として、Ｃ入力を
スルホール４を通じて接地Ｖｓｓに接続し低レベルに固
定するものである。本実施９０は、（ｂ）図に示すよう
にアルミ配線３（第２図（α）の３に相当する）によっ
てＰ型トランジスタＰ３のソースとドレインとを接続し
、２人力Ｎ ＯＲ，構成とするものである。FIG. 1(C) shows the input gate ct-P type transistor P.
It is manufactured so that only 1 remains, and in this way, the 1st
A two-man NAND structure can be realized by using the aluminum wiring 1 shown in FIG. 2(h). FIG. 2 shows another embodiment of the present invention. FIG. 2 (α) shows a CMO83 human-powered NOR circuit, in which this three-person powered NOR is changed to a two-powered NOR, and only the A and B inputs in the figure are used, and the C input is an unused terminal. Figure 2 <h>
? and (C) is to connect the C input to the ground Vss through the through hole 4 and fix it at a low level as a process for the C input. In this implementation 90, the source and drain of the P-type transistor P3 are connected by an aluminum wiring 3 (corresponding to 3 in FIG. 2 (α)) as shown in FIG. It is something to do.
第２図（Ｃ）は、入力ゲートｃｔｒ：ＮＷトランジスタ
Ｎ３のみ残すように製造するものであり、こうすれば第
２図（ｂ）に示すアルミ配線３と同等なものとな）、２
人力ＮＯＲの構成を実現できる・以上述べた方法は現在
世の中で一般的に広く使用されているゲートアレイにお
いて簡単に実現可能であり、ＬＳＩの性能改善がはかれ
るという点でその効果は大変大きい。In FIG. 2(C), only the input gate ctr: NW transistor N3 is left. In this way, it becomes equivalent to the aluminum wiring 3 shown in FIG. 2(b)), 2
A human-powered NOR configuration can be realized.The method described above can be easily realized in gate arrays that are currently widely used in the world, and is very effective in terms of improving the performance of LSIs.
本発明によれば、未使用入力端子があるときに性能改善
がはかれるような半導体装置の製造方法が得られる。According to the present invention, it is possible to obtain a method of manufacturing a semiconductor device in which performance can be improved when there are unused input terminals.
第１図（α）はＣＭＯＳゲートアレイ５人力ＮＡＮＤ基
本回路図、第１図（ｂ）は本発明の一実施例を示す配線
図、第１図（Ｃ）は本発明の他の実施例を示す配約図、
第２図（ａ）はＣｉ Ｍ ＯＳゲートフッ４３人力ＮＯ
Ｒ基本回路図、第２図（ｂ）、 （Ｃ）は本発明の他の
実施例を示す配線図である。Figure 1 (α) is a basic circuit diagram of a CMOS gate array 5-man power NAND, Figure 1 (b) is a wiring diagram showing one embodiment of the present invention, and Figure 1 (C) is a diagram showing another embodiment of the present invention. A distribution diagram showing,
Figure 2 (a) shows Ci M OS gate 43 manual power NO.
2B and 2C are wiring diagrams showing other embodiments of the present invention.
Claims (1)
に高または低レベルの空ピン処理を施した状態で、前記
の未使用入力に対応するＰあるいはＮ型トランジスタの
ドレインとソースとを短絡することを特徴とする半導体
装置の製造方法。 ２、多入力ＣＭＯＳゲートアレイにおいて、未使用入力
に高または低レベルの空ピン処理を施した状態で、未使
用入力に対応するＰあるいはＮ型トランジスタの片方の
ゲート領域部分を取り除くことを特徴とする半導体装置
の製造方法。[Claims] 1. In a multi-input CMOS gate array, with the unused inputs subjected to high or low level empty pin processing, the drain and source of the P or N type transistor corresponding to the unused inputs are 1. A method of manufacturing a semiconductor device, comprising: short-circuiting a semiconductor device; 2. In a multi-input CMOS gate array, the gate region of one of the P or N type transistors corresponding to the unused inputs is removed while the unused inputs are treated with high or low level empty pins. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59184595A JPS6163039A (en) | 1984-09-05 | 1984-09-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59184595A JPS6163039A (en) | 1984-09-05 | 1984-09-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6163039A true JPS6163039A (en) | 1986-04-01 |
Family
ID=16155955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59184595A Pending JPS6163039A (en) | 1984-09-05 | 1984-09-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6163039A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237543A (en) * | 1987-03-26 | 1988-10-04 | Hitachi Ltd | Semiconductor integrated circuit device |
| DE102021110387A1 (en) | 2021-01-29 | 2022-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | INTEGRATED CIRCUIT GEAR AND PROCESS |
-
1984
- 1984-09-05 JP JP59184595A patent/JPS6163039A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237543A (en) * | 1987-03-26 | 1988-10-04 | Hitachi Ltd | Semiconductor integrated circuit device |
| DE102021110387A1 (en) | 2021-01-29 | 2022-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | INTEGRATED CIRCUIT GEAR AND PROCESS |
| US11688731B2 (en) | 2021-01-29 | 2023-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit device and method |
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