JPS6162232A - Two modulus prescaler - Google Patents

Abstract

PURPOSE:To attain high-speed frequency division and low current consumption by using a constant current source of a gate circuit for feedback signal control and one of constant current sources of the 1st stage D flip-flop in common in a frequency synthesizer of a radio receiver. CONSTITUTION:FETs T1/T1a, T2/T2a, T3/T3a whose sources are connected in common are connected as a step as it were and form a load transistor (TR) of a drive TRT4 connected to a signal input terminal 1. Then a common source of the FETT4/T4a is connected to a constant voltage source 11 via an FETTg for constant current source. A signal inputted to terminals 4, 5, 6 is inverted in its phase to a signal inputted to terminals 4a, 5a, 6a and when the FETT1 is turned on, the FETT1a is turned off. Through the constitution above, the circuit T4/T4a corresponding to a NOR gate circuit is connected directly to the constant current source 11 of the 1st stage D flip-flop and incorporated within the 1st stage D flip-flop, then the delay time in the NOR operation is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a two-modulus prescaler circuit suitable for use in a frequency synthesizer of a radio receiver or the like.

[Conventional technology]

As is well known, some wireless receivers such as FM receivers use a frequency synthesizer to generate i number of discrete local oscillation frequencies. This frequency synthesizer divides the oscillation frequency of a voltage controlled oscillator (VCO) using a programmable divider, and controls the divided frequency to match the base frequency to generate a large number of local oscillation frequencies. This normally occurs, but since the oscillation frequency of the VCO is quite high, a high-speed prescaler (prefix 'tva) is required between the VCO and the programmable divider.
A low frequency signal is supplied to the programmable divider.

FIG. 3 is a block diagram showing an example of the configuration of this type of prescaler, which has two division ratios (modular 7,)/
//6. This is a typical GaAs prescaler with ///7. In this figure, 1 is a signal input terminal;
2 is a frequency division output terminal, 3 is a frequency division ratio switching signal input terminal, DF
Fl, DFF2゜D Fl"3 are mask slave type D flip self-flops, TFF'l, TFF'2 are T flip-flops, N0R1, NQ2 are N (JR agate path, (JR is an OR gate circuit.

In this prescaler, the three D flip-flops DFF1 to DFF3 act as a frequency divider with a frequency division ratio of 1/Hiro or 1/9 depending on the signal applied to the frequency division ratio switching signal input terminal 3. T flip-flops T1
1i"Fl, TIi'F2 act as a frequency divider with a frequency division ratio l/lI-. Then, N01 (gate circuit N0R
By controlling the # return signal to the first-stage D flip-flop DFF1 through ORz and the OR gate circuit OR to 1, ///l, or //
The 0th order, which is designed to act as a /7 divider,
Figure φ shows the NoOR gate circuit (JR
l, to (JR2 and first stage D flip-flop f) Fl
! FIG. 2 is a circuit diagram showing a circuit configuration with a mask section of 'l. In this figure, 4.5 is Noah Gate times j! bN(JRI
, 6 is the N0R20 input terminal, and these input terminals 4. 5. 6 includes each component DFF3. (J
R, D1i'F2 and other feedback signals are supplied. In addition, 7 is the output terminal of the mask section of the first stage D flip-flop DF'FI, 8 is the terminal of the costage of DFFI, and 9
is a ground terminal, 10 is a gate bias terminal of a constant current source FET (field effect transistor), 11 is a constant voltage source, R
1°R2 is a load, and TaNTi is a constant %: flow source FET. Each gate of these nine FET-Ta to 'ri is connected to a gate bias terminal 10, and when an appropriate voltage is applied to the terminal 10, each FET-Ta to Ti operates as a constant current source. In this state, the NOR gate circuit N0
When a potential higher than the reference voltage Ref (“H” level) is applied to the RI, N0R20 input terminals 4.5 or 6, the FETs and Tl connected to each of the input terminals 4 to 6 are
~T3 are respectively turned on, and conversely, the reference potential Ref
More than 1. ,.

When applying a low potential (“L” level), FET・'r1～
T3 is turned off.

Figure 3 (c) is a truth table showing the relationship between the levels of input terminals 4 to 6 and the level of terminal 80 when signal input terminal 1 is at the "H" level. 1f/! When r/l is "H"/"L"/"L", the terminal 8 becomes "L" level, and so on.

[Problem that the invention seeks to solve]

By the way, the NOR gate circuit N0RI-,N(Jl(2) of the conventional prescaler circuit described above had the following drawbacks.

+l) Delays the feedback signal and prevents speeding up of the frequency division operation.

In FIG. 3, λ NOR gate circuits N0)Ll,
N(Jl(,2 and three D flip-flops DFF1
The circuit consisting of ~DFF3 directly divides the input signal and determines the maximum operating frequency of this prescaler circuit, and the circuit consisting of D flip-flops IJFF2 and DF11゛3
It will not operate normally unless a complete nine feedback signals from the input signal are input to the first stage D flip-flop DFF1 within one cycle of the input signal. This feedback time is determined by the longest loop in this part, DFF 3→01(1→N0Rz). ).

Therefore, the D7 lip/70 tube DFFI to DFF3 are master-slave type, and their operating time is the individual operating time t.
D? Since it is twice F, that is, 2tDFIF, NO
R gate circuit Na1t, operation time of N0R2 tNoR
Then, the maximum operating frequency fma of this prescaler circuit is
x is expressed by the following formula.

fmax-□kawa(11 2t+2tNoR FF Therefore, although time tD?F and tNOR are short, this prescaler circuit operates at high speed, and NO
It can be seen that R game) NO) Ll, N (JR2) prevents this speed increase.

(21NOR gate circuit N (JRl, N0LLz is 6 in total)
It has constant current sources 'ra, -, , Tf, and consumes a large amount of current.

As mentioned above, two NOR gate circuits N(Jl(.

1. NOO20 Rabbit! The circuit consisting of the three D7 lip/70 tubes DFF1 to DFF3 is designed for high-speed operation, so Iσ is also a part that consumes a lot of current, and the current consumption in this part is the sum of the entire prescaler circuit. It accounts for most of the power consumption. And NOR gate lil! The constant current sources of path N0R1 and N0R2 are H]°
There are six FETs -T a -T f KQ, which is equal to the number of constant current sources in the mask section and slave section of the D flip-flop DFF1. In other words, the current consumption of N (J R1, N U M 2) is equal to the current consumption of one mask slave type D flip-flop, and N (J R gate circuit NURI, N (J 几2) was one of the factors that prevented the prescaler circuit from achieving a low dissipation current.

This invention attempts to solve the above three problems.

[Means for solving problems]

In order to solve the above problems, the present invention has a feature that the constant current source of the gate circuit for feedback signal control 1 and one of the constant current sources of the first stage D flip-flop are made common. [Operation] According to the above configuration, the circuit corresponding to the N(J gate circuit) is directly connected to the constant current source of the first stage D flip-flop, and is incorporated inside the first stage D flip-flop. Therefore, N(Jl(delay time of operation decreases. Also,
Since the constant current source of the N(J)L gate (b) path is also removed, current consumption can also be reduced.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. Figure 1 shows the configuration of a first embodiment of the present invention.
J, and portions corresponding to those in FIG. φ are designated by 4-. Terminals that form a pair with terminals 1 and 4 to 8 have a subscript a added to their reference numbers, and are designated as 1a.

It is shown as 4a. These terminals 1a, 4
The signals from a to 8a are in the opposite phase relationship to the signals from terminals 1.4 to 8.
In Figure 1, the circuit shown in the same picture is equivalent to the circuit (1', jl) in (A).

In the first □□□←), the F whose source ends are commonly connected
ET ” Ts /T+a-Tz /Tza-Ta /
Tsa is connected, so to speak, in a stepped manner and takes the form of a load transistor of the drive transistor T4 connected to the signal input terminal 1. And 1! 'ET-T, /
The common source terminals of T and & are connected to a constant voltage source 11 via a constant current source ET-Tg. In addition, the above PET
The drains of -T and /T1a are connected to terminals 8 and 8a, respectively.

5. In this embodiment, the part surrounded by the broken line in the conventional circuit shown in FIG. It is operated with a constant current source of 1g. Therefore, in comparison with the conventional circuit, the relationship between the input to the part recessed by the broken line and the signal values of terminals 8 and 8a is that when terminal 1 is at the "H" level, that is, the part surrounded by the broken line is active. It is only necessary to consider when the situation is . Therefore,
A description of the operation of the D flip-flop outside the range surrounded by the broken line will be omitted here.

In the circuit shown in No. 1 (8) (b), terminal 4. 5.
6 will be man-powered. The signal is terminal 4a+ 5a, 5a
The phase is opposite to that of the manually input signal, and when FJfflT-TI is on, FhiT-T, & is off. Therefore, for example, terminals 415/6 are each set to "H".
/"L"/"When L1 level, terminal 4 a /
5 a / 5 a is L"/"■(/"H" Lebel FE
T-T, , Tta-”raa is on, T1 amT
,,T, are turned off, and terminal 8/8a is "L"/"H"
level. Thereafter, when the input value of the terminal 4.5°6 is changed in the same manner and the output value of the terminal 8.8a is determined, the result is as shown in the truth table of FIG. 1(c). This result is shown in Figure φ (
This matches the truth table shown in (c), and it can be seen that the circuit within the broken line in FIG. 1(b) is logically equivalent to the circuit within the broken line in FIG.

Then, OR1゜NO to the N0R-gate circuit in Fig. φ
The circuit corresponding to I(, 2 is the D flip-flop DFF
D flip-flop D
Since it is built into F k' 1, the delay time of the OR operation is short. In addition, since the constant current source for the NOF gate circuit (Jl(, 1, NOO20) has also been centered, the current consumption is also low.

For example, from the prescaler (b) path, the T flip-flops T F F l and T F I! '2, that is, the percentage of the //Q-115 prescaler circuit is an important part that almost determines the speed and power characteristics of the entire circuit, but this t/≠115 prescaler circuit According to a computer simulation of this embodiment, the maximum operating 1fi wave number is approximately 15 times higher and the current consumption is approximately J/≠ times higher than that of the conventional circuit shown in Figures Yang and Hong, confirming sufficient effects. was completed. In addition, the device parameters of tj a As F lt T used in the simulation are that the gate width of the FET is 70 μm.

The gate length was 10 μm, and the threshold voltage was aλ■.

Next, FIG. 2 shows the structure of the fourth embodiment of the present invention.
JR and two N (O 几1, N to JR gate circuit
(J) L2 constant current source and %D flip-flop DlI
'lI'' 1 constant current source is used in common. In Fig. 2 (b), 313a is the molecule M number switching signal input terminal, and 12.128 is the T-clip/70-tube TFF.
Input terminal for feedback signal from I (Fig. 3), 13.13a
is the input fM element for the feedback signal from the T7 rip/70 tube TFF2, and the input terminal 3゜12.13 constitutes the three input terminals of the gate circuit.
As can be easily inferred from the first embodiment, the operation of the gl path is equivalent to the operation of the circuit shown in the second leg ←), and can achieve the same operation and effect as the first embodiment.

〔Effect of the invention〕

As explained above, the present invention provides high-speed and low-power comodulus prescaler circuits. The gate circuit, which was a major factor preventing current conversion, was built into the first stage D flip-flop by making the constant current source common.
Delays in gate circuits can be removed. Although there is some deterioration in the operating speed of the D flip-flop due to this gift and the inclusion of the gate circuit in the D7 lip/70 tube, the effect of eliminating the delay of the l'li gate circuit is greater.

Therefore, compared to conventional circuits, the present invention has the advantage of enabling high-speed frequency division operation and reducing current consumption.

Furthermore, the effects of simplifying the pattern design of the prescaler IC and reducing the chip area can be expected.

lA drawing f! IF car explanation Figures 1 and 2 are block diagrams and circuit diagrams showing the configurations of the first and third embodiments of the present invention, respectively.
Figure (C) is a truth table showing the operation of the mounting section of the first embodiment, the third diagram is a block diagram showing the configuration of a conventional prescaler circuit, and Figures (A) and (B) are the same prescaler circuit. FIG. 44(c) is a block diagram and circuit diagram showing the configuration of the prescaler circuit, and a truth table showing the operation of the prescaler circuit.

D F F l,,,,,, first stage D flip-flop, D F F2, DFH'3...D flip-flop, N0kL1, N0R2...01
(Gate circuit (gate circuit), O″R...(J
It gate episode! (gate circuit), Ta~Tf...
・・Field effect transistor (constant current source of gate circuit),
'vg... Field effect transistor (one of the constant current sources of the first stage D flip-flop).

(c) Figure 1 ; 乎

Claims (1)

[Claims] A current-switching circuit using field-effect transistors includes a plurality of frequency-dividing D flip-flops and two or more gate circuits that control a feedback signal fed back to the first-stage D flip-flop of the D flip-flops. and a constant current source provided separately in each of the D flip-flops and each gate circuit, the constant current source of the gate circuit and the constant current source of the first stage D flip-flop; A 2-modulus prescaler circuit characterized by having one of the following in common.