JPS6159515A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To form a system clock signal with high accuracy by assembling a clock oscillator generating a reference clock signal in one chip to adjust simply the oscillating frequency externally. CONSTITUTION:An output signal from a NAND circuit 30 of a clock oscillator 25 incorporated in one chip microcomputer is extracted via inverters 31, 32 and fed back to the circuit 30 via a resistance circuit 33. Built-in terminals P1-P8 are provided across each resistive element (R2-R8) being a component of the circuit 30 and fuses H2-H8 are connected respectively to the elements R2-R8. Thus, the fuse is removed externally to adjust the oscillating frequency of a reference clock signal outputted from the oscillator 25 and each resistance value of the resistors R2-R8 is adjusted to form a system clock signal with high accuracy.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a six-circuit device that is programmable and intended for logic processing, and allows unspecified users to easily control their own system. Ji to be able to run
This invention relates to a one-chip microcomputer made up of four components.

[Background Art] A microcomputer can provide a unique system ff for each user to a constant number of users by changing software configured by a program.
1ll ill is to be executed,
In this respect, it can be used very effectively.

In particular, it can be effectively used in small-scale systems, especially in simple sequence control.

But 1. In microcomputers that have been widely used in the past, the system clock signal that drives and controls the operating section and the memory section built into the microcomputer is based on the reference clock oscillation I that is set externally to the microcomputer. Signals from several components are introduced through an external connection terminal section set in the microcomputer, and a clock signal for driving the system is formed based on a reference clock signal input through this terminal. There is.

Therefore, it is impossible to set the operating state of a microcomputer configured on a single chip without connecting such a separate external circuit mechanism, and it is inevitably necessary to connect external connection terminals to the microcomputer. Increased number and its built-in configuration? ff was in a sloppy state, which was an obstacle to effectively utilizing its capabilities as a microcomputer.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned points. In particular, an oscillation IJIN that generates a system clock signal is effectively incorporated and set in a single-chip element. hand,
IrJ is a one-chip microcomputer that allows each user to use it more effectively by making it possible to effectively adjust and set its oscillation frequency from the outside and effectively reducing the number of external connection terminals.
ll (I'm trying to do it.

[Means for solving the problem] In other words, in the one-chip microcomputer according to the present invention, a clock generator 1i'A3 that generates the WL%u clock signal is incorporated and set in the same depth. However, with this clock oscillator, the oscillation frequency cannot be easily adjusted externally. The connecting portions of the respective resistance elements are constructed by fuses. By selectively cutting off the fuse portions connecting the respective resistance elements from the outside, the oscillation frequency of the reference clock signal can be set and controlled.

[Function] That is, by incorporating and setting the reference clock oscillator in the same depth, there is no need to connect and set an external oscillation circuit when the bamboo is in use. In this case, when the chip is completed, for example, by selectively passing a large current through the fuse section that connects the plurality of resistive elements that constitute the resistive circuit that sets the oscillation frequency of the oscillator. These fuses can be selectively adjusted, and the oscillation frequency can be adjusted reliably and easily.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

, FIG. 1 shows the overall configuration of a microcomputer 10 configured in a one-chip state, and this microcomputer includes a program memory 12 driven by a program counter 11, a data memory 13, and an arithmetic unit
4. Input circuits 15 to 17, output circuits 18.19, input/output circuits 20.21, test mode counter 2.2, etc., and further controlled by power supply voltage detection circuit 23, reset flag bit generation circuit 24, clock oscillator 25 is built-in, and for this oscillator 25 c1. The oscillation stop command is given when the L power supply voltage detection circuit 2G detects a state in which the power supply voltage has decreased.

Here, this microcomputer 10 is basically 0M
The basic elements are a P-channel MO8t-transistor (hereinafter referred to as PMO3, whose threshold voltage is represented by ρ) and a threshold voltage VT of approximately 1V. (14 has been completed.

FIG. 2 does not show the circuit state of the clock oscillator 25 built into the microcomputer 10 as described above, and the output signal from the NAND circuit 30 is connected to the inverter 31.
．． 32, take out and roughly Fl 'II e.g. 8
It has a size of 41 and is fed back to the NAND circuit 30 via a resistor circuit 33 in which resistive elements R2 to R8 are connected in series and a resistor R1. And the above NAND circuit 30
and the inverter 31 circuit so that it is in parallel state! 7
134 is connected and set, and the output signal from the voltage detection circuit 2G is connected to the NAND circuit 30.
The oscillator 25 is supplied as a signal, and the oscillation operation of the oscillator 25 is stopped when the power supply voltage drops below a predetermined voltage. That is, this oscillator 25 has a resistance circuit lB5.
3 and a guest room 34.

Here, each resistance element R2 to constitute the resistance circuit 33
There are built-in terminals P in the parts corresponding to each side of R8.
1 to P8 are set, and each resistance element R2
~Fuses H2~H8 respectively in parallel with R8
The connection is now set.

In the oscillator 25 constructed as Jfe in this way, the built-in capacitor fi34 has its capacitance ffll1itI set by the gate oxide film between the polysilicon film and the diffusion layer formed on the semiconductor substrate. , in order to eliminate the parasitic diode at point a, the a side is made to be ff1 (I) on the polysilicon film side. Also, each of the resistor elements R2 to R8 forming the resistor circuit 33 to (1) Each is composed of a polysilicon film, and its +
The M configuration is shown in FIG. 3 using the resistor element R2 as an example.

In FIG. 3, a low antibody pattern 33a is formed of a polysilicon thin film, and the built-in terminals P1 and R are located close to both ends of this pattern 33a.
2, the resistance terminal portions 33b and +3 are connected to each other.
and 330 are configured.

A fuse 33d made of the same polysilicon is formed to connect the terminal portions 33b and 330. In this case, if a large current is set to flow through the fuse 33d portion compared to the resistor pattern 33a, and a large current is supplied between terminals P1 and R2 (+JL), only the fuse 33d portion is blown. is set to

The clock oscillator 25, which is configured as J:, is configured to be completely built into the microcomputer 10 as described above. In this case, the oscillation frequency or oscillation period of this oscillator 25 needs to be adjusted and set accurately. The oscillation period of this oscillator 25 is
It is determined by the relationship between the value C of 4 and the resistance IUR of the resistor circuit y833, and therefore the built-in capacitor value C,!
: It is sufficient if the resistance value R can be manufactured with high precision. However, the polysilicon resistor has an error of about ±30% depending on the semiconductor manufacturing loft, and some kind of adjustment means is required after the semiconductor manufacturing process. below,
The means for adjusting the oscillation period will be explained.

In the oscillator 25 constructed as described above, in the initial state of manufacture, the built-in terminals P1 to P8 are isolated by fuses.

In this state, when the resistance R1=r, the oscillation period to
seek.

Next, let ta be the final desired firing cycle.

R= (ta/lo) r Measure the resistance IUR of the low 1 circuit 33,
Thereafter, fuses are selected and burned out between built-in terminals P1 to P8 so as to obtain the above-mentioned calculated R.

Here, in the resistance element section shown in FIG. 3, the resistance value of the fuse 33d portion is set to 40Ω, while the resistance value of the resistor pattern 33a portion is approximately 40 KΩ.
A voltage is applied between the built-in terminals P1 and 22 to an extent that the resistor pattern 33a is not burnt out.

Built-in terminals P1 to P8 are not terminals that need to be brought out externally by wire bonding, etc., so they cannot be connected to the IC.
It is sufficient to form the pad in a free space within the chip using a small pad.

Here, as specifically shown in FIG. Oscillator 2
The oscillation period of 5 can now be adjusted to an accuracy of 1.6%. In addition, the overall resistance value of the resistor circuit that constitutes this oscillation circuit can be adjusted in the range from r to 3r, and therefore, for example, the resistance value of a polysilicon film may have an error of ±30% depending on the manufacturing loft. Even in the presence of , the oscillation period can be adjusted to the key 7 with a degree of 1.6%.

FIG. 4 shows f for this microcomputer 10.
Fi! This shows a specific circuit example of the voltage detection circuit 23 for generating the reset 1 to command when the ffl pressure has decreased.
Vtn)≦Vcc<V (1) When II, PROM41 with a high threshold voltage is turned off, and NMO3
42 is set to the on state, therefore, in this state, the potential at point f is set to L level, and the output signal from inverter 43 is set to H level. This output signal is IJt supplied to the reset flag bit generation circuit 24, and a reset flag is supplied and set inside this integrated circuit.

Here, the inverter 43 has a threshold voltage VT (7
) It is composed of a low PROM 41 and an NMO 845, so that an H level signal is reliably output even when r V cc < V tpl+J.

[V cc > V tip J tl),
When PMO8,+1 turns on, the impedance of NIVIO842 becomes PN=I.
Since it is much more sensitive than that of O841, if Vcc exceeds Vt1llll even slightly,
The potential at point f becomes H level. Therefore, in this state, the output of the inverter 43 is at the L level, and the reset
~The command output becomes L level, and reset 1~ is canceled.

NMO84G is for monitoring this output voltage.
Outputting to child N. That is, while the reset signal is at H level, it outputs L level, and in the normal operating state, that is, while the reset signal is at L level, it is set to high impedance.

FIG. 5 does not show the structure of the Vs voltage detection circuit 26 that controls the clock oscillator 25, and shows a differential voltage comparator 5 with an intentionally set offset voltage Vof.
1 to 1 (n). When the potential difference between the differential input Ω point and h point of the comparator 51 exceeds the above 0" due to a change in the voltage Vcc, the output point i becomes H level, and D The type flip 70 knob 54 is now set.In other words, the output Q of this flip 70 knob 54 becomes H level, and this output Q is supplied to the control gate of the oscillator 25 (NAND circuit 30 in FIG. 2). As a result, the oscillator 25 starts operating as a multivibrator.The oscillation start voltage VS is determined by the following equation.

Vs = ((rl + r2)/r2) Vof, where rl and r2 are resistors 52 and 53 set on the input side of the comparator 51, respectively.

The output signal from the clock oscillator 25 is supplied to the two-phase lock generator 5G to form non-overlapping two-phase clocks φa and φb.
j, J= and φb are supplied to other circuit sections as system clock signals.

The flip 70 knob 54 functions to guarantee the clock widths of the clocks φa and φb when the power supply voltage drops and clock oscillation stops. Of course, when the power supply voltage Vcc decreases to a state where rVcc<Vs J, one output point of the comparator 51 goes to L level asynchronously with the clock. By sampling at the rising edge of the clock φa, the clock signal is stopped in synchronization.

FIG. 6 shows a specific circuit example of the differential voltage comparator 51 having the above-mentioned offset voltage.
The point is that the two threshold voltages Vt are set to different states. That is, PMO861f7)Vr
But other PMOS! :While the VT of the PMOS 62 is about 1V, it is higher, about 2V. This VT difference becomes the off-state voltage. This difference in VT can be freely and precisely set by controlling the dose of ion implantation of boron (B) in the manufacturing process of this integrated circuit. Also, in terms of -112, this V・' is approximately 2 mV/'C)
Although it has a 3 degree coefficient, the adjustment coefficient between Vtp and Vtpl+ is extremely small, approximately 0.1 mV/"C, and the offset voltage set in the comparator 51 is set to a very stable IU. be done.

In FIG. 5, the AND-OR gate 55 receives input from the universal lock PA 10i in the death 1-mode.

FIG. 7 shows the configuration of the test circuit related to the test counter 22, and the signal from the input terminal PAO is
Normally, signals within the power supply voltage range are sampled by clocked inverters 7G and 7z and transmitted to the internal data bus. Furthermore, the signal from the terminal PAO (noted above) is supplied to the negative terminal of the comparator T1 to which the offset voltage .Or2 is intentionally set as described above. When this input becomes a voltage state below -Vor2, the comparator 7
The output point of 1 becomes H level, is sampled by clocked inverters 72 and 73, and the reset state of the D-type shift register 74 is released.

When this state is maintained, the H signal is shifted to the shift 1 to register 74 by \γ]; of the program counter signal, that is, by overflow. Then, for the second overflow signal, J,
Then, the output of 02 of the shift register 74 becomes 1'' level, and the connected flip-flops 78 of PCO boards 1 to 3 are set to lot the data bits to L', and the ROM dump mode is entered. At the same time, the RO from AND gate 75
The M dump mode signal is output inside the integrated circuit.

Then, when 03 of the shift register 14 becomes H level due to the third overflow signal, the ROM dump mode can be automatically switched to the external instruction mode. While in this mode, PAO
It is necessary to execute the terminal test mode, but by setting the clock phases of clocked inverters 72, 73, 76, and 77 inversely as shown in the figure, the PΔO port can be executed without dividing the test mode by h7. It allows input signals to be sent inside the integrated circuit. The shift register 74 that loads this test mode has its Q2 and Q3 output terminals set to the ROM dump test 1~ mode signal and the external instruction test mode signal, respectively, so that entering the test mode can be performed using the P
The A O terminal must be kept below -Vof2 for a long time until the program counter overflows by 20, and exiting from test mode can be done only when it becomes below -Vof2 for one machine cycle, so that it can be avoided by mistake. This prevents it from being put into test mode.

Instructions in the external instruction test mode are input serially from the PBO input/output)j terminal at time and minute υ1. Furthermore, data in the internal ROM in the RO1vl dump mode is outputted serially and time-divisionally from the PBO input/output terminal.

As a means for adjusting the oscillation period of the clock oscillation n325, a means for blowing out the fuse by providing an internal butt as shown in FIG. 2 has been described. As shown in the figure, a MOS switch circuit 81 may be used to selectively supply and set the current to blow the fuse. In this case, the switch circuit 81 has an input/output terminal P80 and an input terminal P80.
It is controlled by shift 1 to register 82 which are controlled by a signal from the AO, and these shift 1 to register 82 are reset by a test mode signal. For example, the N channel switch N of the switch circuit 81
In order to turn both S1 and PS2 on, the shift register 82 is set so that the contents of the shift register 82 become rl'1ooooooOJ in the test mode, and then the power supply Vcc is supplied to the PCO terminal. If a current is applied to the fuse, the specified fuse will be blown.

FIG. 9 shows an example in which a plurality of resistance elements constituting the resistance circuit 33 are connected in parallel, and in this case, the fuses connected in series with the bfS resistance elements are selectively blown. As a result, the oscillation signal period of this oscillator 25 becomes If:1. 'l It is something that is adjusted.

In the case of the oscillator 25 shown in FIGS. 2 and 9, the means for blowing out the fuses connected to each resistor element may be other than blowing them out with current as shown in the above explanation. Alternatively, it may be burned out using laser light, for example.

F Effect of the invention J As described above, according to this invention, in the state of one chip (
It is possible to effectively set up a built-in clock oscillator that generates a reference clock signal in a microcomputer installed at the bottom of the cylinder, and when manufacturing this microcomputer, each of the 14 parts that make up the oscillator is simultaneously installed in a membrane chamber. It is possible.

Moreover, in the reference clock oscillator constructed in this way, the oscillation signal period can be effectively adjusted, and it is possible to form a system clock signal of sufficiently high quality. This will have a very large effect on improving the performance and handling of microcomputers.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the ll'i configuration state of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a circuit diagram illustrating a clock optical oscillator internally defined in the microcomputer. , FIG. 3 is a diagram showing one of the resistor elements of the oscillator, and FIG. 4 J-3 and FIG. 5 are circuit configuration diagrams each illustrating an example of a voltage detection circuit built into the microcomputer. , Fig. 6 is the same as Fig. 5 above.
The circuit shown in the figure is a circuit diagram explaining a comparator formed by (π), and FIG.
The figures are circuit configuration diagrams illustrating other examples of clock oscillators. DESCRIPTION OF SYMBOLS 10... Microcomputer, 12... Program memory, 14... Enclosing part, 22... Test mode counter. 23... Vr voltage detection circuit, 24... Reset l-flag bit generation circuit, 25... Clock oscillator, 26
... Vr voltage detection circuit, 30 ... NAND circuit, 31
．． 32... Inverter, 33... Resistance circuit, 33a
... Resistance pattern, 33b, 33c... Terminal section, 33d... Fuse, 34... Capacity ■. Figure 1 Iku Kyyumiko Iku Genkyumi Zen Iryutate φ Figure 2 Figure 31%j Figure 4 Figure 70

Claims (2)

[Claims] (1) A one-chip microcomputer characterized in that the programmable controller includes a program memory, data memory, program section, input/output circuit, etc., and is configured with a built-in clock oscillator that includes an oscillation frequency adjustment element. . (2) The above clock oscillator is equipped with a resistance circuit in which a plurality of resistance elements are connected in series as an oscillation frequency setting element, and each resistance element of this resistance circuit is configured to be connected and set in sequence by a fuse circuit element. 2. A one-chip microcomputer according to claim 1, wherein said fuse circuit element is selectively controlled to be disconnected.