JPS6158982B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device with a high degree of integration and a fast read/write speed.

Semiconductor memory continues to become more highly integrated and larger in capacity, especially RAM (Random Access Memory).
In most cases, 16K bits per chip is becoming the standard product. As higher integration and larger capacity progress, the number of transistors used in memory cells decreases, and some 16K-bit RAM memory cells have a one-transistor, one-capacity configuration. Most of them have a charge-coupled structure in which no transistor is included in the memory cell. An example of the structure is shown in FIGS. 1 and 2.

In Fig. 1, the bit line for reading and writing data is an n ⁺ area provided in the P area, and the address line (word line) for commanding writing and reading of data is an Al or other line provided through an oxide film. The electrode is made of a metal such as Mo or a low-resistance semiconductor such as polysilicon. Near the surface of the P region adjacent to the bit line n ⁺ region, P-type ions such as B (boron) are implanted to increase the impurity density by about an order of magnitude. When the impurity density changes along a part of the surface in this way, the P region surface potential changes depending on the voltage V _G applied to the word line, as shown in FIG. 1c. Figure 1c shows a resistivity of 15Ω-cm (9×10 ¹⁴ cm
^-3 ) P region a and 1Ω-cm (1.5×10 ¹⁶ cm ^-3 ) b
The surface potential φs of is shown. FIG. 1c also shows the dependence of the surface potential of c on V _G when B ions are implanted into the P region of 15 Ω-cm. As shown in FIG. 1c, the lower the resistivity, the lower the surface potential φs. Therefore, when a voltage of about 10 V is applied to the word line, a certain surface potential distribution occurs as shown in ^FIG . For example, if the voltage is maintained at about 5V, electrons are stored in the area where the surface potential of the storage area is sufficient, and data is stored. At the time of reading, when the word line potential is lowered to about the ground potential, a surface potential distribution as shown in FIG. 1b is obtained, the stored electrons flow to the bit line, and data is read out. When the potential of the word line is raised to the write potential, if the potential of the bit line where no data is written is raised to the same level as the word line potential,
No data is written. In this way, data can be written to a desired intersection of a matrix formed by word lines and bit lines, and data can be read from a desired point. In the example in Figure 1, writing,
Three potentials were required on the word line for storing and reading, but by adding only two potentials to the word line,
FIG. 2 shows an example in which writing, storing, and reading are all performed.

For example, 2 of B and P are placed in the P area which becomes the storage area.
By performing staged ion implantation and changing the flat band voltage, the surface potential with respect to the voltage V _G applied to the word line becomes as shown in FIG. 2c.
When applying voltage during writing and reading, the surface potential of the transfer area becomes positive and higher, but
When the applied voltage during storage is almost close to ground potential, the storage region has a higher positive potential.

These charge-coupled RAM memory cells have a high integration density, but because they only utilize surface conduction, they have low mobility and slow read and write speeds.

An object of the present invention is to eliminate the drawbacks of the above-mentioned charge-coupled RAM memory cells and to provide a semiconductor memory device with faster write and read speeds and an equivalent or higher degree of integration.

FIG. 3 shows an example of the cross-sectional structure of a RAM memory cell of the present invention configured in a lateral structure. In FIG. 3, a P substrate is provided with an n ⁺ region 11 and an accumulation region n ^- 13, which serve as bit lines, and a P ⁺ region 14 is a region for isolation. 15 is SiO ₂ , Si ₃ N ₄ ,
It is an insulating layer made of Al ₂ O ₃ , P ₂ O ₅ or a combination of a plurality of these, and 16 is a word line made of a metal such as Al or Mo or a low resistance semiconductor such as polysilicon. The n ⁺ , P ⁺ , and n ^- regions may be produced by diffusion techniques, ion implantation, or other methods.
The impurity density in the n ⁺ region is about 10 ¹⁷ to 10 ²¹ cm ^-3 , P ⁺
The area is about 10 ¹⁶ ~ 10 ²¹ cm ^-3 , the P area is 10 ¹⁴ ~ 10 ¹⁷ cm
^-3 , and the n ^- region is about 10 ¹² to 10 ¹⁶ cm ^-3 . n ^-
The impurity density and dimensions of the region are selected such that the n ^- region becomes a depletion layer almost or completely depending on the diffusion potential of the Pn ^- junction or the P ⁺ n ^- junction. The thickness of the insulating layer is set to be thinner 20 above the P region and thicker above the n ⁺ region and n ⁻ region. It is also effective to make the thickness of the insulating layer on the n ^- region thinner than on the n ⁺ region.
Further, in some cases, the insulating layer 20 in the thin portion shown in FIG. 3 is made into an insulating layer having a higher conductivity than other regions, so that there is almost no difference in thickness. When writing data, a positive voltage is applied to the word line 16. for example
It is 10V. In the case of a memory cell in which data is not written, the potential of the bit line may be set to the same level as that of the word line. Most of the accumulated electrons are accumulated on the side near the bit line, reflecting the diffusion potential difference of the P ⁺ n ^-junction . Therefore, during reading, the accumulated potential quickly flows to the bit line. Figure 4 is
The structure is almost the same as that shown in FIG. 3 by epitaxially growing an n ^- region on a P ⁺ substrate. The P region 12, which serves as a potential barrier layer for controlling the flow of electrons, is formed in a shape surrounding the bit line 11 by diffusion, ion implantation, or the like. The n ^- region 13 is almost or completely a depletion layer due to the diffusion potential difference of the P ⁺ n ^- junction. The operation is almost the same as that shown in FIG. 3, and electrons are accumulated near the surface of the n ^- region 13. In the structures shown in Figures 3 and 4, the accumulation region is a high-resistance n ^- region, and the accumulated electrons are distributed not only near the surface but also far into the interior, which affects conduction such as mobility. Although the contributing parameters are quite close to the values of the semiconductor bulk itself,
Since it is surface conductive, its mobility and diffusion coefficient are small. Connect such memory cells to word lines,
A semiconductor memory is constructed by arranging the required number of bit lines in a matrix.

Up to now, we have described examples of high-speed and high-density memory array sections, but these structural examples are of course not limited to these; for example, it is also possible to use structures with completely opposite conductivity types. The individual structures are not limited to this either. For example, it goes without saying that there may be an impurity distribution in regions 12, 13, etc. in FIGS. 3 and 4.

The access time of semiconductor memory mostly depends on the buffer circuit present in the interface of the input/output section. If a static induction transistor with high input impedance, small interelectrode capacitance, and large conversion conductance is used in this input/output buffer circuit, the access time will be extremely short. As described above, the structure in which a static induction transistor is used in the buffer circuit can of course be applied to the present invention as is. Moreover, almost all of the power consumption of a semiconductor memory is accounted for by the sense amplifier section that amplifies the read signal. Since the number of sense amplifiers is equal to the number of bit lines, the number of sense amplifiers increases as the storage capacity increases, leading to an increase in power consumption. Therefore, configuring the sense amplifier with a static induction transistor that has high input impedance, small interelectrode capacitance, high conversion conductance, and high voltage amplification, and whose characteristics hardly deteriorate even under low current conditions is an effective way to reduce power consumption. It is extremely effective.

The various structural examples described herein can be manufactured using conventionally known diffusion ion implantation techniques, crystal growth techniques, various wet or dry selective etching techniques, thermal oxidation techniques, CVD techniques, and the like.

The present invention is a memory equivalent to a charge-coupled memory that can be highly integrated, and is constructed by developing the concept of a static induction transistor that injects carriers across a potential barrier provided around each bit line. Since it utilizes the conductivity of the semiconductor bulk, it can write and read at high speed, and has the feature that it can be integrated more highly for the same amount of charge storage than conventional devices. Ori,
Its contribution to the semiconductor industry, which is aiming for high speed, low power, and large capacity, is extremely high, and its industrial value is remarkable.

[Brief explanation of the drawing]

1A to 1C and 2A to 2C show charge-coupled RAM memory cells, and FIGS. 3 and 4 show embodiments of cross-sectional structures of RAM memory cells of the present invention configured in a lateral structure.

Claims (1)

[Scope of Claims] 1. A high impurity concentration region of the same or opposite conductivity type as the bit line, which is to become an accumulation region, is The resistance region is selected to have an impurity density and various dimensions that will almost become a depletion layer, the bit line region, the opposite conductivity type region, and the storage region are configured almost horizontally, and a thin insulating layer is formed on the opposite conductivity type region. A word line electrode is formed through a material layer, and the height of the potential barrier is equal to the difference between the diffusion potential created between the opposite conductivity type region and the bit line region and the storage voltage created between the storage region and the opposite conductivity type region. The opposite conductivity type region is substantially depleted by the two diffusion potentials and has a height sufficient for carriers accumulated in the storage region and carriers in the bit line region. A required number of word columns are formed in which memory cells are formed as much as possible and configured to cause carriers to flow into and out of the storage region by lowering the height of the potential barrier by the voltage applied to the word line electrode. What is claimed is: 1. A semiconductor memory comprising at least a part of the intersections of a matrix consisting of lines and a required number of rows and matrix lines for bit lines. 2. A high-resistance region of the same or opposite conductivity type as the bit line, which is to become an accumulation region, and a high resistance region above the bit line, which is to become an accumulation region, are The thickness of the first insulating layer provided on the bit line is at least thinner than the first insulating layer provided on the bit line, and the high resistance region of the same conductivity type or the opposite conductivity type from the bit line is almost completely covered. The impurity density and various dimensions are selected to be a depletion layer, and the bit line region, opposite conductivity type region, and storage region are configured almost horizontally, and a word is formed on the opposite conductivity type region through a thin insulating layer. A line electrode is formed, and the height of the potential barrier is determined by the diffusion potential between the opposite conductivity type region and the bit line region and the storage voltage created between the region and the storage region. The opposite conductivity type region is substantially depleted by the two diffusion potentials and is formed to have a height sufficient for carriers accumulated in the storage region and carriers in the bit line region, and is formed to have a height sufficient for carriers accumulated in the storage region and carriers in the bit line region. A memory cell configured to cause carriers to flow into and out of the storage region by lowering the height of a potential barrier by a voltage applied to an electrode is connected to a memory cell using a required number of word column lines and a required number of word column lines. What is claimed is: 1. A semiconductor memory comprising at least a part of an intersection point of a matrix consisting of row lines and matrix lines for bit lines. 3. A high resistance region of the same conductivity type as the high impurity density region is formed on a substrate comprising a high impurity density region of the opposite conductivity type to the bit line comprising the high impurity density region, and the bit line is formed on the same surface as the bit line. A high resistance storage region of the same conductivity type as the line is arranged through a region of opposite conductivity type, and the thickness of the insulator layer on the region of the opposite conductivity type is thinner than the thickness of the insulator layer on other regions, and the bit line region, the opposite conductivity type region;
The storage region is configured almost horizontally, and a word line electrode is formed on the opposite conductivity type region with a thin insulating layer interposed therebetween, and the height of the potential barrier is such that the opposite conductivity type region is similar to the bit line region. determined by the diffusion potential created between the diffusion potential and the storage voltage created between the storage region, and the opposite conductivity type region is substantially depleted by the two diffusion potentials,
The potential barrier is formed to have a height sufficient for the carriers accumulated in the storage region and the carriers in the bit line region, and the height of the potential barrier is lowered by the voltage applied to the word line electrode. Memory cells configured to allow carriers to flow into and out of the memory cell are arranged at at least some of the intersection points of a matrix consisting of a required number of word column lines and a required number of bit line row lines. Features of semiconductor memory.