GB1602362A - Semiconductor memory devices - Google Patents

Description

(54) IMPROVEMENTS IN SEMICONDUCTOR MEMORY DEVICES (71) We, ZAIDAN HOJIN HANDOTAl KENKYU SHINKOKAI, of Kawauchi, Sendaishi, Hiyagi-ken, Japan, a body corporate organized according to the laws of Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to a semiconductor memory, and more particularly to a high-speed and high-density semiconductor memory, and is a Divisional Application filed on Application No. 6699/78 (Serial No. 1602361).

Semiconductor memories are under development for higher integration density and larger capacitance. In random access memories (RAM), the density of 16 kilobits per chip is now popular. As the integration density has increased to such a level, a reduction in the surface occupation area per memory cell will be required accordingly.

In most of the 4 kilobit RAM's, one memory cell is formed with one lateral transistor structure, while in most of the 16 kilobit RAM's, the transistor structure is further simplified into the charge coupled type. In both cases, the basis concept or the equivalent circuit of a memory cell is "one transistor per memory cell" and this will not be simplified further. Namely, in a memory cell, there is a region for storing information, another region for extracting this information to the outside of the cell, and a further region between these two for controlling the transfer of the memory. Then, the integration density of memory cells in a semiconductor memory is determined largely by the surface occupation area of one transistor which works as a memory cell. The so called MOS FET type memory cell and the charge coupled device type memory cell can be roughly classified as the surface structure cell which inevitably accompany relatively large surface occupation area. Furthermore, since the electron and the hole mobilities in the surface of a semiconductor body (surface mobilities) are usually lower than those in the bulk (bulk mobilities) due to various surface state such as trapping levels (for example in silicon the surface mobility is about one third to one fifth of the bulk mobility), the carrier transit time becomes low in the surface region and the high speed operation is at least partially limited thereby.

In a normal type of bipolar junction transistor, charge carriers which carry the main current are allowed to flow by diffusion in a current-controlling base region. The base region should not be totally depleted in order to achieve well-saturated I-V characteristics.

We have already proposed a new type of field effect transistor (now called "static inductor transistor") which has a very short channel length and a very small series resistance from the source to the pinch-off point, resulting in non-saturating drain current versus drain voltage characteristics. The channel region is formed with a high-resistivity semiconductor region and can be easily pinched off by the gate bias voltage including the built-in voltage.

When the base region of a bipolar junction transistor is arranged to have a high resistivity and a small thickness so as to be easily depleted by a collector voltage, nonsaturating I-V characteristics similar to those of the static induction transistor will result.

According to the present invention, there is provided a semiconductor memory device formed in a semiconductor body including at least one memory cell which comprises: (a) a source semiconductor region of one conductivity type including a low-resistivity portion; (b) a bit line formed with a conducting material electrically connected to said lowresistivity portion; (c) a storage semiconductor region of said one conductivity type arranged separately from said source region and formic a first electrode of a capacitor for storing signal charge; (d) means for forming a second electrode of said capacitor; and (e) a base semiconductor region having a high resistivity of the opposite conductivity type, located between said source and storage regions and arranged to form a control lable current path for charge carriers therebetween, said base semiconductor region having low impurity doping characteristics and dimensions such that base semiconductor region is substantially depleted by the built-in voltage at junction with said source and storage regions and forms a potential barrier for said charge carriers and that the potential barrier is controllable by the voltage applied to said bit line and said second electrode means.

The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, in which: Figure 1A is a diagrammatic partial sectional view of a preferred form of a memory device; and Figures 1B to 1D are diagrammatic partial sectional views which illustrate the steps in the manufacture of the memory device shown in Figure 1A.

It will be appreciated that the embodiment shown in Figure 1A has been divided out of the parent Application No. 6699/78 (Serial No. 1602361) having originally been positioned after the embodiment disclosed in Figure 35 of the parent Application.

For the sake of clarity, it is not proposed to repeat all the constructional details of the memory device shown in Figure 1A and reference should be made to the various embodiments of the parent Application.

It is sufficient to state that the embodiment of Figure 1A differs from those of the parent Application in that it has no gate structure.

The memory device according to the preferred embodiment illustrated in the drawings utilizes a bipolar type structure having a punch-through base region. The whole base region is substantially depleted by the builtin voltages of the emitter-base junction and the base-collector junction.

Although the bipolar type structure in dudes regions of two conductivity types in the current path (i.e. emitter and collector regions of one conductivity type and a base region of the other conductivity type), the base region of the punch-through bipolar type transistor is substantially depleted.

Therefore. the conductivity type of the base region will lose most of its meaning except that the base region contains ionized impuritv atoms of such polarity as will repel out charge carriers from the emitter and the collector regions. Therefore, the punchthrough type bipolar transistor may be relarded as being analogous to the unipolar transistor.

ReferrinlY specifically to Figure IA, the memory device comprises a p-type substrate 715. n tvpe source reasons 713 embedded in the substrate 715. an n type region 7131, n type storage regions 711, p type base regions 754 between the source region 713 and storage regions 711, an insulator layer 718 located between and extending over the storage regions 711 which form the memory cells of the memory device, and a metal region 721 located on the storage regions 711 through the insulator layer 718. An electrode for the base region 754 may be additionally provided. The base region 754 is formed with a p type (or intrinsic) high resistivity semiconductor. The storage cell is provided with a metal-insulator semiconductor structure.

The writing operation into the memory cell is achieved mainly by a positive voltage applied to the metal region 721 constituting a so-called column electrode 721, whereas the reading operation is mainly carried out by the positive voltage applied to source regions 713 constituting a so-called row electrode 713. If additional electrodes are provided in the base region 754, the operational performance of the memory cell will be substantially improved.

Figures 1B, 1C and 1D diagrammatically show the various steps of manufacture of the memory cells shown in Figure 1A.

Figure 1B shows the step where the n+ type source region 713 is formed by selectively diffusing an n type impurity material such as arsenic, antimony or phosphorus using a silicon oxide layer 785 formed on t:le p f.vpe silicon substrate 715 as a mask.

The substrate has an impurity concentration around 101 to 1020 cm-3. The silicon oxide layer 785 shown in Figure 1B is removed after the diffusion. In Figure 1C, using the well-known epitaxial growth method, an n type layer 7131 with an impurity concentration around 101 to 1017 cm-3, a p type layer 754 with an impurity concentration around 1010 to 1017 cm-3, and an ji type layer 711 with an impurity concentration around 1010 to 1007 cm5 are formed, and then a silicon oxide layer 716 is formed by oxidation. In the oxide layer 716, a mask pattern is formed by means of a photolithographic technique, and the recessed portion is formed through the p type layer 754 (in some cases the p type layer 754 may remain) by relying on a directional etching technique such as plasmaetching, chemical etching or sputter etching.

Then, an insulating material may be formed or deposited and a surface electrode may be deposited thereon. Base electrodes may be formed by a directional deposition of an insulator material on the bottom of the recessed portion, selective etching of the insulator, and evaporation or deposition of metal or polycrystalline silicon.

In a modified form, the source region and the storage region may be intercllanned.

Thus, the source region may be formed adjacent to the semiconductor surface, in which case a bit line is directly formed thereon.

The storage region is embedded in the semiconductor body and forms a pn junction capacitor with the substrate. Furthermore, isolation of respective cells can be achieved by other methods known in this technical field. Planar structure also con be used.

WHAT WE CLAIM IS:- 1. A semiconductor memory device formed in a semiconductor body including at least one memory cell which comprises: (a) a source semiconductor region of one conductivity type including a low-resistivity portion; (b) a bit line formed with a conducting material electrically connected to said lowresistivity portion; (c) a storage semiconductor region of said one conductivity type arranged separately from said source region and forming a first electrode of a capacitor for storing signal charge: (d) means for forming a second electrode of said capacitor; and (e) a base semiconductor region having a high resistivity of the opposite conductivity type, located between said source and storage regions and arranged to form a controllable current path for charge carriers therebetween, said base semiconductor region having low impurity doping characteristics and dimensions such that base semiconductor region is substantially depleted by the built-in voltage at junction with said source and storage regions and forms a potential barrier for said charge carriers and that the potential barrier is controllable by the voltage applied to said bit line and said second electrode means.

2. A semiconductor memory device according to Claim 1, wherein said semiconductor body includes at least one recessed portion which substantially surrounds said base semiconductor region.

3. A semiconductor memory device according to Claim 1, further comprising an insulator region filling said recessed portion.

4. A semiconductor memory device according to Claim 1, wherein said storage region is located adjacent to the surface of said semiconductor body and said source region is embedded in said semiconductor body registered with said storage region.

5. A semiconductor memory device according to Claim 4, further comprising an insulator layer formed on said semiconductor body and sandwiched between said second electrode means and said storage region.

6. A semiconductor memory device constructed substantially as herein described with reference to and as illustrated in Figure 1A of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (6)

**WARNING** start of CLMS field may overlap end of DESC **. The storage region is embedded in the semiconductor body and forms a pn junction capacitor with the substrate. Furthermore, isolation of respective cells can be achieved by other methods known in this technical field. Planar structure also con be used. WHAT WE CLAIM IS:-

1. A semiconductor memory device formed in a semiconductor body including at least one memory cell which comprises: (a) a source semiconductor region of one conductivity type including a low-resistivity portion; (b) a bit line formed with a conducting material electrically connected to said lowresistivity portion; (c) a storage semiconductor region of said one conductivity type arranged separately from said source region and forming a first electrode of a capacitor for storing signal charge: (d) means for forming a second electrode of said capacitor; and (e) a base semiconductor region having a high resistivity of the opposite conductivity type, located between said source and storage regions and arranged to form a controllable current path for charge carriers therebetween, said base semiconductor region having low impurity doping characteristics and dimensions such that base semiconductor region is substantially depleted by the built-in voltage at junction with said source and storage regions and forms a potential barrier for said charge carriers and that the potential barrier is controllable by the voltage applied to said bit line and said second electrode means.

2. A semiconductor memory device according to Claim 1, wherein said semiconductor body includes at least one recessed portion which substantially surrounds said base semiconductor region.

3. A semiconductor memory device according to Claim 1, further comprising an insulator region filling said recessed portion.

4. A semiconductor memory device according to Claim 1, wherein said storage region is located adjacent to the surface of said semiconductor body and said source region is embedded in said semiconductor body registered with said storage region.

5. A semiconductor memory device according to Claim 4, further comprising an insulator layer formed on said semiconductor body and sandwiched between said second electrode means and said storage region.

6. A semiconductor memory device constructed substantially as herein described with reference to and as illustrated in Figure 1A of the accompanying drawings.