JPS6158306A - Parallel connection circuit of transistor - Google Patents

Abstract

PURPOSE:To almost simultaneously turn on and turn off transistors connected in parallel and, at the same time, to suppress the voltage between the collector and emitter of each trasistor, by connecting diodes to the winding of a current transformer for balacer. CONSTITUTION:Diodes D1 and D2 which limit voltages generated in the primary winding NP and secondary winding NS, both of which have he same number of turns, of a ucrrent transformer T1 for balancer are connected with both ends of the windings NP and NX, respectively. Therefore, voltages induced in the windings NP and NX are suppressed o lower than the forward drop voltages of the diodes D1 and D2. Since these voltages are resepctively supplied top the emitters of transistors (TR) Q1 and Q2 connected in parallel with each other, both the TRs Q1 and Q2 can almost simultaneously be turned on and turned off. In addition, voltages between the collector and emitter of the TRs Q1 and Q2 can be suppressed to lower than the sum voltage of the supply volt age and the forward drop voltages of the diodes D1 and D2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that connects a plurality of transistors in parallel.

[Conventional technology]

FIG. 2 is a diagram showing a conventional parallel connection circuit of transistors. In the figure, Q□ and Q2 are transistors connected in parallel, respectively.

are the feedback winding N1, the drive winding N2, and the control winding N.

The drive transformer T1 is a balancer current transformer that equalizes the current flowing through each of the transistors Q1 and Q2, and the current transformer has a primary winding N and a secondary winding N having the same number of turns. are connected in series to the emitters of transistors Q□ and Q2, respectively.

Ru. 1.2 is the main circuit terminal. Note that the black dots attached to each winding indicate the same polarity.

Next, the operation of this circuit will be explained. Now, each transistor Q
If U and Q2 share the load current equally, the emitter currents of transistors Q, Q2 and Q2 are equal. Therefore, the winding Np% of the balancer current transformer T8
The current flowing through Ns is also equal, and winding N and winding N3
Since they have opposite polarities and the same number of turns, the magnetic fluxes formed by the respective currents cancel each other out, and the voltage across the winding N %N8 is zero.

However, if the current balance collapses and, for example, the current of transistor Q1 increases more than the current of transistor Q2, the change in the magnetic flux of this increased current causes windings N and N (therefore also winding N3) to A voltage e1 of the polarity shown is induced.

Since the voltage e1 has the opposite polarity to the voltage e0 of the drive winding N2, the bias of the transistor is reduced and the emitter current is completely reduced. At the same time, the voltage induced in winding N3 -
el has the same polarity as the t-pressure e0 of the drive winding N2, deeply biasing the transistor Q2 and increasing the emitter current. This results in transistors Q, ,Q
2 current imbalance is compensated for. The above explanation is only about the increase in the current of the transistor Q, but the same explanation can be applied to the decrease in the current. The same applies to transistor Q2.

[Problem that the invention seeks to solve]

However, in this conventional circuit, the transistors Q□ and Q
2, the transistors Q1 and Q2t
- It is difficult to turn off or turn off at the same time, so the voltage 2E (E is the power supply voltage applied between the main circuit terminals 1 and 2) is applied to the transistor that turns on slowly when turning on, and to the transistor that turns off quickly when turning off. Since the voltage is applied, it rarely requires a transistor with a high withstand voltage.

[Means to resolve the problem]

In order to eliminate the above drawbacks, the present invention provides a parallel connection circuit of transistors, characterized in that diodes are connected to both ends of the primary winding and/or secondary winding of the current transformer for balancer. It is something to do.

[For production]

Since the present invention has the above configuration, when the transistor is turned on and off, the voltage induced in each winding of the balancer current transformer connected to the emitter of the transistor is lower than the forward drop voltage of the diode. By suppressing the voltage, each transistor connected in parallel can be operated to turn on and turn off almost simultaneously, and the voltage between the collector and emitter of each transistor can be lowered to the sum of the power supply voltage and the forward drop voltage of the diode. can be suppressed to

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention.

In the same figure, the primary winding M having the same number of turns of the current transformer T1
Tt8Et-limiting diodes D1.N and Tt8Et-limiting diodes D1.
D, is connected.

Next, the operation of this circuit will be explained. Transistor Q1, Q
Since the operation in the state where both transistors Q1 and Q2 are on is the same as the explanation in FIG. 2, the explanation will be omitted, and the operation when the transistors Q1 and Q2 are turned on and turned off will be explained.

The operation when the first transistor is turned on will be explained. For example, when the transistor is turned on, if transistor Q8 tries to turn on before Q2, a voltage with the black dot as positive is induced in the winding N, and the diode D2?
! - a current iD2 flows through it. For this reason, transistor Q
Since the emitter voltage of transistor Q2 is a negative voltage -vD2 (vD2 is the forward drop voltage of diode D2), a forward bias is applied between the pace and emitter of transistor Q2, which acts to turn on transistor Q2. On the other hand, the emitter voltage of transistor Q1 is a positive voltage vD2
As a result, a reverse bias is created between the pace and emitter of the transistor Q1, which acts to turn off the transistor Q1t''.In this way, when the transistors are turned on, the transistors Q, , Q, and t- can be turned on almost simultaneously. , transistor Q2
The collector-emitter voltage can be suppressed to 'iE+vD2.

Next, the operation when the transistor is turned off will be explained. For example, if transistor Q1 tries to turn off before Q2 when the transistor is turned off, a voltage that makes the black dot negative is induced in the winding Np, and the diode D
1 Current 'DI flows throughout. Therefore, the emitter voltage of the transistor Q1 becomes a negative voltage -vD8 (vDl is the forward drop voltage of the diode D□), and the space between the pace and emitter of the transistor Q1 becomes a forward bias, turning on the transistor Q1. act. On the other hand, the emitter voltage of the transistor Q2 becomes a positive voltage vD, and a reverse bias is created between the pace and emitter of the transistor Q2, which acts to turn off the transistor Q2. In this way, when the transistors are turned off, the transistors Ql and Q2k- can be turned off almost simultaneously, and the transistor Q0
The collector-emitter voltage can be suppressed to 'kE+VD1.

FIG. 3 is a diagram showing another embodiment of the present invention. In the same figure, T1 and T2 have a turns ratio of 1:n between the primary winding N, 1, N and the secondary winding N, Ns□, and p2
81 Use a current transformer of the same standard, secondary winding N, 1, N8□
Diodes D1 and D2 are connected to both ends of the diodes D1 and D2, respectively. What is this embodiment and the embodiment shown in FIG.

In the embodiment of FIG. 1, the voltage induced in the windings connected in series with the emitters of the transistors Q, , Q2 is transferred to the diodes D1, D2 connected across the windings.
In contrast, in this embodiment, the voltage generated in the secondary windings N, , %N, □ of the current transformers T, , T2 is indirectly limited by limiting the voltage. Vessel T
, , When attempting to limit the voltage of the T20 primary winding N SN , the operation is almost the same as that described in the embodiment of FIG. 1, with the only difference being the roller pi p2 , and the same effects can be obtained. In particular, in this embodiment, the turns ratio between the primary and secondary windings of the current transformers T1 and T2 is 1:n, so the current flowing through the diodes D□ and D2 t- is the same as that of the embodiment shown in FIG. Since 1/n of the current tm is sufficient for the diodes (Dl, D, t) used in

FIG. 4 is a diagram showing another embodiment of the present invention. In the figure, T1 to T3 are primary windings Np0 to Np3 and secondary windings Ns1 to N8. The current transformers are of the same standard and have a turns ratio of 1:n, and diodes D□ to D3 are connected to both ends of the first-order wires N, 1 to Np3, respectively. This embodiment differs from the embodiment of FIG. 1 in that it has two transistors Q1 and Q.
The difference is that the circuit is a parallel connection circuit of three transistors Q1 to Q3, whereas the circuit is a parallel connection circuit of three transistors Q1 to Q3, but the operation is almost the same as that described in the embodiment of FIG.
The effect of this can be obtained.

In the above embodiments, a circuit in which 12 or 6 transistors are connected in parallel has been described, but a circuit in which four or more transistors are all connected in parallel can be similarly implemented. Further, the number of diodes connected to both ends of the winding is not limited to one, but several diodes connected in series can be used as necessary.

〔Effect of the invention〕

As described above, the present invention provides a circuit in which a plurality of transistors are connected in parallel, in which the primary winding or the secondary winding of a current transformer is connected in series to the emitter of each of the transistors, and the current transformer's primary winding or secondary winding is This is a parallel connection circuit of transistors characterized in that diodes are connected to both ends of the primary winding and/or the secondary winding. Since the present invention has such characteristics, it is possible to turn on and turn off a plurality of transistors connected in parallel almost simultaneously, and the voltage between the collector and emitter of each transistor can be reduced. It can be suppressed to a value equal to or less than the sum of the power supply voltage and the forward drop voltage of the diode.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a conventional parallel connection circuit of transistors, and FIGS. 3 and 4 are diagrams showing another embodiment of the present invention. is. 1.2... Main circuit terminal Ql, Q2. QB...Transistor T...Drive transformer No...Feedback winding N2...Drive winding N3...Control winding T1. T2. T3...Current transformer for balancer N, , N, N, N...
・Primary winding pi p2 p3 N,, N, □, N82. Nl53...Secondary winding D
1. D2. D, ... Diode patent applicant Origin Electric Co., Ltd. 1 Figure 2 Figure 1.2-11 ball Fu) Main circuit! Itaima Q+, Qz −−−1−ra〉ji entered To−−Ku Kintora〉Epijira〉 is condolence service

Claims (1)

[Claims] In a circuit in which multiple transistors are connected in parallel, the emitter of each transistor is connected to the primary winding or secondary winding of a current transformer.
1. A parallel connection circuit of transistors, characterized in that secondary windings are connected in series, and diodes are connected to both ends of the primary winding and/or secondary winding of the current transformer.