JPS59201682A - Inverter - Google Patents

Inverter

Info

Publication number
JPS59201682A
JPS59201682A JP58075225A JP7522583A JPS59201682A JP S59201682 A JPS59201682 A JP S59201682A JP 58075225 A JP58075225 A JP 58075225A JP 7522583 A JP7522583 A JP 7522583A JP S59201682 A JPS59201682 A JP S59201682A
Authority
JP
Japan
Prior art keywords
coil
current
balance
winding
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58075225A
Other languages
Japanese (ja)
Inventor
Yoshihiro Nakajima
中島 良浩
Hitoshi Kono
等 河野
Kiyoshi Ikemura
池村 清
Yoshiyuki Takashina
高階 良幸
Yoshiaki Ito
伊東 義明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Priority to JP58075225A priority Critical patent/JPS59201682A/en
Publication of JPS59201682A publication Critical patent/JPS59201682A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To enable to balance currents at both normal and transient times and to simplify the structure by connecting balance transformers to both ends of a load and taking a current balance. CONSTITUTION:The connecting point of transistors 1a, 3a is connected to the starting end of a coil C11a of a balance transformer BL11, the connecting point of transistors 1b, 3b is connected to the finishing end of a coil C11b, and the winding end of the coil C11a and the winding starting end of the coil C11b are connected to one end of a load L. The connecting point of transistors 2a, 4a is connected to the starting end of the coil C12 of a balance transformer BL12, the connecting point of transistors 2b, 4b is connected to the finishing end of the coil C12b, and the winding end and starting end of the coils C12a, C12b are connected to the other end of the load L. The currents of the transistors la, 1b- 4a, 4b driven in parallel are balanced by the transformers BL11, BL12.

Description

【発明の詳細な説明】 この発明は複数のスイッチング素子を並列接続して使用
するインバータに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter using a plurality of switching elements connected in parallel.

高周波大電力のインバータにおいては、小容量の高周波
トランジスタを複数個並列に接続して使用する場合が多
いが、この場合、高速スイッチング状態における各トラ
ンジスタの電流バランスをとることが非常に重要な問題
となる。
High-frequency, high-power inverters often use multiple small-capacity, high-frequency transistors connected in parallel, but in this case, balancing the current of each transistor during high-speed switching is an extremely important issue. Become.

従来、この電流バランスをとる方法として、第1図に示
すように各トランジスタのコレクタ回路に各々バランス
リアクトルLrを挿入し、これによシ過渡時の電流バラ
ンスをとる方法、あるいは各トランジスタのエミッタ回
路に各々抵抗を挿入し、これによシ定常時の電流バラン
スをとる方法等が知られている。なお、第1図において
符号Eは直流電源、符号りは負荷、符号りはフライホイ
ーリングダイオードである。しかしながら、これらの方
法はバランスリアクトルLrまたは抵抗による電力損失
が大きく、このためインバータ効率が著るしく低下する
という欠点がある。ちなみに、第1図に示す回路におい
て、各トランジスタの電流を5OA、バランスリアクト
/I/ I、 rのインダクタンスを54 H、インバ
ータの出力周波数を20Kuzとすると、全バランスリ
アクトルLrによる損失の合計は となる。また、各トランジスタのエミッタ回路に抵わし
ン押入し、各抵抗によって0.2Vの電圧降下を発生さ
伊たとすると、全抵抗による損失の合計は、 50(A)Xo、2(lX0.5X8=40(W)とな
る。なお、上式におけるrO,Jはデユーティ比50チ
を意味している。
Conventionally, as a method of balancing this current, as shown in Fig. 1, a balancing reactor Lr is inserted into the collector circuit of each transistor, and this balances the current during a transient period, or an emitter circuit of each transistor is used. A known method is to insert a resistor into each of the two, thereby balancing the current during steady state. In FIG. 1, the symbol E is a DC power supply, the symbol E is a load, and the symbol E is a flywheeling diode. However, these methods have the disadvantage that power loss due to the balance reactor Lr or resistance is large, and therefore the inverter efficiency is significantly reduced. By the way, in the circuit shown in Figure 1, if the current of each transistor is 5OA, the inductance of balance reactor/I/I, r is 54H, and the output frequency of the inverter is 20Kuz, the total loss due to all balance reactors Lr is Become. Also, if a resistor is inserted into the emitter circuit of each transistor and a voltage drop of 0.2V is generated by each resistor, the total loss due to all resistors is 50(A)Xo, 2(lX0.5X8= 40 (W). Note that rO and J in the above equation mean a duty ratio of 50 degrees.

また、従来、定常時の電流バランスおよび過渡時の電流
バランス乞共にとることができる回路として第2図に示
す回路が知られている。この図に示す回路は、並列駆動
されるトランジスタla。
Further, a circuit shown in FIG. 2 is conventionally known as a circuit that can maintain current balance during steady state and current balance during transient state. The circuit shown in this figure includes transistors la driven in parallel.

1b〜4a、4’bの各コレクタ回路に各々バランス変
成器BL、−BL4を介伸したものである。
Balance transformers BL and -BL4 are respectively extended to the collector circuits 1b to 4a and 4'b.

なお、図におけるドツトは各コイルの巻始めを示す。こ
の図に示す回路において、トランジスタla、lbの各
コレクタ電流エム 、1B(第3図(イ)参照)が盆く
同一の場合は、バランス変成器BL1の各コイルの両端
間に電圧が発生し々い。
Note that the dots in the figure indicate the beginning of winding of each coil. In the circuit shown in this figure, if the collector currents M and 1B of the transistors la and lb (see Figure 3 (a)) are the same, a voltage will be generated across each coil of the balance transformer BL1. Many.

しかし、例えばTA) T Bとなった場合は、バラン
ス変成器BL、の各コイルに第3図(イ)に示す向きの
電圧が各々発生して電流エム 、TBの相違を補正し、
また、TA〈よりとなった場合は各コイルに図と逆向四
の電圧が発生して電流エム 、TBの相違を補正する。
However, if, for example, TA) TB occurs, voltages in the directions shown in FIG.
Furthermore, when TA is greater than TA, a voltage in the opposite direction to that shown in the figure is generated in each coil to compensate for the difference in currents Em and TB.

これによシ、電流エム 、IBが各々、過渡時および定
常時において常に同一となる。
As a result, the currents M and IB are always the same during transient and steady states, respectively.

ところで、この第2図に示す回路には次の様な問題がお
る。すなわちトランジスタla、lbのカットオフ時間
には、通常、μSオーダーのバラツキが発生する。いま
、例えば第3図(ロ)に示すように、トランジスタ1a
がカットオフ状態に移行し、これに対し、トランジスタ
1bが未だオン状態におるとすると、まず、電流丁^が
減少し始める。電流Thが減少すると、バランス変成器
BL%の作用によシ亀流TBも減少する。これに対し、
負荷¥L流Thは同一電流を保とうとするため、電I&
Th+rBの減少分がダイオードp、を通して流れ、し
たがって、ダイオードD、が導通状態となり、図に示す
点P1の電位が直流電源Eの負電圧端子の電位と等しく
なる。ここで、トランジスタ1bが未だオン状態にある
と、バランス変成器BL、のコイルC2の両端電圧EB
が電源電圧Evに等しくなり、したがってコイ、11/
 Q 、の両端電圧Eムが+im E vかつ図に示す
向きとなり、この結果、トランジスタ1aのエミッター
コレクタ間に電圧2Evが印加される。次に、トランジ
スタ1bがカットオフし、これにより、電流エム、より
が共に0となると、全ての負荷電流ILはダイオードD
、を介して供給され、また、トランジスタla。
By the way, the circuit shown in FIG. 2 has the following problems. That is, the cutoff times of transistors la and lb usually vary on the order of μS. Now, for example, as shown in FIG. 3(b), the transistor 1a
When the transistor 1b shifts to the cut-off state and, on the other hand, the transistor 1b is still in the on state, the current d begins to decrease. When the current Th decreases, the torque current TB also decreases due to the action of the balance transformer BL%. On the other hand,
Since the load\L current Th tries to maintain the same current, the electric current I&
The decrease in Th+rB flows through diode p, so diode D becomes conductive, and the potential at point P1 shown in the figure becomes equal to the potential at the negative voltage terminal of DC power supply E. Here, if the transistor 1b is still in the on state, the voltage EB across the coil C2 of the balance transformer BL
is equal to the power supply voltage Ev, and therefore Coi, 11/
The voltage Em across Q is +im E v and in the direction shown in the figure, and as a result, a voltage 2 Ev is applied between the emitter and collector of the transistor 1a. Next, transistor 1b is cut off, so that both currents M and Y become 0, and all load current IL is transferred to diode D.
, and also the transistor la.

lbの各エミッターコレクタ間電圧が共にXVとなる。The emitter-collector voltages of lb are both XV.

なお、トランジスタi’ a 、 t bのオン時間に
バラツキがある場合も上述した動作と略同様の動作が行
われろ。
Incidentally, even when there are variations in the on-time of the transistors i'a and tb, substantially the same operation as described above is performed.

このように、第2図に示す回路にあっては、トランジス
タのエミッターコレクタ間に、過渡的に電源′喝圧EV
の培の電圧が印加される。したがつて、φIJえば電源
電圧Evを300(v)とし、また、トランジスタ耐圧
を、女全度を力線して最大印加電圧の1.5倍とすると
、 300x2x1.5=900 (v) の耐圧のトランジスタが必要となる。しかしながら1.
牧10KIlz以上の高周波で使用するトランジスタの
耐圧は、ぎいぜい6oo (v)程度でおる。
In this way, in the circuit shown in FIG.
A voltage of 100 mL is applied. Therefore, for φIJ, if the power supply voltage Ev is 300 (v) and the transistor breakdown voltage is 1.5 times the maximum applied voltage using the force line as a line of force, then 300x2x1.5=900 (v). A voltage-resistant transistor is required. However, 1.
The withstand voltage of transistors used at high frequencies of 10Kilz or higher is approximately 6oo (v) at most.

したがって、第2図に示す回路は、特に高周波。Therefore, the circuit shown in FIG. 2 is particularly suitable for high frequencies.

高電圧のインバータにおいては災用化がむずかしいとい
う問題がある。
There is a problem with high voltage inverters that it is difficult to put them into use.

この発明は以上の事情に鑑み、定常時および過渡時の電
流バランスを共にとることができ、また、高周波、高電
圧のインパークにも適用でき、さらに、従来のものに比
べて構成も簡単なインバータを提供するもので、負荷の
一端を、バランスンとるべき電流の大きさに逆比例する
巻線比を有しかつ互いに磁気結合された第1.第2のコ
イルの各巻始めおよび巻終りに接続し、前記第1.第2
のコイルの各巻終シおよび巻始めを各々バランスをとる
べ1電流の線路に接続し、また、前記負荷の他端を、バ
ランスをとるべき電流の大きさに逆比例する巻線比を有
しかつ互いに磁気結合された第3、第4のコイルの各巻
始めおよび巻終りに接続し、AjJ記M3 )第4のコ
イルの各巻終シおよび巻始めを各々バランスをとるべき
電流の線路に接続してなるものでおる。
In view of the above circumstances, this invention is capable of balancing the current during both steady and transient conditions, is applicable to high frequency and high voltage impark, and has a simpler configuration than conventional ones. This invention provides an inverter in which one end of the load is connected to a first inverter having a winding ratio inversely proportional to the magnitude of the current to be balanced and magnetically coupled to each other. The second coil is connected to the beginning and end of each winding of the first coil. Second
The end and beginning of each turn of the coil are connected to a line of the current to be balanced, and the other end of the load has a winding ratio inversely proportional to the magnitude of the current to be balanced. and connect to the beginning and end of each winding of the third and fourth coils which are magnetically coupled to each other, and connect the end and beginning of each winding of the fourth coil to the current line to be balanced. It's something that will happen.

以下、図面を参照しこの発明の詳細な説明する。第4図
はこの発明の第1の実施例の構成を示す図であり、この
図においてトランジスタla。
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 4 is a diagram showing the configuration of the first embodiment of the present invention, and in this figure, the transistor la.

3aの接続点がバランス変成器13LHのコイルC11
11の巻始めに接続され、トランジスタlb。
The connection point of 3a is the coil C11 of the balance transformer 13LH.
The transistor lb is connected to the beginning of the winding No. 11.

3bの接続点がコイルO+1bの巻終りに接続され、コ
イルOuaの巻終シおよびコイルC1工)の巻始めが各
々共通接続された後負荷りの一端に接続されている。ま
た、トランジスタ2a、4aの接続点がバランス変成器
B L、、のコイル012aの巻始めに接続され、トラ
ンジスタ2b、4bの接続点がコイルC+zbの巻終り
に接続され、コイル012&10+zbの各巻終りおよ
び巻始めが共通接続された後負荷りの他端に接続されて
いる。この場合、コイルOha 、Cub  の巻数お
よびコイルCl2m+0+zbの巻数は各々同一でおる
The connection point of 3b is connected to the end of coil O+1b, and the end of coil Oua and the beginning of coil C1 are each connected to one end of the commonly connected rear load. Further, the connection point of transistors 2a and 4a is connected to the beginning of winding of coil 012a of balance transformer BL, , the connection point of transistors 2b and 4b is connected to the end of winding of coil C+zb, and the end of each winding of coils 012&10+zb and The beginning of the winding is connected in common and then the other end of the load is connected. In this case, the number of turns of the coils Oha and Cub and the number of turns of the coil Cl2m+0+zb are the same.

以上の構成において、まず、トランジスタta。In the above configuration, first, the transistor ta.

11+、4a、4bが同時にオン状態となると、負荷り
に矢印Y、方向の電流が流れ、次いでトランジスタla
、lb、4a、4bがオフ、トラ/ジスタ2a、2b、
3a、3bがオンとなると、負荷りに矢印Y!方向の電
流が流れ、以下、上記動作が繰返光されることにより負
荷りへ交流電流が供給される。との場合、並列駆動され
るトランジスタIa、lb〜4a、4bの各電流はバラ
ンス変成器BL、、、BL、2によって第2図の場合と
同様の原理でバランスされる。
When 11+, 4a, and 4b are turned on at the same time, a current flows in the direction of arrow Y through the load, and then transistor la
, lb, 4a, 4b are off, tiger/jista 2a, 2b,
When 3a and 3b are turned on, the arrow Y! A current flows in the direction, and the above operation is repeated, thereby supplying alternating current to the load. In this case, the currents of the transistors Ia, lb to 4a, 4b driven in parallel are balanced by balance transformers BL, . . . BL, 2 on the same principle as in the case of FIG.

次に、第4図に示す回路の電流切換時における動作を第
5図を参照して説明する。いま、例えばトランジスタl
aがオフ状態へ移行し、一方、トランジスタlbが未だ
オン状態にあるとすると、まス、トランジスタ1aのエ
ミッタ電流TAが減少し、この減少に伴い、バランス変
成器BL、、の作用によりトランジスタlbのエミッタ
亀a T Bも同様に(iff流Thと同−甑を保ちつ
つ)減少する。一方、負荷電流ILは同一電流を保とう
とするため、′亀圀8^+よりの減少分がダイオードD
Next, the operation of the circuit shown in FIG. 4 during current switching will be described with reference to FIG. 5. Now, for example, the transistor l
Assuming that a transitions to the OFF state and, on the other hand, the transistor lb is still in the ON state, the emitter current TA of the transistor 1a decreases, and with this decrease, the transistor lb increases due to the action of the balance transformer BL, . The emitter a T B decreases similarly (while maintaining the same value as the if flow Th). On the other hand, since the load current IL tries to maintain the same current, the decrease from 'Kamekuni8^+' is the diode D.
.

を通して供給され、これによりダイオードD、が゛導通
状態となり、点P、の電位が直流電源Eの負電圧端子の
電位0に等しくなる。すなわち、トランジスタlaのエ
ミッターコレクタ間に電圧EVが印加される。この時、
トランジスタlbが未だオン状態にあると、点P3の電
位が+E■9点P!の電位がOとなることからコイル0
11□、 Qllbの各両端電圧が共に図に示すように
y:v/2となる。
As a result, the diode D becomes conductive, and the potential at the point P becomes equal to the potential 0 at the negative voltage terminal of the DC power source E. That is, voltage EV is applied between the emitter and collector of transistor la. At this time,
If transistor lb is still in the on state, the potential at point P3 is +E■9 point P! Since the potential of the coil becomes 0, the potential of the coil becomes 0.
The voltages across both terminals of 11□ and Qllb are y:v/2 as shown in the figure.

そして、トランジスタibもオフ状態となり、電流Xl
 、 丁nが共にOになると、負荷電流Tbはダイオー
ドDa  、Dbを介して均等に供給される。
Then, transistor ib is also turned off, and current Xl
, Dn both become O, the load current Tb is equally supplied through the diodes Da and Db.

なお、トランジスタla、1bのオン時間にバラツキが
ある場合も上述した動作と略同様の動作が行われる。
Note that even when there are variations in the on-times of the transistors la and 1b, substantially the same operation as described above is performed.

このように、第4図に示す回路にあっては、過渡的状態
においても、トランジスタla、lb・・・の各エミッ
ターコレクタ間に印加される電圧の最大1直が電源電圧
Bvであり、したがって、第2図に示す従来の回路の1
/2の電圧しか印加されない。また、第4図の回路はバ
ランス変圧器BL、、。
In this way, in the circuit shown in FIG. 4, even in a transient state, the maximum voltage applied between the emitters and collectors of transistors la, lb... is the power supply voltage Bv, and therefore , one of the conventional circuits shown in FIG.
Only a voltage of /2 is applied. In addition, the circuit shown in Fig. 4 is a balance transformer BL, .

B L、、の数が第2図のものの半分で済む利点も得ら
れる。
There is also an advantage that the number of B L, , is only half that of the one in FIG.

第6図はこの発明の第2の実施例の構成を示す図であり
、この図に示す実施例は並列1JiA動されるスイッチ
素子の数が3個の場合でおる。この実施例においてスイ
ッチ素子5a、5b、5ck!びスイッチ素子8a、8
b、8cがオン状態になると、負荷りに矢印Y1方向の
電流が流れ、また、スイッチ素子6a、6b、6cおよ
びスイッチ素子7a、7b、7cがオン状態になると、
負荷りに矢印Y、方向の電流が流れる。ここで、バラン
ス変圧器BL、、はライン!、およびl、に流れる電流
のバランスをとるもので、各コイルの巻数比は1:lで
るる。また、バランス変圧器BL□はラインl、および
14に流れる電流のバランスをとるもので、ライン13
に流れる電流とライン7I4に流れる電流の比が2:l
であることから、コイルC+5a とC!+sbとの巻
数比が1=2となっている。同様に、バランス変成器B
 L、4はラインβ、。
FIG. 6 is a diagram showing the configuration of a second embodiment of the present invention, and the embodiment shown in this figure is for a case where the number of switching elements operated in parallel at 1JA is three. In this embodiment, switch elements 5a, 5b, 5ck! and switch elements 8a, 8
When b and 8c are turned on, a current flows in the direction of arrow Y1 through the load, and when switch elements 6a, 6b, 6c and switch elements 7a, 7b, and 7c are turned on,
Current flows in the direction of arrow Y through the load. Here, balance transformer BL,, is line! , and l, and the turns ratio of each coil is 1:l. In addition, the balance transformer BL□ balances the currents flowing in lines 1 and 14, and
The ratio of the current flowing to line 7I4 and the current flowing to line 7I4 is 2:l.
Therefore, coil C+5a and C! The turns ratio with +sb is 1=2. Similarly, balance transformer B
L,4 is line β,.

16の電流バランスをとるもので、その巻数比は1:1
、バランス変成器B ’Ltaは2インl?、l。
16 current balance, the turns ratio is 1:1
, the balance transformer B'Lta is 2 in l? ,l.

の電流バランスをとるもので、コイfi/ Q 16 
aおよびcr6bの巻数比は1:2でるる。
It balances the current of Koi fi/Q 16
The turns ratio of a and cr6b is 1:2.

第7図はこの発明の第3の実施例の構成を示す図である
。この図に示す実施例は並列駆動されるスイッチ素子の
数が4個の場合であシ、スイッチ索子5a〜5dおよび
9a〜9dがオン状態になると、負荷りに矢印Y8方向
の電流が流れ、スイッチ索子6a〜6dおよび7a〜7
dがオン状態になると、負荷りに矢印Y1L方向の電流
が流れる。
FIG. 7 is a diagram showing the configuration of a third embodiment of the present invention. In the embodiment shown in this figure, the number of switch elements driven in parallel is four, and when the switch cables 5a to 5d and 9a to 9d are turned on, a current flows in the direction of arrow Y8 to the load. , switch cords 6a-6d and 7a-7
When d is turned on, a current flows in the direction of arrow Y1L through the load.

この回路の場合、バランスコイルBL18〜B Lza
の各巻数比はいずれもl:1である。
In the case of this circuit, balance coils BL18 to B Lza
The turns ratio of each is 1:1.

なお、バランス変成器BLは磁路を閉じた磁性有料に2
1面のコイルを巻回したものでもよく、あるいは、磁性
材料をなくし、2個のコイルを密に磁気結合したもので
もよい。
In addition, the balance transformer BL has 2 magnetic fluxes that close the magnetic path.
It may be made by winding a coil on one side, or it may be made by eliminating the magnetic material and tightly magnetically coupling two coils.

以上説明したように、この発明によれば負荷の両端に各
々バランス変成器を接続して電流バランスをとるように
したので、定常時および過渡時の電流バランスを共にと
ることができ、また、スイッチ素子の両端にかかる電圧
が従来の1/2となることから高周波、高電圧のインバ
ータに適用し得る利点が得られ、さらに、従来のものよ
り構成が簡単になる利点も得られる。
As explained above, according to the present invention, a balance transformer is connected to each end of the load to balance the current, so that the current can be balanced both in steady state and in transient state. Since the voltage applied across the element is 1/2 that of the conventional one, there is an advantage that it can be applied to a high frequency, high voltage inverter, and there is also an advantage that the structure is simpler than the conventional one.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は各々従来のインバータの構成例を示す
図、第3図(イ)、仲)は各々第2図に示す回路の動作
を説明するための説明図、第4図はこの発明の第1の実
施例の構成を示すブロック図、第5図は同実施例の動作
を説明するだめの説明図、第6図、第7図は各々この発
明の第2.第3の実施例の構成を示すブロック図である
。 la、lb〜4a、4b・・・・・トランジスタ(スイ
ッチ素子)、5a、5b、5c、5d〜8a。 8 b 、 8 c 、 8 d−・−スイッチ索子、
BLH。 BLHIBL16 +BI116 +BL20.BL2
3・・・・・バランス変成器、C++a + C++b
、 Cl2a 、Cl2b+ Cl6a l Cl5b
+C+6a + O+6b °”” コイル。 出願人神鋼電機株式会社 第3図 第4図 第6図
Figures 1 and 2 are diagrams each showing an example of the configuration of a conventional inverter, Figures 3 (a) and 3) are explanatory diagrams for explaining the operation of the circuit shown in Figure 2, and Figure 4 is an explanatory diagram for explaining the operation of the circuit shown in Figure 2. FIG. 5 is a block diagram showing the configuration of the first embodiment of this invention, FIG. 5 is an explanatory diagram for explaining the operation of the same embodiment, and FIGS. FIG. 3 is a block diagram showing the configuration of a third embodiment. la, lb~4a, 4b...transistor (switch element), 5a, 5b, 5c, 5d~8a. 8b, 8c, 8d-・-switch cord,
B.L.H. BLHIBL16 +BI116 +BL20. BL2
3...Balance transformer, C++a + C++b
, Cl2a , Cl2b+ Cl6a l Cl5b
+C+6a + O+6b °”” Coil. Applicant Shinko Electric Co., Ltd. Figure 3 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 複数のスイッチング素子が並列に駆動されるインバータ
において、負荷の一端を、バランスをとるべき電流の大
きさに逆比例する巻線比を有しかつ互いに磁気結合され
た第1.第2のコイルの各巻始めおよび巻終りに接続し
、前記第1.第2のコイルの各巻終りおよび巻始めを各
々バランスをとるべき電流の線路に接続し、また、前記
負荷の他端を、バランスをとるべき電流の大きさに逆比
例する巻線比を有しかつ互いに磁気結合された第3、第
4のコイルの各巻始めおよび巻終りに接続し、前記第3
.第4のコイルの各巻終りおよび巻始めを各々バランス
をとるべき電流の線路に接続してなるインバータ。
In an inverter in which a plurality of switching elements are driven in parallel, one end of the load is connected to a first switching element having a winding ratio inversely proportional to the magnitude of the current to be balanced and magnetically coupled to each other. The second coil is connected to the beginning and end of each winding of the first coil. The end and beginning of each turn of the second coil are respectively connected to the line of the current to be balanced, and the other end of the load has a turns ratio inversely proportional to the magnitude of the current to be balanced. and connected to the beginning and end of each winding of the third and fourth coils which are magnetically coupled to each other, and
.. An inverter in which the end and beginning of each winding of the fourth coil are connected to current lines to be balanced.
JP58075225A 1983-04-28 1983-04-28 Inverter Pending JPS59201682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58075225A JPS59201682A (en) 1983-04-28 1983-04-28 Inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58075225A JPS59201682A (en) 1983-04-28 1983-04-28 Inverter

Publications (1)

Publication Number Publication Date
JPS59201682A true JPS59201682A (en) 1984-11-15

Family

ID=13570065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58075225A Pending JPS59201682A (en) 1983-04-28 1983-04-28 Inverter

Country Status (1)

Country Link
JP (1) JPS59201682A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186496A (en) * 1986-02-10 1987-08-14 松下電器産業株式会社 Induction heating cooker
JPS62159190U (en) * 1986-03-26 1987-10-09
JPS6352674A (en) * 1986-08-21 1988-03-05 Fuji Electric Co Ltd Parallel connection circuit for inverter
JPS63299779A (en) * 1987-05-28 1988-12-07 Fuji Electric Co Ltd Parallel connection of single-phase inverter
JPH1070889A (en) * 1996-08-27 1998-03-10 Origin Electric Co Ltd Inverter circuit
JP2006050728A (en) * 2004-08-03 2006-02-16 Miyaden Co Ltd High-frequency heating inverter apparatus
JP2009148001A (en) * 2007-12-11 2009-07-02 Fuji Electric Systems Co Ltd Power converter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4977125A (en) * 1972-12-01 1974-07-25
JPS5227522A (en) * 1975-08-26 1977-03-01 Fuji Electric Co Ltd Transistor inverter
JPS5725622A (en) * 1980-07-22 1982-02-10 Fuji Electric Co Ltd Current balancing unit for contact

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4977125A (en) * 1972-12-01 1974-07-25
JPS5227522A (en) * 1975-08-26 1977-03-01 Fuji Electric Co Ltd Transistor inverter
JPS5725622A (en) * 1980-07-22 1982-02-10 Fuji Electric Co Ltd Current balancing unit for contact

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186496A (en) * 1986-02-10 1987-08-14 松下電器産業株式会社 Induction heating cooker
JPH0568839B2 (en) * 1986-02-10 1993-09-29 Matsushita Electric Ind Co Ltd
JPS62159190U (en) * 1986-03-26 1987-10-09
JPS6352674A (en) * 1986-08-21 1988-03-05 Fuji Electric Co Ltd Parallel connection circuit for inverter
JPS63299779A (en) * 1987-05-28 1988-12-07 Fuji Electric Co Ltd Parallel connection of single-phase inverter
JPH1070889A (en) * 1996-08-27 1998-03-10 Origin Electric Co Ltd Inverter circuit
JP2006050728A (en) * 2004-08-03 2006-02-16 Miyaden Co Ltd High-frequency heating inverter apparatus
JP4497409B2 (en) * 2004-08-03 2010-07-07 株式会社ミヤデン Inverter device for high frequency heating
JP2009148001A (en) * 2007-12-11 2009-07-02 Fuji Electric Systems Co Ltd Power converter

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