JPS6157987A - Character pattern accentuation control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a character pattern emphasis control system used in document creation devices, character output devices, etc. that handle character 7-ont information having a dot matrix structure.

[Technical background of the invention and its problems]

Conventionally, when providing a device that handles character fonts with a specified dot matrix structure, such as a document creation device, with a function that can enlarge or reduce the character fonts with a specified dot matrix structure at a certain magnification, In Figure 5, as shown in (a) to (c), the original characters are 4 turn dots)
A so-called simple enlargement method was adopted in which dots were simply increased or deleted from sd.

Such conventional enlarging/reducing means can be realized relatively easily and inexpensively, but the output pattern shape may not be the character form that should be reproduced, for example, if the step-like formation (constriction) in the diagonal line area is noticeable. This had the disadvantage that it deviated from the original character, resulting in an unnatural character expression that was difficult to recognize.

Furthermore, in the conventional enlarging/reducing means as mentioned above,
It is not possible to easily obtain various types of modified fonts such as italics, rotations, outlines, and even thick lines, and the range of modification is greatly restricted.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and allows arbitrary dot patterns to be created inside characters with high quality, for example, as shown in FIG. It is an object of the present invention to provide a character pattern emphasizing control system having a character modification function capable of obtaining white characters (hereinafter referred to as halftone characters).

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention. In the figure, 10 is a CPU that controls the entire system;
is the main memory (MM), 12 is the cpσ bus, 13 is the display control circuit (CRT-C), and 14 is the frame memory (F
M), 15 is a parallel-serial conversion circuit (p-s),
16 is a CRT display section.

21 to 25 are I connected to the CPU bus 12, respectively.
4.9.21 with 10 registers is X during dot interpolation
Directional dot step width (dX)'e register, 22
23 is a register that stores the initial value (initial address; 'sx) in the X direction during dot interpolation, and 23 is a register that stores the dot width (dy) in the Y direction during dot interpolation.
A register 24 stores an initial value (initial address; my) in the Y direction during dot interpolation, and a register 25 stores a comparison value threshold (th) for comparison with an interpolated value, which will be described later.

26 is an adder circuit (ADD) that adds the value (dx) of the register 21 to the value of the latch circuit 28 (described later); 27 is the circuit that selects the value (Ilx) of the register 22 at the time of start;
After that, the data selector (SEL) selects the output of the adder circuit 26, and the data selector 28 stores the new dot address (sx+1-dx) at the time of dot interpolation, which is expressed by the integer part and decimal part output from the data selector 27. It is a latch circuit. 29 is an adder circuit that adds the value (dy) of register 23 to the value of latch circuit 31, which will be described later. 30 selects the value C11y of register 24 at the start, and thereafter selects the output of adder circuit 29. The data selector 31 is a latch circuit that stores a new dot address (sy+j-dy) at the time of dot interpolation, which is expressed by an integer part and a decimal part and is output from the data selector 30.

Reference numeral 32 denotes a control frizzo 70 that controls switching of the data selectors 27 and 30. Reference numeral 33 denotes a kanji 4-turn memory (4-turn memory for kanji characters) in which character no-turn data in a predetermined dot matrix unit (for example, 16 x 16 dots) including kanji characters is stored.
KPM).

Reference numeral 34 denotes a single character buffer consisting of a high-speed RAM that stores the dot pattern for one character read from the kanji pattern memory 33; ') is stored in a state filled with dot patterns. 35 is 1 character buffer 34
This is a bit selection circuit that selectively outputs dot information of four points in one lattice surrounding a new dot according to the value of each integer part of the two-way circuit 28 and 31 among character turn data stored in the character number turn data. A latch circuit 36 latches the 4-bit information output from the bit selection circuit 35.

37 to 39 constitute constituent elements of a dot pattern recognition unit CDSP) which recognizes the pattern of dot information output from the bit selection circuit 35 and selectively switches and controls the interpolated value of a new dot surrounded by four dots. 37 recognizes the dot pattern state of four points from the bit contents of the latch circuit 36, and when the dot pattern state is in a specific dot pattern state described later, it sequentially selects the dot information of two specific grids around the dot pattern state. 38 is a latch circuit that latches each of the 4 bits of information read out under the control of the discrimination control circuit 37; 39;
is a dot discrimination circuit which outputs a 1-bit interpolation value switching selection signal according to the dot pattern state of the dot information for two grids read out under the control of the discrimination control circuit 37 and the dot information of the latch circuit 36.

40 is the fractional part value stored in the latch circuit 28 (5-bit X-direction offset value), the fractional part value stored in the latch circuit 31 (5-bit Y-direction offset value), and the fractional part value stored in the latch circuit 36. The interpolation value of a new dot in the area surrounded by the dot information of the four points is determined by inputting the dot information of the four points and the 1-bit interpolation value switching selection signal output from the dot discrimination circuit 39 as input information. It is an interpolation table ROM that outputs (QX7), and here it is 256K (3
Using a 2K x 8) bit mask ROM, the above 15
An 8-bit (0 to 255 level) interpolated value is output according to the pit read address. 41 is an interpolation table ROM
It is a comparator that compares the interpolated value that is output more than 40 times with the threshold value stored in the register 25, and indicates an on dot (bright spot) when the interpolated value exceeds the comparison value, that is, the threshold value.
] Outputs an N level signal.

42 sequentially stores the dot information output from the comparator 41 in units of a predetermined bit length (here, 1 byte).
This is the I10 register that outputs on the CPU/4 bus 12 every time.

2(&) to (f) respectively show dot information (dot/4 turns) of four points in one grid surrounding a new dot generated by the interpolation process and interpolation values set in the interpolation table ROM 40. It is a diagram showing the relationship between level classification and table type, and here, the interpolated value is set to 0 to 255 levels of brightness (
It is expressed in terms of brightness and darkness levels), and some of the divided areas are shown as contours.

Figure 3 is for explaining an example of table type selection switching when only one dot out of the four dot patterns in one grid is on ("1'") or off (O"). /4 turn recognition unit (DSP), for example, among the surrounding four dots (DOIDl, D2.Da),
Only one point is off, or “0” (D (7) shown in white in the figure)
), the specific dots (Da,
DalD b =
If it is "1", select the corner type table (T1) as shown in Fig. 2(d), and if at least either Da or Db is "'O", select the table in Fig. 2 (f
Select an oblique type table (TO) as shown in ). In this way, the interpolated value of a new dot located within the four dot area is further determined by the state of the surrounding dots when the four dots form a specific pattern as described above.

Here, the operation of an actual journey example will be explained with reference to FIGS. 1 to 4. First, the CPU 10 generates a dot pattern (hereinafter referred to as shading) to be written inside a white character.
is stored in the shading pattern storage area of the main memory 11. Then, at the fourth dot, the CPU 10 first initializes the registers 21, 22, 23, and 24.25. In other words, the dot step width (
dx), the initial value in the X direction (initial address; SX) in the register 22, the dot width in the Y direction (dy) in the register 23, the initial value in the Y direction (initial address; ay) in the register 24, and the interpolation in the register 25. A comparison value, that is, a threshold value (th) for comparison with the value is set respectively.

Here, the dot step width of registers 21 and 23 is given as an inverse value of the enlargement/contraction magnification. Further, the register 22 is set with the initial value sx, which is I x = (dx-i)/2, and the register 24 is set with Iy = (
Iy consisting of dy 1)/2 is set as the initial value sy, and when dx or dy is less than 1 (that is, when expanding), Ix or I7 becomes negative and the original character pattern is stored in the 1-character buffer 34. Indicates the address outside the area, and when dx or ciy is 1 or more (i.e. when reducing), Ix or y
becomes positive and indicates an address within the original character pattern storage area of the one-character buffer 34.

Further, the register 25 contains an arbitrary value (0 to 255) for determining which level of new dots should be compared with the interpolated values output from the interpolation table ROM 4θ to be considered meaningful dots. A level comparison value or threshold is set. Here, in order to obtain two types of character patterns with different heel widths to obtain halftone letters, first and second comparison values (tha, thb) with different values are prepared, and first, the first and second comparison values (tha, thb) are prepared. 1 comparison value (tha', here tha(th
b) is set in the register 25.

Furthermore, the CPU J o extracts one character's worth of dot pattern data to be subjected to redot interpolation, that is, to be subjected to whiteout processing, from the kanji pattern memory 33, and stores it in the one character buffer 3.
4. As mentioned above, in this original one-character buffer 34, one character's worth of dot pattern data to be subjected to dot interpolation is surrounded by meaningless ``'o#Q dots.'' It is stored in the same state.

Each of these registers? After setting the data to J, 22, 23, 24° 25 and taking out the interpolation target character/arm turn to the 1-character buffer 34, register 22.2
Initial address data stored in 4 (sx a
T17) is selected by the r-ta selector 27.30 under the control of the control free lag flop 32 and latched into the corresponding latch circuit 28.31. The value of the integer part of the dot at 1 nos data stored in the latch circuits 28 and 31 is given to the bit selection circuit 35, and the value of the decimal part is given to the interpolation table ROM 40. The bit a selection circuit 35 selects the dot information of 4 points of the υ1 lattice from the 4-point buffer 34 for one character in the first order of the integer part, and supplies it to the interpolation table ROM 40. At this time, at the time of expansion (dx, dy(1)), the bit selection circuit 35 is given a negative value indicating an address outside the original character pattern storage area of the one character buffer 34. Dot selection starts with the dot information of 4 points in 1 grid, including dots outside the storage area.Also, when reducing (dx, dy
In >1), the bit selection circuit 35 is given a positive value indicating the address in the original character pattern storage area of the 1 character buffer 34. Start dot selection based on dot information.

The interpolation table ROM 40 is connected to the latch circuit 211.
Each offset value in the X direction and Y direction from 31 (total 10
bit), dot information on the surrounding four points from the bit selection circuit 35, and a 1-bit interpolation value switching selection signal from the dot/4-turn recognition unit (DSP) as input information, and an 8-bit interpolation value according to the contents is generated. Output. At this time, the dots/four turns at four points in one grid outputted from the bit selection circuit 35 are recognized by the dot pattern recognition section (DSP), and as shown in FIG. further recognizes the on/off state of specific dots in the surrounding grid and outputs a 1-bit interpolation value switching selection signal corresponding to the dot state. That is, for example, as shown in FIG. 3, there are four surrounding dots (DO, DI#I)'.

DJ), when only one point is off, that is, 'O# (DO shown in white in the figure), the on/off state of specific dots (Da, Db) in the surrounding grid is further recognized, D
If a, Db = "1", select a corner type table (T1) as shown in Fig. 2(d), and D a
If at least one of t D b is O”,
A diagonal type table CT as shown in Fig. 2(f)
An interpolation value switching selection signal is output to select O). or,
Among the surrounding four dots (DOIDl, D2.D3),
When only one point is on, that is, 1'' (IM indicated by a black dot in the figure), specific dots (Da, Db
), and if Da, Db = "'0", select a corner type table (T1) as shown in Figure 2 (a), and at least Da, Db. If either one is 1", an interpolation value switching selection signal is output to select a diagonal type table (TO) as shown in FIG. When the four dots form a specific pattern as described above, the interpolation value of a new dot located at 4 is further determined by the state of the surrounding dots. Bit (O~255
The h opening value of level) is input to the comparator 41,
The comparison value stored in the register 25, that is, the dark value (tha)
If the interpolated value exceeds the dark value, it outputs a ``1'' level signal indicating that it is a meaningful dot, and if the interpolated value does not exceed the threshold value, it outputs a meaningless dot. Outputs a '0'' level signal indicating that the output is active.

On the other hand, after the interpolation value is selected and output from the interpolation table ROM 40, the contents of the latch circuit 28 and the contents of the register 21 are added by the adder circuit 26, and the contents of the latch circuit 31 and the contents of the register 23 are added together. are added by the addition circuit 29, and the data of the addition result is sent to the control 7 and the output 7.
Under the control of the respective data selectors 27 and 30, the latch circuits 28 and 31 are selected.
Now, I get hit. In this way, interpolation table ROM 4
Every time an interpolated value is output from 0, the address value of the latch circuit 28 is updated according to the value of the register 21 (step size: dx), and the address value of the latch circuit 31 is updated according to the value of the register 23 (step size: dy ) will be updated accordingly.

In this way, the interpolated values output from the interpolation table Rα:'140 are sequentially transferred to the first . The dot information is compared with the comparison value, that is, the darkness value (tha), and new dot information is generated.

The interpolated new dot information outputted from the comparator 41 is sequentially stored in the register 42 and outputted to the CPU node 12 in 1-byte units. This CPU
The new dot information after the interpolation process output on bus 12 is C
Under the control of the PU 10, the characters are sequentially stored in a predetermined first character pattern storage area in the main memory 11.

When the first character turn obtained by the comparator 41 is stored in the predetermined first character turn storage area in the main memory 11, the first character turn is stored in the register 25. , a second comparison value, that is, a threshold value t, which is lower than the comparison value of @1, that is, the speed value tha.
hb is set to zero), and the above-described processing operation is repeated again using this dark value thb. The second character pattern obtained by the comparator 41 using thb as a comparison value is stored in a predetermined second character pattern storage area in the main memory 11.

When the first and second character patterns are stored in the first and second character pattern storage areas of the main memory 11, the CPU 1o processes the first and second character patterns by superimposing them. , obtain an outline character pattern. That is, the four turns of the first and second characters are subjected to an exclusive OR operation for each corresponding dot, and the processed dot and turn information is written into the first character pattern storage area. As a result, a white character pattern with only dots having interpolated values of tha to thb as on-dots (pa 1'') is stored in the main memory 1.
1 is stored in the first character no-no-turn storage area.

Next, the second character pattern and the half-shaded turn stored in the half-shaded nine-turn storage area of the main memory 11 are ANDed for each corresponding dot, and the processed dot pattern information is used as described above. Write to the second character/9th turn storage area. Next, the white character arm turn stored in the first character/gut turn storage area and the dot pattern stored in the second character 9 turn storage area are logically ORed for each corresponding dot. The calculated dot pattern information is written into the first character pattern storage area.

This allows only dots with interpolated values exceeding thb to be shaded I? For example, a cross-hatched character pattern as shown in FIG. 4 is stored in the first character 4 turn storage area of the main memory 11.

The first character 1 of this main memory 11? The four turns of cross-hatched characters stored in the turn storage area are transferred character by character via the CPU bus 12 to the display control circuit 13 under the control of the CPU 10, stored in the frame memory 14, and then transferred to the CR1. It is displayed on the display section 15.

1st. Second letter arm turn and shading A? In addition to the above-mentioned method, there is a method for creating cross-hatched characters from patterns.
There is a means for performing an exclusive OR operation between a dot pattern obtained by ANDing the character pattern and the shading/4' turn, and the first character turn.

As a result of the above-mentioned processing operations, the cross-hatched character cutter after dot interpolation is very easy to recognize, with no conspicuous step-like constriction in the diagonal lined areas, and no missing corners. υ, it becomes possible to express a high degree of mesh character.

In addition, the enlargement/reduction ratio can be set at very fine values, making it possible to easily create white characters of any size. Optionally specify that value as CPU f
By changing sequentially or selectively under the control of O, you can not only enlarge or reduce characters, but also express characters such as long letters, half letters, italics of arbitrary angles, bottom-aligned italics, rotation, etc. is easily possible, and advanced character modification is possible. For example, if you set the value of register 21.23 to 2:1, you will get a long character whose vertical width is twice the horizontal width.
．． If the value of 23 is set to 1:1.2, a half-length character whose width is 1.2 times the length of the vertical line will be 11. Also, by sequentially changing the value of the register 22 to 1 sura r s'iJJ, the desired f1 type character can be obtained, and the value of the register 2
By changing the value of 2°24 by j; on a daily basis, characters with arbitrary rotation angles can be obtained.

〔Effect of the invention〕

As described in detail above, according to the present invention, character patterns having a character pattern with a decorative function can obtain high-quality cross-hatched characters at arbitrary enlargement/reduction ratios from character patterns having a basic dot matrix structure. An emphasis control method can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of essential parts in an embodiment of the present invention, and FIGS. 2 (-) to (f) and 3 are diagrams for explaining the operation of the above embodiment, respectively. Figures 2 (a) to (f) respectively show the dot information (dot pattern) of four points in one grid surrounding a new dot generated by interpolation processing, and the level classification and table of interpolation values set in the interpolation table ROM. Figure 3 is a diagram showing the gatekeeper between types, and Figure 1 and Figure 4 are for explaining the table type selection switching operation.
The figure shows character 1 in the above example? FIGS. 5(a) to 5(c) are diagrams illustrating examples of dot generation, and diagrams for explaining conventional dot interpolation processing means, respectively; FIGS. 10...CPU, 11...Main memory, 12...
・CPU bus 13... Display control circuit, 14... Frame memory, 15... CRT display section, 21-25.
...Register, 26... Addition circuit, 27... Data selector, 28... Latch circuit, 29... Addition circuit, 30... Data selector, 3... Latch circuit,
32... Control frig 70 knobs, 33... Kanji number turn memory, 34... 1 character buffer, 35...
Bit selection circuit, 36... Latch circuit, 37... Discrimination control circuit, 38... Latch circuit, 39... Dot discrimination circuit, 40... Interpolation f-7" ROM, 41.
...Comparator, 42...Register, DSP...
Dot pattern recognition section. Figure 2 (a) (b) (C) (
d) Figure 4 Figure 5

Claims (1)

[Claims] means for enlarging a character pattern having a basic dot matrix configuration by dot interpolation; means for obtaining a first character pattern with a thick line width and a second character pattern with a thin line width from the expanded character pattern; a means for storing an arbitrary dot pattern to be written in the blank character; and a means for selecting two dot patterns from three dot patterns: the first and second character patterns and a dot pattern to be written inside the white character; means for performing various logical operations such as logical sum, logical product, and exclusive logical sum for each dot when two dot patterns are placed on the same dot position; A character pattern emphasis control method characterized by obtaining dot pattern information of white characters having an arbitrary dot pattern inside.