JPS6084583A - Dot interpolation control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dot interpolation control method used in document creation devices, character output devices, etc. that handle character 7-ont information in a dot matrix structure.

[Technical Background of the Invention and Problems Therewith] In a device that handles a character font with a specified dot matrix structure, such as a document creation device, it is possible to enlarge or reduce the character font with a specified dot matrix structure at a specified magnification. Conventionally, when providing a function that allows for
A so-called simple enlargement method has been adopted in which dots are simply increased or deleted from d....

Such conventional enlarging/reducing means can be realized relatively easily and inexpensively, but the output pattern shape may not be the original character form that should be expressed, for example, the step-like formation (constriction) in the diagonal line area is noticeable. This had the disadvantage that it deviated from the original character, resulting in an unnatural character expression that was difficult to recognize. Furthermore, with the conventional enlarging/reducing means as described above, it is not possible to easily obtain various deformed fonts such as italics, rotated characters, outlines, and even thick lines, and the range of deformation is greatly restricted. There was a drawback.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and is a device that handles character fonts with a prescribed dot matrix structure, and is capable of performing dot interpolation of character patterns while maintaining high character quality and allowing arbitrary enlargement.・The purpose is to provide an extremely practical dot interpolation control method that can be easily performed at a reduced magnification and also allows for various character decorations, including compensation for diagonal lines using half-tone luminance. shall be.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit block diagram showing one embodiment of the present invention. In the figure, 10 is a CPU that controls the entire system;
12 is a main memory (MM), 12 is a CPU bus, 13 is a display control circuit (CRT-C), and 14A.

14B is a pair of frame memories (FM), 15 is a pair of parallel-serial conversion circuits (P-8), and 16 is CR7.
This is the display section.

21 to 24, 25A, and 25B are CPUs, respectively.
The I10 register is connected to the bus 12, 21 is a register that stores the dot width (dx) in the X direction during dot interpolation, and 22 is the initial value (dx) in the X direction during dot interpolation.
23 is a register that stores the dot width (dy) in the Y direction during dot interpolation. 24 is a register that stores the initial value (initial address: SV) in the Y direction during dot interpolation. 25
A and 25B are respectively different comparison values for comparison with interpolated values to be described later, that is, threshold values (thl),
(th2).

26 is an adder circuit (ADD) that adds the value (dx) of the register 21 to the value of the latch circuit 28, which will be described later; 27 is the adder circuit that selects the value (SX) of the register 22 at the time of start;
After that, a data selector (SEL) selects the output of the adder circuit 26, and a latch 28 stores the new dot address (sx+l ・dx) during dot interpolation, which is expressed by the integer part and decimal part output from the data selector 27. It is a circuit. 29 is an adder circuit that adds the value (dy) of register 23 to the value of latch circuit 31, which will be described later. 30 selects the value of register 24 (<8V) at the start, and thereafter selects the output of adder circuit 29. data selector, 3
1 is the new dot address (s
This is a latch circuit that stores y+J-dy). Reference numeral 32 denotes a control flip 70 for controlling switching of the data selectors 27 and 30.

33 is a predetermined dot matrix unit (for example, 1
This is a Kanji pattern memory (KPM) in which character pattern data of 6×16 dots is stored. Reference numeral 34 denotes a single character buffer composed of a high-speed RAM that stores the dot pattern for one character read from the kanji pattern memory 33. Here, the six-dot pattern for one character is surrounded by off-dots ("0"). It is stored filled with bit patterns. 35 is a bit selection circuit that selectively outputs dot information of four points in one lattice surrounding a new dot according to the values of each integer part of the latch circuit 28 and 31 among the character pattern data stored in the one character buffer 34. It is. A latch circuit 36 latches the 4-bit information output from the bit selection circuit 35.

37 to 39 indicate patterns of dot information output from the bit selection circuit 35. I! It is a constituent element of the dot pattern recognition unit (DSP) that recognizes and selectively switches and controls the interpolated value of a new dot surrounded by four dots.
37 recognizes the dot pattern state of four points from the pit contents of the latch circuit 36, and when the dot pattern state is in a specific dot pattern state described later, bit selection is performed to sequentially select dot information for two specific grids around the dot pattern state. A discrimination control circuit that controls the circuit 35; 38 a latch circuit that latches the information of 4 pits read out under the control of the discrimination control circuit 37; 39 a latch circuit that latches the information of 2 grids read out under the control of the discrimination control circuit 37; This is a dot discrimination circuit that outputs a 1-bit interpolation value switching selection signal according to the dot pattern state of the information and the dot information of the latch circuit 36. 40 is a latch circuit 28
The decimal part value stored in the latch circuit 31 (5-bit X-direction offset value), the decimal part value stored in the latch circuit 31 (5-bit Y-direction offset value), and the 4 points stored in the latch circuit 36 The interpolation value (Qxy) of a new dot in the area surrounded by the dot information of the four points is determined using the dot information of the dot information and the 1-bit interpolation value switching selection signal output from the dot discrimination circuit 39 as input information. Interpolation table RO to output
Here, a 256K (32Kx8) pit mask ROM is used to output an 8-bit (0 to 255 level) interpolated value in accordance with the 15-bit read address described above. 41A and 41B are interpolation table ROMs, respectively.
This is a comparator that compares the interpolated value output from 40 with threshold values stored in registers 25A and 25B associated with each other in advance, and each interpolated value is a comparison value, that is, a threshold value (t
hl, th2), it outputs a ``1'' level signal indicating an on-dot (bright spot). 42A and 42B sequentially store the dot information output from the corresponding comparators 41A and 41B, and store the dot information in a predetermined bit length. These are a pair of I10 registers that output onto the CPU bus 12 in units (here, 1 byte).

FIGS. 3(a) to 3(f) respectively show dot information (dot pattern) of four points in one grid surrounding a new dot generated by interpolation processing, level divisions and table types of interpolation values set in the interpolation table ROM 40. Here, interpolated values are expressed in luminance levels (brightness levels) of 0 to 255, and some of the divided areas are shown with contour lines.

FIG. 4 is for explaining an example of table type selection switching when only one dot out of the four dot patterns in one grid is on (1) or off (0).
The dot pattern recognition unit (DSP) detects, for example, four surrounding dots (DO).

DI, D2. Da ), only one point is off, that is, “0
” (DO shown in white in the figure), further lil the on/off state of the specific dots (Da, Db > in the surrounding lattice), and set [)a, [)b="1" tear]. tLlf
, a corner type table as shown in Figure 3(d) (
T1) is selected, and if at least one of Da and Db is "0", a diagonal type table (TO) as shown in FIG. 3(f) is selected.

In this way, the interpolated value of a new dot located within the four dot area is further determined by the state of the surrounding dots when the four dots form a specific pattern as described above.

FIG. 5 is a diagram showing an example of dot pattern compensation by half-filia1 display in one embodiment, and in the figure, hd is a half-tone dot.

The operation of one embodiment will now be described with reference to FIGS. 2 to 5. During dot interpolation, the CPU 10 first initializes the registers 21, 22, 23, 24, 25A, and 25B. That is, the register 21 has the dot width (dx) in the X direction, the register 22 has the initial value (initial address; SX) in the X direction, the register 23 has the dot width (dy) in the Y direction, and the register 24 has the Y direction 10- Initial value of direction (initial address: sy), register 2
Comparison values, that is, threshold values (thl, th2) for comparison with interpolated values are set in 5A and 25B, respectively.

Here, the dot step width of registers 21 and 23 is given as an inverse value of the enlargement/contraction magnification. Further, in the register 22, IX, which is lx = (dx -1) /2, is set as the initial value Sx, and in the register 24, Ty - (d
y-1') /2 is set as the initial value sy, and when dx or dV is less than 1 (i.e., during expansion), IX or Iy becomes negative and the original character in the 1-character buffer 34 is It indicates an address outside the pattern storage area, and when dx or dv is 1 or more (that is, during reduction), lx or Iy becomes positive and indicates an address within the original character pattern storage area of the one-character buffer 34. Further, the registers 25A and 25B contain arbitrary values (0 to 25B) for comparing the interpolation values outputted from the interpolation table ROM 40 and determining which level of the new dot is considered to be a meaningful dot.
255) Level comparison values or thresholds (thl, th2) are set. Here, thl > th2, and the threshold value (t
hi), and a threshold value (th2) for obtaining half-gradation dot information is set in the register 25B.

Further, the cpuio reads dot pattern data for one character to be subjected to dot interpolation from the kanji pattern memory 33 and writes it into the one character buffer 34. At this time, the one-character buffer 34 stores dot pattern data for one character to be subjected to dot interpolation surrounded by meaningless 0'° dots, as described above.

Each of these registers 21.22.23.24.25A, 2
After completing the data set to 5B and the extraction of the interpolation target character pattern to the 1-character buffer 34, register 2
2. Initial address data stored in 24 (sx
, sy) are selected by the data selector 27.30 under the control of the control flip-flop 32 and latched into the corresponding latch circuits 28.31. The value of the integer part of the dot address data stored in the latch circuits 28 and 31 is given to the bit selection circuit 35, and the value of the decimal part is given to the interpolation table ROM 40. The bit selection circuit 35 selects dot information of four points in one grid from the one character buffer 34 based on the value of the integer part, and supplies it to the interpolation table ROM 40. At this time, when enlarging (dx,
dV<1), the bit selection circuit 35
Since a negative value indicating an address outside the original character pattern storage area of the character buffer 34 is given, dot selection is started from dot information of four points in one lattice including dots outside the original character pattern storage area. Also, when reducing (dx, dy> 1
), since the bit selection circuit 35 is given a positive value indicating the address in the original character pattern storage area of the 1 character buffer 34, the dot information of 4 points in 1 lattice in the original character pattern storage area is Start dot selection.

The interpolation table ROM 40 is connected to the latch circuit 28°3.
1 in the X and Y directions (10 bits in total), dot information on the surrounding 4 points from the bit selection circuit 35, and a 1-pit interpolation value switching selection signal from the dot pattern recognition unit (DSP). As input information 13-, an 8-bit interpolated value according to the contents is output.

At this time, the dot pattern of four points per grid outputted from the bit selection circuit 35 is recognized by the dot pattern recognition section (DSP), and if it is a specific dot pattern as shown in FIG. The on/off state of a specific dot on the grid is recognized and a 1-bit interpolation value switching selection signal corresponding to the dot state is output. That is, for example, as shown in FIG. 4, the surrounding four dots (DO, DI, D2
When only one point among ゜Da) is off or "0" (DO shown in white in the figure), the on/off state of specific dots (Da, Db) in the surrounding grid is further recognized. ,
If Da, Db = "1", select a corner type table (T1) as shown in Fig. 3(d),
Also, if at least one of Qa and Qb is 0'', a diagonal type table (T
An interpolation value switching selection signal is output to select O). or,
Of the four surrounding dots (DO, DI, 02.Da), only one is on, that is, "1" (DO indicated by a black dot in the figure)
14-, the specific dot (Da) of the surrounding grid is further added.

Recognize the on/off state of Db), Qa, [)b=゛0
”, select a corner type table (T1) as shown in FIG. 3(a), and select Da.

If at least one of Db is "1°", an interpolation value switching selection signal is output to select a diagonal type table (TO) as shown in FIG. 3(e). In this way,
The interpolated value of a new dot located within the four-point dot area is further determined by the state of the surrounding dots when the four dots form a specific bump as described above. The interpolated values of 8 pits (0 to 255 levels) outputted from the interpolation table ROM 40 are input to comparators 41A and 41B, and are compared with the threshold value (t) stored in the corresponding registers 25A and 25B, respectively.
hl, th2), and if the interpolated value exceeds the threshold, a 1" level signal is output indicating that the dot is meaningful, and if the interpolated value does not exceed the threshold, it is output as a meaningless dot. A “0” level signal indicating that
Half-gradation dot information is obtained from 1B.

On the other hand, after the interpolation value is selected and output from the interpolation table ROM 40, the contents of the latch circuit 28 and the contents of the register 21 are added by the adder circuit 26, and the contents of the latch circuit 31 and the contents of the register 23 are added. The data are added by the adder circuit 29, and the resulting data is selected by the corresponding data selectors 27, 30 under the control of the control flip-flop 32, and then sent to the latch circuits 28, 28, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 22, 30, and 30sss. '
31. In this way, the interpolation table ROM
Every time an interpolated value is output from 40, the address value of the latch circuit 28 is updated according to the value of the register 21 (step size: d×), and the address value of the latch circuit 31 is updated according to the value of the register 23 (step size: dy).

In this way, the interpolated values output from the interpolation table ROM 40 are sequentially compared with the threshold values ([old, th2)] of the registers 25A and 25B by the comparators 41A and 41B, and the new dot information is divided into full gradation and half gradation. Generated for each key.

The new dot information outputted from the comparators 41A and 44B after interpolation processing is stored in the corresponding registers 42A and 42B, respectively, and sent to the CP in 1-byte units.
It is output onto the U bus 12. The new dot information after the interpolation process outputted onto the CPU bus 12 is sequentially stored in a predetermined character pattern storage area in the main memory 11 under the control of the CPU 10 for full gradation and half gradation. After being stored, they are stored separately in the frame memories 14A and 14B under the control of the display 11Ji11 circuit 13, and are respectively parallel-recorded.
The signals are sent via the serial conversion circuit 15 to the video circuit of the CRT display section 16, where they are combined and output for display. As a result, the register 2 is displayed on the display screen of the CRT display section 16.
Dots with interpolated values greater than or equal to the comparison value (thl) stored in register 25A are displayed in all gradations, and the comparison value (th2) stored in register 25B is calculated from the comparison value (thl) stored in register 25A. Only dots with interpolated values within the range are displayed in half-tone. In this way, characters with half-gradation areas are displayed at the specified enlargement/reduction ratio, and specifically, as shown in FIG. In this case, it is possible to express characters with natural sloped lines by expressing the constricted portions with half-gradation dots (HD).

Furthermore, by performing an exclusive OR of the character pattern dots obtained from the comparator 41A and the character pattern dots obtained from the comparator 41B, a white character pattern can be easily obtained.

It is also possible to obtain a character pattern with dot interpolation using only the comparator 41A. In this case, for example, the reciprocal of the enlargement/reduction magnification is set to 81 in the register 25A, and the minimum line width of the character pattern to be output is A, and the interpolation When the maximum value is K, by setting the value T given by T = (1-(SA/2))K, characters with an optimal line width that is always balanced for enlarged/reduced characters can be created. A pattern is obtained.

Due to the dot interpolation process described above, the character pattern after dot interpolation is very easy to recognize, with no conspicuous step-like constrictions in diagonal lines and no missing corners. This makes it possible to express characters extremely close to the original character form. Furthermore, the enlargement/reduction ratio and multiple gradation levels can be set with very fine values, making it easy to obtain characters of any size.
One or more of 25A and 25B are optionally designated and their values are sequentially set under the control of the CPU 10.
Or by selectively changing it, you can not only enlarge or reduce the characters, but also express characters such as thick lines, thin lines, long letters of any proportion, flat letters, italics of arbitrary angles, bottom-aligned italics, rotation, etc. is easily possible, allowing advanced character decoration. For example, if the value of register 21.23 is set to 2:1, a long character whose height is twice the width will be obtained.
If the value of 23 is set to 1:1.2, a plain text whose width is 1.2 times the height can be obtained. Also, register 2
By sequentially changing the value of 2 for each slice, a desired italic character can be obtained, and by sequentially changing the values of registers 22 and 24, a character with an arbitrary rotation angle can be obtained.

In the above embodiment, two sets of circuits are provided to obtain new dot information by comparison with interpolated values, and two types of dot information are simultaneously obtained from the two comparators 41A and 41B. However, the present invention is not limited to this, and for example, the comparison means may be provided as only one set, and a plurality of types of character patterns may be sequentially obtained for the same character font by rewriting the comparison values.

[Effects of the Invention] As described in detail above, according to the dot interpolation control method of the present invention, in a device that handles character fonts with a prescribed dot matrix structure, dots of arbitrary character fonts stored in the dot pattern memory can be Interpolation and modification can be easily performed at arbitrary enlargement/reduction magnification while maintaining high character quality, and the cost performance of the device can be greatly improved.

[Brief explanation of drawings]

1A to 1C are diagrams for explaining conventional dot interpolation processing means, FIG. 2 is a circuit block diagram showing the configuration of main parts in an embodiment of the present invention, and FIG. Figure (a
) to (f), FIG. 4, and FIG. 5 are for explaining the operation of the above embodiment, respectively.
f) is a diagram showing the relationship between the dot information (dot pattern) of four points in one grid surrounding each new dot generated by interpolation processing, the level classification of the interpolation value set in the interpolation table ROM 40, and the table type. FIG. 4 is a diagram for explaining the table type selection switching operation, and FIG. 5 is a diagram showing an example of compensation for a dot pattern using half-mm display. 10... CPLI, 11... Main memory, 12.
...CPLJ bus, 13...Display control circuit, 14...
・Frame memory, 15...CRT display section, 21-2
4...Register, 25A, 25B...Register,
26...Addition circuit, 27...Data selector, 28
... Latch circuit, 29 ... Addition circuit, 30 ... Data selector, 31 ... Latch circuit, 32 ... Control flip 70 knob, 33 ... Kanji pattern memory, 3
4...1 character buffer, 35...pit selection circuit,
36...Latch circuit, 37...Discrimination control circuit, 38
...Latch circuit, 39...Dot discrimination 21-circuit, 40...Interpolation table ROM, 41A, 41B
...Comparator, 42A 142B...Register, DSP...Dot pattern recognition section. Applicant's agent Patent attorney Takehiko Suzue 22- Figure 5...

Claims (7)

[Claims] (1) A dot pattern memory for storing character pattern data having a predetermined dot matrix structure; a means for obtaining dot information on four points adjacent to each other at arbitrary positions from the dot pattern memory; means for obtaining an interpolated value consisting of a plurality of bits within an area surrounded by four points; a storage means for storing a comparison value for comparison with the interpolated value; and a comparison between the interpolated value and the comparison value. 1. A dot interpolation control system comprising: interpolation value comparison means for obtaining a determination output indicating dot on or dot off. (2) The dot interpolation control method according to claim 1, wherein the output value from the interpolation value comparison means is controlled by rewriting the comparison value stored in the storage means. (3) A plurality of sets of storage means for storing the comparison value and an interpolation value comparison means for comparing the interpolation value and the comparison value and obtaining a judgment output indicating dot on or dot off are provided, and the interpolation value comparison of the plurality of sets is provided. A dot interpolation control system according to claim 1, characterized in that a plurality of types of dot information are obtained using each determination output obtained from the means. (4) The dot interpolation control method according to claim 2, wherein the comparison value in the storage means is changed in accordance with the enlargement/reduction magnification. (5) When the reciprocal of the enlargement/reduction magnification is S, the minimum line width of the output character pattern is A, and the maximum interpolation value is K, the storage means for storing the comparison value has T= (1-( S.A.
/2)) The dot interpolation control method according to claim 4, wherein a value T given by K is set. (6) The dot interpolation control method according to claim 3, wherein a plurality of types of dot information having different gradations are obtained from each determination output obtained from the plurality of sets of interpolation value comparison means. (7) The third aspect of the present invention is characterized in that dot pattern information of a white character is obtained by exclusive OR operation of each determination output obtained from the plurality of sets of interpolation value comparison means.
The dot interpolation control method described in .