JPS6156595B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit for a semiconductor memory device used as a high-speed, high-sensitivity sense amplifier circuit.

Semiconductor memory devices, especially transistor circuits using insulated gate transistors (hereinafter abbreviated as transistors) called MOS memory,
It is in great demand as a general-purpose memory because of its low power consumption operation and ease of realizing large-scale integrated circuits.
In order to detect stored information, this type of memory has a sense amplifier circuit that amplifies the potential difference between a pair of digit lines using a gated flip-flop circuit. The operating characteristics of this sense amplifier circuit have a large impact on the large-scale and high-density integration of memories, but with conventional circuits, it has been impossible to achieve high-speed operation and high sensitivity characteristics with low power consumption. .

An object of the present invention is to provide a transistor circuit for a semiconductor memory device having a low power consumption, high speed, and high sensitivity sense amplifier circuit.

A transistor circuit according to the present invention includes: a dynamic type gated flip-flop coupled to a pair of sense contacts; a pair of transfer transistors for respectively transmitting signals between the pair of sense contacts and a pair of digit lines; a pair of transistors having one of their respective output regions coupled to the digit line of the sense amplifier and a pair of transistors having control electrodes coupled to each other's sense contact;
It includes a flip-flop and a gated flip-flop outside the sense amplifier separated by a transfer transistor.

According to the present invention, a first transistor Q A1 has one of its output regions coupled to the first sense contact _A1 and a control electrode coupled to the second sense contact A2; and a second transistor Q A2 having a control electrode coupled to the first sense contact A1, and a second transistor Q _A2 having an output region coupled to the first sense contact A1 and the first digit line B1 and having a control electrode coupled to the cutoff pulse φ _T a fourth transistor Q _T2 whose output regions are respectively coupled to the second sense contact _A2 and the second digit line B2 and whose control electrode receives the cutoff pulse φ _T ; and the second transistor Q _A1
and Q _A2 have a transistor circuit for controlling the common potential of the other contact S1 of the output region, and one of the output regions is coupled to the first digit line B1, and a control electrode is connected to the second sense contact A2. a fifth transistor Q _D1 connected to the second digit line B2; a sixth transistor Q _D2 having one of its output regions coupled to the second digit line B2 and a control electrode connected to the first sense contact A1; and a transistor circuit for controlling the potential of the other contact S2 of the common output region of the sixth transistor. Further, in such a transistor circuit, a transistor circuit for a semiconductor memory device is obtained, in which the gain constant of the fifth and sixth transistors is larger than that of the first and second transistors, and further, in these transistor circuits, A transistor circuit for a semiconductor memory device is also obtained in which capacitive elements C _B1 and C _B2 are added, one terminal of each of which is coupled to the sense contacts A1 and A2, and the other terminals of which are commonly coupled to the pulse signal φ _S1 .

The transistor circuit of the present invention performs a high-speed, high-sensitivity amplification operation using the gated flip-flop circuit inside the sense amplifier, which has a light parasitic capacitance, and uses this signal output to operate the gated flip-flop circuit outside the sense amplifier, which has a heavy parasitic capacitance. Drive the circuit.
The gain constant of the external transistor pair is larger than that of the internal transistor pair, which allows the potential difference between the digit line pairs to be expanded rapidly.

Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.

FIG. 1 shows a transistor circuit according to an embodiment of the present invention. This embodiment is a sense circuit of a so-called one-transistor type MOS memory, and a switching transistor Q _W1 is connected to one digit line B1.
The information storage capacitive element C _M is coupled to the other digit line B2 via a _transistor Q _W2 . All transistors in this embodiment are MOS transistors, and the current between output regions called drain and source is controlled by the potential of a control electrode, which is a gate electrode. The sense amplifier includes a first transistor Q A1 having one output region coupled to a first sense contact A1 and a control electrode coupled to a second sense contact A2, and a first transistor Q _A1 having one output region coupled to a second sense contact A2. A second transistor Q A2 is coupled and has a control electrode coupled to the first sense contact A1, and a second transistor Q _A2 has an output region coupled to the first sense contact A1 and the first digit line B1, respectively, and has a control electrode coupled to the cutoff pulse φ _T . a third transistor Q _T1 receiving and a second sense contact A2
and a fourth transistor Q _T2 whose output regions are coupled to the second digit line B2 and whose control electrode receives the cutoff pulse φ _T , and the other of the output regions of the first and second transistors Q _A1 and Q _A2 . Contact S1
a circuit consisting of transistors Q _P1 and Q S1 controlling the common potential of the transistors Q P1 and Q _S1 , and a fifth transistor Q _D1 having one of its output regions coupled to the first digit line B1 and a control electrode connected to the second sense contact A2; , one of the output areas is coupled to the second digit line B2, and the first
A circuit consisting of a sixth transistor Q D2 whose control electrode is connected to the sense contact A1 of the transistor Q _D2 and transistors Q _P2 and Q _S2 that control the potential of the other contact S2 in the common output area of the fifth and sixth transistors. include. In such a one-transistor type MOS memory circuit, the parasitic amount of the sense contacts A1 and A2 is usually
The parasitic capacitance of the digit lines B1 and B2 ranges from 1 to 2 PF. The gain of an example transistor that achieves high-speed and high-sensitivity operation is as follows: The ratio of the channel length (L) to the channel width (W) of transistors Q _A1 and Q _A2 is 2 to 4, and the transistor Q
The goal is to set _D1 and Q _D2 to larger values of 4 to 20, respectively.

Further, in this embodiment, digit lines B1, B
Transistor Q _P which precharges 2 respectively.
₃ , Q _P4 and a transistor Q that balances the potential of the paired digit lines B1 and B2 during precharging.
_C is provided. Pre-charge transistor Q _P
The control electrodes of ₁ , Q _P2 , Q _P3 , and Q _P4 are all driven by a precharge signal φ _P , one of the output regions is coupled to a predetermined potential line V _D , and the other output region is connected to contacts S1, S2, and digits, respectively. Connect to lines B1 and B2. One of the output regions of sense transistors Q _S1 and _S2 is coupled to contacts S1 and S2, respectively, the other is coupled to a common potential (GND), and the control electrodes are driven by sense signals φ _S1 and φ _S2 , respectively. . Further, the reference capacitance element _CDM is charged to the common potential (GND) by the transistor _QR during precharging.

FIG. 2 shows the operating waveforms of FIG. 1. That is, upon completion of precharge, the precharge pulse φ _P falls, and the potentials V _S1 and V S2 of contacts S1 and S2, the potentials V _B1 and V B2 of digit lines B1 and B2, and the potentials V _A1 and V _A1 of sense contacts A1 and _A2 , respectively. V _A2 is charged to approximately 4V. After this pulse φ _P , the balancing pulse φ _C coupled to the control electrode of the transistor Q _C falls,
Next, word pulse φ _W and dummy word pulse φ _DW
rises, and the switch length transistors Q _W1 , Q _W2
conducts to give an information potential to the digit line. The potential difference between the digit lines is transmitted to the sense contact, and the fall of the pulse φ _T electrically disconnects the digit line and the sense contact. Pulse φ _S1 rises around the fall of pulse φ _T , transistor Q _S1 conducts, contact potential V _S1 gradually falls, amplification operation by transistors Q _A1 and Q _A2 starts, and the sense contact potential increases. The potential difference between V _A1 and V _A2 is expanded. Thereafter, the pulse φ _S2 rises, the contact potential V _S2 rapidly falls, the potential difference between the digit lines B1 and B2 is amplified, and the sense refresh operation of the one-transistor type MOS memory is completed.

As described above, in this embodiment, the potential difference between the digit lines B1 and B2, which have a large parasitic capacitance, is amplified by the transistors Q _D1 and Q _D2 which have a large gain, and the gate potential of these transistors is connected to a high-sensitivity wire inside. Controlled by gated flip-flop. Therefore, even if the potential difference of the digit line is rapidly increased, there is no risk of malfunction, and a highly sensitive and high-speed sense/refresh operation can be obtained. Moreover, this embodiment can be obtained with the minimum mask pattern pitch when configuring the sense amplifier circuit as an integrated circuit, and can be used on a large scale.
Achieve high-density MOS memory.

FIG. 3 shows a circuit diagram of another embodiment of the invention. In this embodiment, the same reference symbols are used for parts common to the embodiment of FIG. 1, and the details of the common explanation will be omitted. This embodiment, like the previous embodiment, includes a dynamic gated flip-flop having transistors Q _A1 and Q _A2 whose drains are coupled to sense contacts A ₁ and A ₂ , respectively, and a pair of digit lines B ₁ and B It has an outer gated flip-flop including transistors Q _D1 and Q _D2 coupled to the transistors Q _{D1 and} Q D2 . Sense contacts A ₁ , A ₂ and digit wire B ₁ ,
B ₂ is a transistor Q C whose conductive state is controlled by transistors Q _T1 and Q _T2 , respectively, and the control electrodes of sense contacts A ₁ and A ₂ and digit lines B ₁ and B ₂ are each driven by a balancing pulse _{φ C} , Q _C ' have the same potential upon reset. The circuit elements of this embodiment, which are different from the previous embodiment, are capacitive elements C _B1 and C _B2 , one terminal of which is coupled to each of the sense contacts A ₁ and A ₂ , and a pulse φ _S1 introduced into the other terminal. This capacitive element C _B
1 , C _B2 has an insulated gate capacitance that is more than 1/8 and about 10 times the parasitic capacitance of the sense contact that is cut off from the digit line by the fall of the pulse φ _T , and is The sense sensitivity is improved by suppressing the drop in the potential of the sense contact, and the potential of this contact is actively raised to increase the driving ability of the outer flip-flop. The lower limit of the capacitance is the minimum capacitance for exhibiting sense sensitivity, and the upper limit is determined in consideration of wasted power consumption and delay in access time due to excess potential rise. In this example, the preferred range is 0.02PF to 1PF.

FIG. 4 shows operating waveforms of the embodiment of FIG. In this embodiment, the digit _line is
A pulse φ _C that completes the precharge operation of B ₁ , B ₂ , sense contacts A ₁ , A ₂ , and contacts S ₁ , S ₂ and balances the potential of sense contacts A ₁ , A ₂ and digit lines B ₁ , B ₂ . The reset operation is completed when the voltage falls. Pulse φ
The rise in _W and φ _DW gives stored information to the digit lines B ₁ and B ₂ and the sense contacts A ₁ and A ₂ as in the previous embodiment,
Thereafter, the digit line and the sense contact are electrically interrupted by the fall of the pulse _φT . Then pulse φ
As _S1 rises, the contact potential V _S1 falls, the inner flip-flop operates, and the sense contact potentials V _A1 , V
The potential difference of _A1 is amplified. At this time, in this embodiment, the "pull-in K" of the sense contact potential on the high potential side is suppressed by the bootstrap effect of the capacitive element, and the potential becomes higher than the precharge level. Therefore, as the pulse φ _S2 rises, the contact potential V _S2
When the voltage decreases and the outer transistors Q _D1 and Q _D1 operate, the drive voltage to the control electrode is high, so the mutual conductance increases, causing the digit line potential on the low potential side to drop sharply.

In this embodiment, since a bootstrap effect is provided for the sense contact, the potential difference between the digit line potentials V _B1 and V _B2 during refreshing can be made larger than in the previous embodiment. Therefore, this embodiment has the advantages of good refresh operation, high sense sensitivity, and fast access time to the MUS memory of information obtained through the digit line. Furthermore, the circuit operation is completely dynamic and has low power consumption performance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of this invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a circuit diagram showing another embodiment of this invention, and FIG. FIG. 3 is an operational waveform diagram of the embodiment. In the figure, A1, A2... pair of sense contacts, B
1, B2... Paired digit lines, Q _A1 ... First transistor, Q _A2 ... Second transistor, Q _T1 ... Third transistor, Q _T2 ... Fourth transistor, Q _D1 ... Fifth transistor, Q
_D2 ...Sixth transistor, C _B1 , C _B2 ... Capacitive element.

Claims (1)

[Claims] 1. A first transistor having one of its output regions coupled to a first sense contact and a control electrode coupled to a second sense contact; and a first transistor having one of its output regions coupled to a second sense contact. a second transistor having a control electrode coupled to the first sense contact, a third transistor having an output region coupled to the first sense contact and the first digit line, respectively, and a control electrode receiving a cutoff pulse; a fourth transistor whose output region is coupled to the sense contact and the second digit line, respectively, and whose control electrode receives a cutoff pulse; and a common potential of the other contact of the output region of the first and second transistors. a fifth transistor having one of its output regions coupled to the first digit line and a control electrode connected to the second sense contact; a fifth transistor having one of its output regions coupled to the second digit line; a sixth transistor having a control electrode connected to the first sense contact; and a second control means for controlling the potential of the other contact of the common output region of the fifth and sixth transistors. Transistor circuits for semiconductor storage devices, including: 2. The semiconductor memory device according to claim 1, wherein gain constants of the fifth and sixth transistors are larger than gain constants of the first and second transistors. transistor circuit. 3. Claim 1, characterized in that each of the first and second sense contacts has one terminal coupled to the other end of capacitive elements C _B1 and C _B2 which are commonly coupled to a pulse signal. 2. The transistor circuit for a semiconductor memory device according to item 1.