CN114388015B - Read-out circuit structure - Google Patents
Read-out circuit structure Download PDFInfo
- Publication number
- CN114388015B CN114388015B CN202210036563.0A CN202210036563A CN114388015B CN 114388015 B CN114388015 B CN 114388015B CN 202210036563 A CN202210036563 A CN 202210036563A CN 114388015 B CN114388015 B CN 114388015B
- Authority
- CN
- China
- Prior art keywords
- active region
- bit line
- gate
- type
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
The application relates to a read-out circuit structure, comprising: a first N-type active region and a first gate electrode disposed on the first N-type active region; a second N-type active region and a second gate electrode disposed on the second N-type active region; a first P-type active region and a third gate disposed on the first P-type active region; a second P-type active region and a fourth gate electrode disposed on the second P-type active region; the first isolation grid is used for forming a first isolation tube; the application can effectively reduce the data reading time length.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a read-out circuit structure.
Background
Memory timing (Memory timings) are four parameters describing the performance of dynamic random access Memory (Dynamic Random Access Memory, DRAM), including: CAS Latency (CL), row address to column address delay (tRCD), row precharge time (tRP), and row active time (tRAS).
The row address to column address delay tRCD, which is the minimum number of clock cycles required to open a row of memory and access a column therein, requires a time interval t from row open to column open greater than tRCD during the design of the DRAM to ensure proper read-out of the data in the memory cells.
However, in the current data readout process of the DRAM, the time between the row opening and the column opening, that is, the charge sharing stage of the sense amplifier, ensures the delay of tRCD through the time of the charge sharing stage, resulting in longer readout process time of the sense amplifier, which results in longer data readout time of the DRAM.
Disclosure of Invention
In view of the above, it is desirable to provide a read circuit structure capable of reducing the data read time period.
A readout circuit structure comprising:
the first N-type device unit comprises a first N-type active region and a first grid electrode arranged on the first N-type active region, wherein the first grid electrode is used for forming a first N-type transistor;
the second N-type device unit comprises a second N-type active region and a second grid electrode arranged on the second N-type active region, and the second grid electrode is used for forming a second N-type transistor;
the first P-type device unit comprises a first P-type active region and a third grid electrode arranged on the first P-type active region, wherein the third grid electrode is used for forming a first P-type transistor;
The second P type device unit comprises a second P type active region and a fourth grid electrode arranged on the second P type active region, and the fourth grid electrode is used for forming a second P type transistor;
the first processing unit comprises a first active region and a first isolation grid electrode arranged on the first active region, wherein the first isolation grid electrode is used for forming a first isolation tube;
the second processing unit comprises a second active region and a second isolation grid electrode arranged on the second active region, wherein the second isolation grid electrode is used for forming a second isolation tube;
one end of the first P-type active region and one end of the first N-type active region are connected with a first readout bit line, and the third grid electrode and the first grid electrode are connected with a second readout bit line; one end of the second P-type active region and one end of the second N-type active region are connected with a first complementary read bit line, and the fourth grid electrode and the second grid electrode are connected with a second complementary read bit line; the other end of the first P-type active region and the other end of the second P-type active region are connected with a first signal end, and the other end of the first N-type active region and the other end of the second N-type active region are connected with a second signal end; one end of the first isolation tube is connected with the first readout bit line, the other end of the first isolation tube is connected with the initial bit line, one end of the second isolation tube is connected with the first complementary readout bit line, and the other end of the second isolation tube is connected with the initial complementary bit line; and the first sense bit line is connected to the second complementary sense bit line, the first complementary sense bit line is connected to the second sense bit line.
In one embodiment, the readout circuit structure further includes:
the first capacitor grid is used for forming a first transistor capacitor;
the third active region is connected to the first sense bit line, and the first capacitive gate is connected to the second complementary sense bit line.
In one embodiment, the third active region is the same active region as the first active region.
In one embodiment, the first capacitor gate and the second gate are of the same metal pattern structure.
In one of the embodiments of the present invention,
the third active layer is positioned between the second N-type active layer and the second P-type active layer;
or the third active layer is positioned between the second N-type active layer and the second active layer;
or, the third active layer is located between the second N-type active layer and the first N-type active layer.
In one embodiment, the readout circuit structure further includes:
the first capacitor grid is used for forming a first transistor capacitor;
The third active region is connected to the second complementary sense bit line, and the first capacitive gate is connected to the first sense bit line.
In one embodiment, the third active region and the second active region are the same active region.
In one embodiment, the third active region and the first capacitor gate are located between the first N-type active region and the first P-type active region, or the third active region and the first capacitor gate are located between the first N-type active region and the second N-type active region.
In one of the embodiments of the present invention,
the first capacitor gate spans the third active region; or alternatively, the process may be performed,
the first capacitor grid electrode is arranged opposite to the third active region part, and a space is arranged between the first capacitor grid electrode and one side edge of the third active region in the direction perpendicular to the conducting channel of the first transistor capacitor.
In one embodiment, the readout circuit structure further includes:
a fourth active region and a second capacitive gate disposed on the fourth active region, the second capacitive gate being configured to form a second transistor capacitance;
the fourth active region is connected to the first complementary sense bit line, and the second capacitive gate is connected to the second sense bit line.
In one embodiment, the fourth active region and the second active region are the same active region.
In one embodiment, the second capacitor gate and the first gate are of the same metal pattern structure.
In one of the embodiments of the present invention,
the fourth active region is positioned between the first N-type active region and the first P-type active region;
or, the fourth active region is located between the first N-type active region and the first active region;
alternatively, the fourth active region is located between the second N-type active region and the first N-type active region.
In one embodiment, the readout circuit structure further includes:
a fourth active region and a second capacitive gate disposed on the fourth active region, the second capacitive gate being configured to form a second transistor capacitance;
the fourth active region is connected to the second sense bit line, and the second capacitive gate is connected to the first complementary sense bit line.
In one embodiment, the fourth active region is the same active region as the first active region.
In one embodiment, the fourth active region and the second capacitor gate are both located between the second N-type active region and the second P-type active region.
In one of the embodiments of the present invention,
the second capacitor gate spans the fourth active region; or alternatively, the process may be performed,
the second capacitor grid electrode is arranged opposite to the fourth active region part, and a space is arranged between the second capacitor grid electrode and one side edge of the fourth active region in the direction perpendicular to the conducting channel of the second transistor capacitor.
In one of the embodiments of the present invention,
a first offset cancellation gate is further arranged on the first active region, the first offset cancellation gate is used for forming a first offset cancellation tube, and two ends of the first offset cancellation tube are respectively connected with the first readout bit line and the second readout bit line;
and a second offset elimination grid electrode is further arranged on the second active region and used for forming a second offset elimination tube, and two ends of the second offset elimination tube are respectively connected with the first complementary read bit line and the second complementary read bit line.
In one of the embodiments of the present invention,
a first pre-charge grid electrode is further arranged on the first active region and used for forming a first pre-charge tube, and the first pre-charge tube is connected with the initial bit line;
and a second pre-charge grid electrode is further arranged on the second active region and used for forming a second pre-charge tube, and the second pre-charge tube is connected with the initial complementary bit line. ,
In the above-mentioned sense circuit structure, the first isolation tube is provided to isolate the initial bit line from the first sense bit line, and the second isolation tube is provided to isolate the initial complementary bit line from the first complementary sense bit line. Thus, the potentials on the first sense bit line, the second sense bit line, the first complementary sense bit line, and the second complementary sense bit line are trimmed to eliminate the offset, while the potentials on the initial bit line and the initial complementary bit do not affect the performance of offset elimination. Therefore, the application can perform charge sharing at the same time of the offset elimination stage, thereby effectively reducing the data reading time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic circuit diagram of a readout circuit according to an embodiment of the application;
FIG. 2 is a timing diagram of a read circuit structure according to an embodiment of the application;
Fig. 3 to 9 are schematic structural diagrams of a readout circuit corresponding to the circuit shown in fig. 2 according to various embodiments of the present application;
FIG. 10 is a circuit diagram of a read-out circuit structure according to another embodiment of the application;
fig. 11 to 16 are schematic structural diagrams of a readout circuit structure corresponding to the circuit shown in fig. 10 according to various embodiments of the present application.
Reference numerals illustrate:
reference numerals illustrate: 110-first N-type transistor, 111-first N-type active region, 112-first gate, 120-second N-type transistor, 121-second N-type active region, 122-second gate, 210-first P-type transistor, 211-first P-type active region, 212-third gate, 220-second P-type transistor, 221-second P-type active region, 222-fourth gate, 310-first isolation transistor, 311-first active region, 312-first isolation gate, 320-second isolation transistor, 321-second active region, 322-second isolation gate, 410-first offset cancellation transistor, 412-first offset cancellation gate, 420-second offset cancellation transistor, 422-second offset cancellation gate, 510-first pre-charge transistor, 512-first pre-charge gate, 520-second pre-charge transistor, 522-second pre-charge gate, 600-first transistor capacitor, 601-third active region, 602-first capacitor gate, 602-second capacitor transistor, 700-second capacitor, 700-fourth active region, 702-active region.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In the drawings, the size of layers and regions may be exaggerated for clarity of illustration. It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, like reference numerals refer to like elements throughout.
In the following embodiments, when a layer, region or element is "connected," it can be construed that the layer, region or element is not only directly connected but also connected through other constituent elements interposed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or electrically connected but also through another layer, region, element, etc. interposed therebetween.
Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are used only to distinguish one component from another. It will also be understood that the use of the expression "a" or "an" includes the plural unless the singular is in a context clearly different.
It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
In one embodiment, referring to fig. 1 to 3, a readout circuit structure is provided, which includes: the device comprises a first N-type device unit, a second N-type device unit, a first P-type device unit, a second P-type device unit, a first processing unit and a second processing unit.
The first N-type device cell includes a first N-type active region 111 and a first gate 112 disposed on the first N-type active region 111. The first N-type transistor 110 may be formed based on the first N-type active region 111 and the first gate 112. As an example, the first N-type transistor 110 may be a first NMOS transistor; the first N-type transistor 110 includes a first gate 112 and a first N-type active region 111 corresponding thereto.
As an example, the first N-type device unit may include a plurality of first N-type active regions 111 and a plurality of first gates 112, and the plurality of first N-type active regions 111 may be separately arranged in the first direction; at least one first gate 112 is disposed on each first N-type active region 111, thereby forming a plurality of first N-type transistors 110.
Of course, the first N-type device unit may include only one first N-type active area 111 and one first gate 112, and when the first N-type device unit includes a plurality of first N-type active areas 111, only one first gate 112 may be disposed on each first N-type active area 111, which is not limited herein.
The second N-type device unit includes a second N-type active region 121 and a second gate 122 disposed on the second N-type active region 121. A second N-type transistor 120 may be formed based on the second N-type active region 121 and the second gate 122; as an example, the second N-type transistor 120 may be a second NMOS transistor; the second N-type transistor 120 includes a second gate 122 and a second N-type active region 121 corresponding thereto.
As an example, the second N-type device unit may include a plurality of second N-type active regions 121 and a plurality of second gates 122, and the plurality of second N-type active regions 121 may be separately arranged in the first direction; at least one second gate 122 is disposed on each second N-type active region 121, thereby forming a plurality of second N-type transistors 120.
Of course, the second N-type device unit may include only one second N-type active region 121 and one second gate 122; when the first N-type device unit includes a plurality of second N-type active regions 121, only one second gate electrode 122 may be disposed on each second N-type active region 121, which is not limited herein.
The first P-type device cell includes a first P-type active region 211 and a third gate 212 disposed on the first P-type active region 211. A first P-type transistor 210 may be formed based on the first P-type active region 211 and the third gate 212; as an example, the first P-type transistor 210 may be a first PMOS transistor; the first P-type transistor 210 includes a third gate 212 and a corresponding first P-type active region 211.
As an example, the first P-type device unit may include a plurality of first P-type active regions 211 and a plurality of third gates 212, and the plurality of first P-type active regions 211 may be separately arranged in the first direction, and at least one third gate 212 is disposed on each of the first P-type active regions 211, thereby forming a plurality of first P-type transistors 210.
Of course, the first P-type device unit may include only one first P-type active region 211 and one third gate 212, and when the first N-type device unit includes a plurality of first P-type active regions 211, only one third gate 212 may be disposed on each first P-type active region 211, which is not limited herein.
The second P-type device unit includes a second P-type active region 221 and a fourth gate 222 disposed on the second P-type active region 221. The second P-type transistor 220 may be formed based on the second P-type active region 221 and the fourth gate 222; as an example, the second P-type transistor 220 may be a second PMOS transistor; the second P-type transistor 220 includes a fourth gate 222 and a second P-type active region 221 corresponding thereto.
As an example, the second P-type device unit may include a plurality of second P-type active regions 221 and a plurality of fourth gates 222, and the plurality of second P-type active regions 221 may be separately arranged in the first direction, and at least one fourth gate 222 is disposed on each second P-type active region 221, thereby forming a plurality of second P-type transistors 220.
Of course, the second P-type device unit may also include only one second P-type active region 221 and one fourth gate 222; when the first N-type device unit includes a plurality of second P-type active regions 221, only one fourth gate 222 may be disposed on each second P-type active region 221, which is not limited herein.
The first processing unit includes a first active region 311 and a first isolation gate 312 disposed on the first active region 311. The first isolation tube 310 may be formed based on the first active region 311 and the first isolation gate 312. The first isolation tube 310 includes a first isolation gate 312 and a first active region 311 corresponding thereto; the first isolation gate 312 may be connected to a first isolation signal terminal. The first isolation signal terminal is configured to receive the first isolation signal ISO1, and open the first isolation tube 310 according to the first isolation signal ISO 1.
As an example, the first processing unit may include a plurality of first active regions 311, the plurality of first active regions 311 being separately arranged in a first direction, and a first isolation gate 312 being disposed on each of the separate first active regions 311 and extending in the first direction.
The second processing unit includes a second active region 321 and a second isolation gate 322 disposed on the second active region 321. The second isolation tube 320 may be formed based on the second active region 321 and the second isolation gate 322; the second isolation tube 320 includes a second isolation gate 322 and a second active region 321 corresponding thereto; the second isolation gate 322 may be connected to a second isolation signal terminal. The second isolation signal terminal is configured to receive the second isolation signal ISO2, and open the second isolation tube 320 according to the second isolation signal ISO 2.
As an example, the second processing unit may include a plurality of second active regions 321, the plurality of second active regions 321 being separately arranged in the first direction, and the second isolation gate 322 being disposed on each of the separate second active regions 321 and extending in the first direction.
Of course, the first processing unit may include only the first active region 311, the second processing unit may include only one second active region 321, and so on. And the like, are not limited herein.
Meanwhile, in the present embodiment, one end of the first P-type active region 211 and one end of the first N-type active region 111 are connected to the first sensing bit line SABL, the third gate 212 and the first gate 112 are connected to the second sensing bit line ISABL, so that the drain of the first P-type transistor 210 and the drain of the first N-type transistor 110 are connected to the first sensing bit line SABL, and the gate of the first P-type transistor 210 and the gate of the first N-type transistor 110 are connected to the second sensing bit line ISABL.
One end of the second P-type active region 221 and one end of the second N-type active region 121 are connected to the first complementary sense bit line SABLB, and the fourth gate 222 and the second gate 122 are connected to the second complementary sense bit line isalb, so that the drain of the second P-type transistor 220 and the drain of the second N-type transistor 120 are connected to the first complementary sense bit line SABLB, and the gate of the second P-type transistor 220 and the gate of the second N-type transistor 120 are connected to the second complementary sense bit line isalb.
The other end of the first P-type active region 211 and the other end of the second P-type active region 221 are connected to a first signal terminal, so that the source of the first P-type transistor 210 and the source of the second P-type transistor 220 are connected to the first signal terminal, and the first signal terminal is configured to receive the first level signal PCS.
The other end of the first N-type active region 111 and the other end of the second N-type active region 121 are connected to a second signal terminal, so that the source of the first N-type transistor 110 and the source of the second N-type transistor 120 are connected to the second signal terminal, and the second signal terminal is configured to receive the second level signal NCS. One of the first level signal and the second level signal is a high level signal, and the other is a low level signal.
Meanwhile, in the present embodiment, a first active region 311 and a second active region 321 are also provided. The first active region 311 has one end connected to the first sense bit line SABL and the other end connected to the initial bit line BLT, so that the source and drain of the first isolation tube 310 are connected to the first sense bit line SABL and the initial bit line BLT, respectively. One end of the second active region 321 is connected to the first complementary sense bit line SABLB, and the other end is connected to the initial complementary bit line BLB, so that the source and the drain of the second isolation tube 320 are respectively connected to the first complementary sense bit line SABLB and the initial complementary bit line BLB; and the first sense bit line SABL is connected to the second complementary sense bit line isabel, and the first complementary sense bit line SABLB is connected to the second sense bit line isabel.
In reading a memory cell using the readout circuit structure of this embodiment, it may include:
in the first stage, the initial bit line BLT, the initial complementary bit line BLB, the first sense bit line SABL, the second sense bit line isabelb, the first complementary sense bit line SABLB, and the second complementary sense bit line isabelb may be precharged, and the precharge voltage VBLP is VDD/2.
And a second stage, in which the pre-charge is stopped, and the first signal terminal and the second signal terminal are respectively provided with a first level signal PCS and a second level signal NCS, wherein the first level signal PCS may be VDD, and the second level signal may be 0 (ground signal), so that the potentials on the first sensing bit line SABL, the second sensing bit line isab, the first complementary sensing bit line SABLB and the second complementary sensing bit line isab are trimmed, and offset cancellation is performed.
By controlling the first isolation tube 310 and the second isolation tube 320 not to be conductive in the offset canceling stage, charge sharing can be realized while the offset canceling stage is performed in the offset canceling process of the electric potentials on the first sense bit line SABL, the second sense bit line isalb, the first complementary sense bit line SABLB, and the second complementary sense bit line isalb, thereby reducing the data readout time and improving the data readout efficiency.
As an example, referring to fig. 2, when the memory cell is read by using the readout circuit structure of the present embodiment, it may include:
the first stage, in the period from t0 to t1, pre-charging is carried out;
a second stage of performing one-end time offset cancellation in a period from t1 to t 3; then, the word line WL is turned on in the period from t2 to t4 to share the logic potential in the memory cell to the initial bit line BLT, thereby performing charge sharing. And, while sharing the charges in the period of t2 to t3, continuing to offset elimination for a period of time; after that, offset cancellation is not performed any more in the period t3 to t4, thereby improving the circuit reliability.
A third stage of amplifying signals of the initial bit line BLT and the initial complementary bit line BLB in a period from t4 to t 5;
and a fourth stage, re-priming in the period from t5 to t 6.
In one embodiment, referring to fig. 1 and fig. 3, a first offset cancellation gate 412 is further disposed on the first active region 311, where the first offset cancellation gate 412 is used to form a first offset cancellation tube 410, and the first offset cancellation tube 410 includes the first offset cancellation gate 412 and the first active region 311 corresponding thereto; the first offset canceling gate 412 receives the first offset canceling signal OC1 and opens the first offset canceling pipe 410 according to the first offset canceling signal OC 1.
Meanwhile, two ends of the first offset cancellation pipe 410 are respectively connected to the first sense bit line SABL and the second sense bit line ISABL.
The second active region 321 is further provided with a second offset cancellation gate 422, the second offset cancellation gate 422 is used for forming a second offset cancellation tube 420, and the second offset cancellation tube 420 comprises the second offset cancellation gate 422 and a second active region 321 corresponding to the second offset cancellation gate 422; the second offset canceling gate 422 receives the second offset canceling signal OC2 and opens the second offset canceling tube 420 according to the second offset canceling signal OC 2.
Meanwhile, both ends of the second offset canceling tube 420 are connected to the first complementary sense bit line SABLB and the second complementary sense bit line isabelb, respectively.
In this embodiment, the first offset canceling tube 410 and the first isolation tube 310 are both located in the first processing unit and can be simultaneously connected to the first sense bit line SABL through the common active area therebetween; the second offset canceling tube 420 and the second isolation tube 320 are both located in the second processing unit and can be simultaneously connected to the first complementary sense bit line SABLB through the common active area therebetween.
In an embodiment, referring to fig. 1 and fig. 3, a first pre-charge gate 512 is further disposed on the first active area 311, the first pre-charge gate 512 is used to form a first pre-charge tube 510, the first pre-charge tube 510 includes the first pre-charge gate 512 and the first active area 311 corresponding thereto, the first pre-charge tube 522 is connected to the initial bit line BLT, the first pre-charge gate 512 receives the first pre-charge signal EQ1, and the first pre-charge tube 510 is opened according to the first pre-charge signal EQ 1.
The second active area 321 is further provided with a second pre-charge gate 522, the second pre-charge gate 522 is used for forming a second pre-charge tube 520, the second pre-charge tube 520 includes the second pre-charge gate 522 and the first active area 311 corresponding to the second pre-charge gate 522, the second pre-charge tube 520 is connected to the initial complementary bit line BLB, the second pre-charge gate 522 receives the second pre-charge signal EQ2, and the second pre-charge tube 520 is opened according to the second pre-charge signal EQ 2.
In this embodiment, the first pre-charge tube 510 and the first isolation tube 310 are both located in the first processing unit and can be simultaneously connected to the initial bit line BLT through the common active region therebetween, and the second pre-charge tube 520 and the second isolation tube 320 are both located in the second processing unit and can be simultaneously connected to the initial complementary bit line BLB through the common active region therebetween.
In one embodiment, referring to fig. 1 and 3, the readout circuit structure further includes a third active region 601 and a first capacitor gate 602 disposed on the third active region 601, where the first capacitor gate 602 is used to form a first transistor capacitor 600, and the first transistor capacitor 600 includes the first capacitor gate 602 and the third active region 601 corresponding thereto.
The third active region 601 (source-drain of the first transistor capacitor 600) is connected to a first sense bit line SABL, and the first capacitor gate 602 (gate of the first transistor capacitor 600) is connected to a second complementary sense bit line isabel; at this time, the capacitor in the form of MOSCAP constitutes a first transistor capacitor 600, and the first sense bit line SABL and the second complementary sense bit line isabelb are effectively connected through the first transistor capacitor 600.
In one embodiment, referring to fig. 3 to 5, the third active region 601 and the first active region 311 are the same active region.
At this time, the first transistor capacitor 600 and the first isolation tube 310 are both located in the first processing unit, which can effectively save circuit area, and simultaneously, the first isolation tube 310 and the first transistor capacitor 600 can be simultaneously connected to the first sense bit line SABL through the common active region therebetween.
When the first offset cancellation gate 412 and the first pre-charge gate 512 are further disposed on the first active region 311, the first pre-charge gate 512, the first isolation gate 312, the first capacitor gate 602 and the first offset cancellation gate 412 may be sequentially arranged, and the active region between the first pre-charge gate 512 and the first isolation gate 312 may be connected to the initial bit line BLT. The active region between the first isolation gate 312 and the first capacitive gate 602 and the active region between the first capacitive gate 602 and the first offset cancellation gate 412 may both access the first sense bit line SABL.
In one embodiment, referring to fig. 6 and 9, the first capacitor gate 602 and the second gate 122 are in the same metal pattern structure, and the first capacitor gate 602 and the second gate 122 can be simultaneously connected to the second complementary read bit line isabelb through the metal pattern structure.
Specifically, at this time, the metal pattern structures where the first capacitor gate 602 and the second gate 122 are located may extend along the first direction, and the third active region 601 may be disposed above or below the second N-type active region 121 along the first direction.
In one embodiment, referring to fig. 6 and 7, the third active region 601 may be located between the second N-type active region 121 and the second P-type active region 221, or, referring to fig. 8, the third active region 601 may be located between the second N-type active region 121 and the second active region 321, or, referring to fig. 9, the third active region 601 may be located between the second N-type active region 121 and the first N-type active region 111.
At this time, the third active region 601 is an independent active region, and the first capacitor gate 602 may be an independent gate, or may be the same metal pattern structure as the second gate 122.
In one embodiment, referring to fig. 10 and 11, the readout circuit structure further includes a third active region 601 and a first capacitor gate 602 disposed on the third active region 601, where the first capacitor gate 602 is used to form a first transistor capacitor 600, and the first transistor capacitor 600 includes the first capacitor gate 602 and the third active region 601 corresponding thereto.
Meanwhile, in the present embodiment, the third active region 601 (source-drain electrode of the first transistor capacitor 600) is connected to the second complementary sense bit line isabelb, and the first capacitor gate 602 (gate electrode of the first transistor capacitor 600) is connected to the first sense bit line SABL, so that the first sense bit line SABL and the second complementary sense bit line isabelb are effectively connected through the first transistor capacitor 600.
In one embodiment, referring to fig. 11 and 12, the third active region 601 and the second active region 321 are the same active region.
At this time, the first transistor capacitor 600 and the second isolation tube 320 are both located in the second processing unit, so that the circuit area can be effectively saved.
When the second active region 321 is further provided with a second offset cancellation gate 422 and a second pre-charge gate 522, the second isolation gate 322, the second offset cancellation gate 422 and the first capacitor gate 602 may be sequentially arranged; the active region between the second pre-charge gate 522, the second isolation gate 322 may access the initial complementary bit line BLB. The active region between the second isolation gate 322 and the second offset cancellation gate 422 may each access the first complementary sense bit line SABLB; the active region between the second offset cancellation gate 422 and the first capacitive gate 602 may each access a second complementary sense bit line isabelb.
In one embodiment, referring to fig. 13, the third active region 601 and the first capacitor gate 602 are located between the first N-type active region 111 and the first P-type active region 211; alternatively, the third active region 601 and the first capacitor gate 602 are located between the first N-type active region 111 and the second N-type active region 121.
At this time, the third active region 601 is an independent active region, and the first capacitor gate 602 is an independent gate.
In one embodiment, referring to fig. 3, 6, 9, 13, and 16, the first capacitor gate 602 spans the third active region 601, thereby facilitating processing.
In one embodiment, referring to fig. 5, 7, 8, 14 and 15, the first capacitor gate 602 is disposed partially opposite to the third active region 601, and a space is provided between the first capacitor gate 602 and a side edge of the third active region 601 in a direction perpendicular to the conductive channel of the first transistor capacitor 600.
At this time, the third active region 601 between the first capacitor gate 602 and one side edge of the third active region 601 may effectively electrically connect the source region and the drain region located at both sides thereof, thereby effectively forming the first transistor capacitor 600.
It can be appreciated that the third active region 601 in this embodiment may be used as a separate active region, or may be the same active region as other active regions; the first capacitor gate 602 may be used as an independent gate, or may be the same metal pattern structure as other gates.
In one embodiment, referring to fig. 1 and fig. 3, the readout circuit structure further includes a fourth active region 701 and a second capacitor gate 702 disposed on the fourth active region 701, where the second capacitor gate 702 is used to form a second transistor capacitor 700, and the second transistor capacitor 700 includes the second capacitor gate 702 and the fourth active region 701 corresponding thereto.
The fourth active region 701 (source-drain electrode of the second transistor capacitor 700) is connected to the first complementary sense bit line SABLB, the second capacitor gate 702 (gate electrode of the second transistor capacitor 700) is connected to the second sense bit line ISABL, and at this time, the first complementary sense bit line SABLB and the second sense bit line ISABL can be effectively connected through the second transistor capacitor 700.
In one embodiment, referring to fig. 3 to 5, the fourth active region 701 and the second active region 321 are the same active region.
At this time, the second transistor capacitor 700 and the second isolation tube 320 are both located in the second processing unit, which can effectively save circuit area, and simultaneously, the second isolation tube 320 and the second transistor capacitor 700 can be simultaneously connected to the first complementary sense bit line SABLB through the common active area therebetween.
When the second offset canceling gate 422 and the second pre-charge gate 522 are further disposed on the second active region 321, the second pre-charge gate 522, the second isolation gate 322, the second capacitor gate 702 and the second offset canceling gate 422 may be sequentially arranged, an active region between the second pre-charge gate 522 and the second isolation gate 322 may be connected to the initial complementary bit line BLB, and an active region between the second isolation gate 322 and the second capacitor gate 702 and an active region between the second capacitor gate 702 and the second offset canceling gate 422 may be connected to the first complementary read bit line SABLB.
In one embodiment, referring to fig. 6 and 9, the second capacitor gate 702 and the first gate 112 are in the same metal pattern structure, and the second capacitor gate 702 and the first gate 112 can be connected to the second complementary read bit line isabelb at the same time through the metal pattern structure.
Specifically, the metal pattern structure where the second capacitor gate 702 and the first gate 112 are located may extend along the first direction. And the fourth active region 601 may be disposed above or below the first N-type active region 111 in the first direction.
In one embodiment, referring to fig. 6 and 7, the fourth active region 601 is located between the first N-type active region 111 and the first P-type active region 211, or referring to fig. 8, the fourth active region 701 is located between the first N-type active region 111 and the first active region 311, or referring to fig. 9, the fourth active region 701 may be located between the second N-type active region 121 and the first N-type active region 111.
At this time, the fourth active region 701 is an independent active region, and the second capacitor gate 702 may be an independent gate, or may be the same metal pattern as the first gate 112.
In one embodiment, referring to fig. 10 and 11, the readout circuit structure further includes a fourth active region 701 and a second capacitor gate 702 disposed on the fourth active region 701, where the second capacitor gate 702 is used to form a second transistor capacitor 700, and the second transistor capacitor 700 includes the second capacitor gate 702 and the fourth active region 701 corresponding thereto.
The fourth active region 701 (source-drain of the second transistor capacitor 700) is connected to the second sense bit line ISABL, the second capacitor gate 702 (gate of the second transistor capacitor 700) is connected to the first complementary sense bit line SABLB, and the first complementary sense bit line SABLB is effectively connected to the second sense bit line ISABL through the second transistor capacitor 700.
In one embodiment, referring to fig. 11 and 12, the fourth active region 701 and the first active region 311 are the same active region, and the second transistor capacitor 700 and the first isolation tube 310 are both located in the first processing unit, so that the circuit area can be effectively saved.
When the first offset cancellation gate 412 and the first pre-charge gate 512 are further disposed on the first active region 311, the first pre-charge gate 512, the first isolation gate 312, the first offset cancellation gate 412 and the second capacitor gate 702 may be sequentially arranged, an active region between the first pre-charge gate 512 and the first isolation gate 312 may be connected to the initial bit line BLT, an active region between the first isolation gate 312 and the first offset cancellation gate 412 may be connected to the first readout bit line SABL, and an active region between the first offset cancellation gate 412 and the second capacitor gate 702 may be connected to the second readout bit line ISABL.
In one embodiment, referring to fig. 13, the fourth active region 701 and the second capacitor gate 702 are located between the second N-type active region and the second P-type active region, or the fourth active region 701 and the second capacitor gate 702 are located between the first N-type active region 111 and the second N-type active region 121.
At this time, the third active region 601 is an independent active region, and the first capacitor gate 602 is an independent gate.
In one embodiment, referring to fig. 3, 6, 9, 13, and 16, the second capacitor gate 702 spans the fourth active region 701, thereby facilitating processing.
In one embodiment, referring to fig. 5, 7, 8, 14 and 15, the second capacitor gate 702 is disposed partially opposite to the fourth active region 701, and a space is provided between the second capacitor gate 702 and one side edge of the fourth active region 701 in a direction perpendicular to the conductive channel of the second transistor capacitor 700.
At this time, the fourth active region 701 between the second capacitor gate 702 and one side edge of the fourth active region 701 may effectively electrically connect the source region and the drain region located at both sides thereof, thereby effectively forming the second transistor capacitor 700.
It can be appreciated that the fourth active region 701 in this embodiment may be used as a separate active region, or may be the same active region as other active regions; the second capacitor gate 702 may be used as an independent gate, or may be the same metal pattern structure as other gates.
In the description of the present specification, reference to the term "one embodiment" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (20)
1. A readout circuit structure, comprising:
a first N-type active region and a first gate electrode disposed on the first N-type active region;
a second N-type active region and a second gate electrode disposed on the second N-type active region;
a first P-type active region and a third gate disposed on the first P-type active region;
a second P-type active region and a fourth gate electrode disposed on the second P-type active region;
a first active region and a first isolation gate disposed on the first active region;
a second active region and a second isolation gate disposed on the second active region; one end of the first P-type active region and one end of the first N-type active region are connected with a first readout bit line, and the third grid electrode and the first grid electrode are connected with a second readout bit line; one end of the second P-type active region and one end of the second N-type active region are connected with a first complementary read bit line, and the fourth grid electrode and the second grid electrode are connected with a second complementary read bit line; the other end of the first P-type active region and the other end of the second P-type active region are connected with a first signal end, and the other end of the first N-type active region and the other end of the second N-type active region are connected with a second signal end; one end of the first active area is connected with the first readout bit line, the other end of the first active area is connected with the initial bit line, one end of the second active area is connected with the first complementary readout bit line, and the other end of the second active area is connected with the initial complementary bit line; and the first sense bit line is connected to the second complementary sense bit line, the first complementary sense bit line is connected to the second sense bit line.
2. The sensing circuit structure of claim 1, wherein the sensing circuit structure further comprises:
the first capacitor grid is used for forming a first transistor capacitor;
the third active region is connected to the first sense bit line, and the first capacitive gate is connected to the second complementary sense bit line.
3. The sensing circuit structure of claim 2, wherein the third active region is the same active region as the first active region.
4. The sensing circuit structure of claim 2, wherein the first capacitor gate and the second gate are of the same metal pattern structure.
5. The structure of claim 2, wherein,
the third active layer is positioned between the second N-type active layer and the second P-type active layer;
or the third active layer is positioned between the second N-type active layer and the second active layer;
or, the third active layer is located between the second N-type active layer and the first N-type active layer.
6. The sensing circuit structure of claim 1, wherein the sensing circuit structure further comprises:
The first capacitor grid is used for forming a first transistor capacitor;
the third active region is connected to the second complementary sense bit line, and the first capacitive gate is connected to the first sense bit line.
7. The sensing circuit structure of claim 6, wherein the third active region and the second active region are the same active region.
8. The sensing circuit structure of claim 6, wherein the third active region and the first capacitive gate are both located between the first N-type active region and the first P-type active region, or wherein the third active region and the first capacitive gate are both located between the first N-type active region and the second N-type active region.
9. The structure of a readout circuit according to any one of claims 2 to 8, wherein,
the first capacitor gate spans the third active region; or alternatively, the process may be performed,
the first capacitor grid electrode is arranged opposite to the third active region part, and a space is arranged between the first capacitor grid electrode and one side edge of the third active region in the direction perpendicular to the conducting channel of the first transistor capacitor.
10. The sensing circuit structure of claim 1, wherein the sensing circuit structure further comprises:
a fourth active region and a second capacitive gate disposed on the fourth active region, the second capacitive gate being configured to form a second transistor capacitance;
the fourth active region is connected to the first complementary sense bit line, and the second capacitive gate is connected to the second sense bit line.
11. The sensing circuit structure of claim 10, wherein the fourth active region and the second active region are the same active region.
12. The sensing circuit structure of claim 10, wherein the second capacitor gate and the first gate are of the same metal pattern structure.
13. The sensing circuit structure of claim 12, wherein the sensing circuit structure comprises a plurality of transistors,
the fourth active region is positioned between the first N-type active region and the first P-type active region;
or, the fourth active region is located between the first N-type active region and the first active region;
alternatively, the fourth active region is located between the second N-type active region and the first N-type active region.
14. The sensing circuit structure of claim 1, wherein the sensing circuit structure further comprises:
A fourth active region and a second capacitive gate disposed on the fourth active region, the second capacitive gate being configured to form a second transistor capacitance;
the fourth active region is connected to the second sense bit line, and the second capacitive gate is connected to the first complementary sense bit line.
15. The sensing circuit structure of claim 14, wherein the fourth active region is the same active region as the first active region.
16. The sensing circuit structure of claim 14, wherein the fourth active region and the second capacitive gate are both located between the second N-type active region and the second P-type active region.
17. The sensing circuit structure of any of claims 10 or 16, wherein,
the second capacitor gate spans the fourth active region; or alternatively, the process may be performed,
the second capacitor grid electrode is arranged opposite to the fourth active region part, and a space is arranged between the second capacitor grid electrode and one side edge of the fourth active region in the direction perpendicular to the conducting channel of the second transistor capacitor.
18. The structure of claim 1, wherein,
A first offset cancellation gate is further arranged on the first active region, the first offset cancellation gate is used for forming a first offset cancellation tube, and two ends of the first offset cancellation tube are respectively connected with the first readout bit line and the second readout bit line;
and a second offset elimination grid electrode is further arranged on the second active region and used for forming a second offset elimination tube, and two ends of the second offset elimination tube are respectively connected with the first complementary read bit line and the second complementary read bit line.
19. The structure of claim 1, wherein,
a first pre-charge grid electrode is further arranged on the first active region and used for forming a first pre-charge tube, and the first pre-charge tube is connected with the initial bit line;
and a second pre-charge grid electrode is further arranged on the second active region and used for forming a second pre-charge tube, and the second pre-charge tube is connected with the initial complementary bit line.
20. The readout circuit structure according to claim 1, characterized by comprising:
the first P-type transistor is formed based on the first P-type active region and the third grid electrode, a source electrode is connected with the first signal end, and the first signal end is used for receiving a first level signal;
The first N-type transistor is formed based on the first N-type active region and the first grid electrode, a source electrode is connected with a second signal end, and the second signal end is used for receiving a second level signal;
one of the first level signal and the second level signal is a high level signal, and the other is a low level signal;
the grid electrode of the first P-type transistor and the grid electrode of the first N-type transistor are connected with a second readout bit line, and the drain electrode of the first P-type transistor and the drain electrode of the first N-type transistor are connected with a first readout bit line;
a second P-type transistor formed based on the second P-type active region and the fourth gate, the source electrode being connected to the first signal terminal;
a second N-type transistor formed based on the second N-type active region and the second gate, the source electrode being connected to the second signal terminal;
the grid electrode of the second P-type transistor and the grid electrode of the second N-type transistor are connected with a second complementary read bit line, and the drain electrode of the second P-type transistor and the drain electrode of the second N-type transistor are connected with a first complementary read bit line;
the first isolation tube is formed based on the first active region and the first isolation grid, a source electrode and a drain electrode are respectively connected with the first read bit line and the initial bit line, the first isolation grid is connected with a first isolation signal end, and the first isolation signal end is used for receiving a first isolation signal;
And the second isolation tube is formed based on the second active region and the second isolation grid, the source electrode and the drain electrode are respectively connected with the first complementary read bit line and the initial complementary bit line, the second isolation grid is connected with a second isolation signal end, and the second isolation signal end is used for receiving a second isolation signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210036563.0A CN114388015B (en) | 2022-01-13 | 2022-01-13 | Read-out circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210036563.0A CN114388015B (en) | 2022-01-13 | 2022-01-13 | Read-out circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114388015A CN114388015A (en) | 2022-04-22 |
| CN114388015B true CN114388015B (en) | 2023-10-03 |
Family
ID=81202814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210036563.0A Active CN114388015B (en) | 2022-01-13 | 2022-01-13 | Read-out circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114388015B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1135659A (en) * | 1995-01-12 | 1996-11-13 | 三菱电机株式会社 | MOS transistor read amplifier with dynamic controllable threshold voltage |
| CN1481029A (en) * | 2002-08-07 | 2004-03-10 | ���µ�����ҵ��ʽ���� | Semiconductor device with mix-loaded DRAM |
| CN104091801A (en) * | 2014-07-23 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Storage cell array, formation method of storage cell array and drive method of storage cell array |
| CN108257631A (en) * | 2016-12-28 | 2018-07-06 | 三星电子株式会社 | The sense amplifier and memory device eliminated with offset |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100413065B1 (en) * | 2001-01-04 | 2003-12-31 | 삼성전자주식회사 | Arrangement of a bit line boosting capacitor in a semiconductor memory device |
| WO2015033491A1 (en) * | 2013-09-09 | 2015-03-12 | パナソニック株式会社 | Semiconductor storage device and sense amplifier circuit |
-
2022
- 2022-01-13 CN CN202210036563.0A patent/CN114388015B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1135659A (en) * | 1995-01-12 | 1996-11-13 | 三菱电机株式会社 | MOS transistor read amplifier with dynamic controllable threshold voltage |
| CN1481029A (en) * | 2002-08-07 | 2004-03-10 | ���µ�����ҵ��ʽ���� | Semiconductor device with mix-loaded DRAM |
| CN104091801A (en) * | 2014-07-23 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Storage cell array, formation method of storage cell array and drive method of storage cell array |
| CN108257631A (en) * | 2016-12-28 | 2018-07-06 | 三星电子株式会社 | The sense amplifier and memory device eliminated with offset |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114388015A (en) | 2022-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100646972B1 (en) | 3T1D Memory Cells Using Gated Diodes and Methods of Use Thereof | |
| US4584672A (en) | CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge | |
| CN111933195B (en) | Sense amplifier, memory and control method of sense amplifier | |
| JP4994135B2 (en) | Sense amplification circuit and sense amplification method | |
| US4493056A (en) | RAM Utilizing offset contact regions for increased storage capacitance | |
| US20020154561A1 (en) | Sense amplifier for reduction of access device leakage | |
| US4413330A (en) | Apparatus for the reduction of the short-channel effect in a single-polysilicon, one-device FET dynamic RAM array | |
| US4543500A (en) | High performance dynamic sense amplifier voltage boost for row address lines | |
| EP0834883B1 (en) | Semiconductor nonvolatile memory device | |
| US4247917A (en) | MOS Random-access memory | |
| KR100633653B1 (en) | An interleaved sense amplifier with a single-sided precharge device | |
| US5835403A (en) | Multiplication of storage capacitance in memory cells by using the Miller effect | |
| US5926410A (en) | Memory array architecture and method for dynamic cell plate sensing | |
| US5905686A (en) | Fast sense amplifier for small voltage differences | |
| CN114388015B (en) | Read-out circuit structure | |
| EP4246520A1 (en) | Sensing amplification circuit and data readout method | |
| US20230005522A1 (en) | Readout circuit structure | |
| US4370575A (en) | High performance dynamic sense amplifier with active loads | |
| US4543501A (en) | High performance dynamic sense amplifier with dual channel grounding transistor | |
| US5995410A (en) | Multiplication of storage capacitance in memory cells by using the Miller effect | |
| CN115411035A (en) | Read circuit layout, structure and memory layout | |
| US6597040B2 (en) | Semiconductor device having MOS transistor for coupling two signal lines | |
| JPH054753B2 (en) | ||
| US20030189857A1 (en) | Semiconductor memory device | |
| CN116467988A (en) | Reading out circuit layout |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |