JPS6156575A - Output device of picture data - Google Patents

Abstract

PURPOSE:To reduce comparatively the memory capacity for both the 1st and 2nd memory means regardless of a large size of a display-enable area, by delivering repetitively the picture data on all display-enable areas outputted from a data buffer and then writing and reading those picture data alternately to and out of the 1st and 2nd memory means respectively. CONSTITUTION:The picture data corresponding to areas 11 and 12 are written at first on both virtual frame memories 51 and 52 respectively. Then the picture data a corresponding to the area 11 is read out of the memory 51, and then the data corresponding to the area 12 is read out of the frame 52. Here the picture data corresponding to an area 13 is written on the memory 51. When the picture data corresponding to the area 11 is written on the frame 51, an undesired vector deciding circuit 2 and an out-of-frame monitor circuit 4 are provided between a data buffer 1 and a DDA3 so that the data on the areas excluding the area 11 are not outputted from the DDA3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to an image data output device, for example, in an electrostatic plotter, which develops image data in a frame memory and outputs the developed image data. Regarding output devices.

BACKGROUND OF THE INVENTION FIG. 8 is a diagram showing a state in which image data is interlayered in a frame memory in a conventional electrostatic plotter J'3. For example, in an electrostatic block, coordinate data representing an image output from a host computer is stored in data buffer 1, and a VRC (vector-raster converter) converts the coordinate data read from the data buffer as shown in FIG. A method is used in which vectors are expanded into frame memory.

Problems to be Solved by the Invention In the electrostatic plotter described above, expansion of vectors into image data is normally performed for each vector. Therefore, it is necessary to rearrange the coordinate data in the Y direction so that each vector can be sequentially output. There are two methods for rearranging the coordinate data: one is by the host computer, and the other is by the terminal of the electrostatic plotter, but either method has the disadvantage that data rearranging requires a long processing time.

Another drawback is that the drawing is not output until the processing time ends. On the other hand, as a method of omitting rearrangement of coordinate data, there is a method of having a memory for all frames, but this method requires an enormous amount of memory proportional to the displayable area mentioned above.

Means for Solving the Problems Therefore, the main object of the present invention is to provide an image data output method that eliminates the need for sorting coordinate data, develops image data into a frame memory at high speed, and outputs it. The purpose is to provide equipment.

This invention divides an area capable of displaying an image consisting of a large number of dots in a first direction and a second direction perpendicular to the first direction into a plurality of areas in the second direction, and First and second storage means that output image data and include a data buffer that temporarily stores the image data, storage areas corresponding to each divided area, and first and second storage means. determining means for determining image data to be written across the area and image data outside the area that does not need to be written to the first or second storage means;
or a control means for alternately writing and reading only the image data within the area to be stored in the second storage means into the first or second storage means.

Operation In this invention, when writing image data to the first storage means, among the image data output from the data buffer 1,
When the determining means determines that the image data is the data in the area to be read into the first storage means, the image data is written into the first storage means. Subsequently, the same image data is output from the data buffer, and at the same time, the image data of only the area to be read into the second storage means is written into the second storage means, and at the same time the image data stored in the first storage means is written. The image data of all the displayable areas outputted from the data buffer 1 are repeatedly outputted, and the image data is alternately written to the first and second storage means, and read and outputted. EXAMPLES The invention will be explained in more detail in the following with examples of embodiments shown in the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention.
FIG. 2 is a diagram for explaining the invention in detail.

First, as shown in FIG.
It is configured to be able to output image data to an area consisting of 9,600 dots in the first direction (direction) and 13,440 dots in the second direction (Y direction) perpendicular to the first direction. And this area 10
is divided into a plurality of parts (61 [1i1 in this embodiment)] in the Y direction. In order to output image data to the divided areas 11 to 16, two virtual frame memories 51 and 52 are used as first and second storage means. Then, the image data sequentially output in the Y direction from the data buffer 1 shown in FIG. 1 is alternately loaded and read by the two virtual frame memories 51 and 52. That is, first, two virtual frame memories 51
．． Image data corresponding to areas 11 and 12 are loaded into both of the virtual frame memories 51 and 52, respectively, and then stored in the virtual frame memory 51.
The image data corresponding to the area 11 entered into the virtual frame memory 52 is read out, and the image data corresponding to the area 12 entered into the virtual frame memory 52 is read out.
The image data corresponding to the image data is read out.

At this time, image data corresponding to area 13 out of the same image data is written into virtual frame memory 51 at the same time. Then, after reading the image data corresponding to the area 12 written in the virtual frame memory 52, the image data corresponding to the area 14 is written in the virtual frame memory 52, and at the same time, the image data corresponding to the area 12 written in the virtual frame memory 51 is read out. The image data corresponding to is read out.

By the way, when writing image data corresponding to area 11 to virtual frame memory 51, it is necessary to write image data that exists only within area 11. However, since all image data in area 10 is read from data buffer 1, some images extend from area 11 to 12, and some image data exists only in area 12.

Therefore, the image data corresponding to the area 11 is stored in the virtual frame memory 51! When inputting data, it is necessary to prevent data other than area 11 from being output from the DDA 3 shown in FIG.

For this purpose, as shown in FIG. 1, an unnecessary vector determining circuit 2 and an out-of-frame monitoring circuit 4 are provided between the data buffer 1 and the DDA 3 as determining means. For example, when writing image data corresponding to area 14 to virtual frame memory 51, unnecessary vector determination circuit 2
It is determined whether image data existing in areas other than 4, that is, areas 11 to 13 or areas 15 to 16, has been output from data buffer 1, and image data that does not correspond to area 14 is given to DDA3. prohibited.

The out-of-frame monitoring circuit 4 is a virtual frame memory 51
．． Image data other than the area to be written to ffi?
J? It is for the purpose of This is data buffer 1
From then on, all the data in area 10 shown in FIG. When outputting the image data to and from the virtual frame memory 51 or 52, it is not possible to read out only the uniform data corresponding to the intermediate gA area 4 from the data buffer 1, so the image data is sequentially output from the data buffer 1. In order to output and output image data corresponding to area 14, when uniform data corresponding to areas 11 to 13 or uniform data corresponding to areas 15 to 16 is being output, 3 is sent to DD.
It is not necessary to write to the virtual frame memories 51 and 52. Therefore, the out-of-frame monitoring circuit 4
When DDA3 determines that image data passing through area 14 and corresponding to areas 11 to 13 or areas 15 to 16 has been generated, the operation of DDA3 is terminated. On the contrary, fr4 area 11 iL/13'& Tahar r4WC
In the case of a vector entering the area 14 from 15 or 16, the out-of-frame visualization device 4 operates the virtual Writing to frame memory 51 or 52 is prohibited.

Then, from the time when the generation address of DDA3 enters the area 14, allocation to the virtual frame memory 51 or 52 is permitted.

FIG. 3 is a concrete block diagram of the unnecessary vector judgment circuit 2 shown in FIG. 1, and FIG.
FIG. 5 is a diagram for explaining the operations of the unnecessary vector determination circuit 2 and the out-of-frame monitoring circuit 4.

First, the configuration of the unnecessary vector determination circuit 2 will be explained with reference to FIG. The unnecessary vector judgment circuit 2 mainly includes a latch 21.26 and a comparator 22.23.27.
and 28, an OR gate 24, 29, and an AND gate 25. The latch 21 receives the Ii! output from the data buffer 11! ii) The Y address of the fulcrum coordinate in the vector included in the image data is latched, and the latch 26 latches the Y address of the end point coordinate in the same vector. The output of latch 21 is applied to one comparison input of each of comparators 228 and 23. The other comparison input of the comparator 22 is the boundary line CU between the areas 12 and 13, as shown in FIG.
The Y address of Δ is given. The other comparison input of the comparator 23 is given the Y address of the boundary line CLΔ between the areas 11 and 12. Therefore, the comparator 22 outputs a trubel signal when the Y address of the starting point coordinates in the vector l~ is not shown in FIG. 5 and is on the boundary MCUA or on the fiA area 1 side 3 side. This torque signal is applied via the OR gate 24 to one input of a gate 251 included in the AND gate 25. Comparator 2
3, the Y address of the starting point coordinates in the vector is area 11
When it is on the side, it outputs a torque signal, which is applied to one input of AND gate 252.

The output of the latch 26 mentioned above is applied to one comparison input of each of comparators 27 and 28.

The other comparison input of the comparator 27 receives the Y address of the boundary line CUA. The other comparison input of the comparator 28 is given the Y address of the boundary line CLA. Therefore, the comparator 27 outputs a trubel signal when the Y address of the end point coordinate in the vector exists on the boundary line CUA or on the area 13 side. This torque signal is passed through the OR gate 29 to the aforementioned AND gate 251.
is given to the other input of The comparator 28 applies a trubel signal to the other input of the AND gate 252 when the Y address of the end point coordinate exists on the region 11 side. Therefore, as shown in FIG. 5, the AND gate 25 outputs a trubel signal when it detects the vector {circle around (2)} whose Y addresses of the start point coordinate and the end point coordinate are on the 1[13 side. Similarly, the AND gate 25 is connected to the vector
The Y address of the start point coordinates and end point coordinates is area 1 as shown in
It also outputs a trubel signal when it detects that it exists at 1.

That is, when the unnecessary vector judgment circuit 2 shown in FIG.
Try not to give it to 3.

Next, the out-of-frame monitoring circuit 4 will be explained with reference to FIG. The out-of-frame monitoring circuit 4 monitors vectors (1), (2), and (2) extending from the area 11 to the area 12 and from the area 1a12 to the area 13 shown in FIG. For this purpose, the out-of-frame monitoring circuit 4 includes comparators 41 and 42, a NOR gate 43, and a D-type flip 70 knob 44.
．． 45. One comparison input of the comparator 41 is given the Y address of the coordinate data generated by the DDA 3, and the other comparison input is given the Y address of the boundary line CLA. Further, one comparison input of the comparator 42 is given the Y address of the coordinate data generated by the DDA 3, and the other comparison input is given the CUA address. Therefore, the comparator 41 outputs the trubel signal when the Y address of the starting point coordinates is closer to the area 11 than the boundary line CLA. The comparator 42 outputs a trubel signal when the Y address of the end point coordinates is on the boundary tilcUA or exists on the area 13 side.

The trubel signals output from the comparators 41 and 42 are passed through a NOR gate 43 to a D type flip 70 tube 4.
It is given to the D input of 4. A clock pulse is applied to this D type flip 70 tube 44. therefore,
D-type flip-flop 44 sets the output of NOR gate 43 based on the clock pulse.

The 0 output of this D type flip-flop 44 is DDA
The coordinate data generated in step 3 satisfies CLA ≦ departure data < C
It outputs a trubel signal when it is UA, and outputs a trubel signal when it is not. This serves as a prohibition signal for the DDA 3 to determine whether to expand the virtual frame memory 51 or 52 data. When this inhibition signal is at L level, data is expanded, and when it is at H level, data expansion is prohibited. This D type flip-flop 4
The 0 output of 4 is applied to the clock pulse input terminal of a D-type flip-flop 45. Note that the D input of the D-drive flip-flop 45 is grounded.

Therefore, D type knob 70 knob 45 is DDA3
When the coordinate data generated in the area 12 goes out of the area, it falls.

FIG. 6 is a timing diagram of each vector passing through a predetermined area. In the timing chart shown in FIG. 6, the output Q of the D type flip 70 knob 45 is the termination signal of the DDA3. In the case of the vector ■, before the end signal is output, the coordinates of the end point of the vector ■ are detected by DD3, and DDΔ3 is stopped. That is, in vector ■, the generation address of DDA3 starts from 18, and D
When the generated address of DA3 is on the boundary line CLA after t1, the 0 output of the D type flip-flop 44 becomes L level. During this period [1], the DDA3 operates, but no data is written into the virtual frame memory 51 or 52. And D type flip-flop 4
When [2 periods have elapsed since the Φ output of DDA3 becomes L level, that is, when the generation address of DDA3 becomes 1E, vector expansion 171 ends.

In addition, in the case of vector ■, the generation address of DDA3 starts from 28, and [after 3 periods have elapsed, that is, DD
When the address of A3 is on the boundary line CUA, DDA
Finish the operation in step 3. In other words, [2 periods are DDA3
operates, and the data is stored in the virtual frame memory 51 or 52.

Furthermore, in the case of vector ■, DDA3 starts operating by 2 from 48, and DDA3 operates during the t4 period until the DDA3 generation address becomes on the boundary line CLA, but the data is transferred to virtual frame memory 51 or 52. Do not write.

Then, during the period t5 until the generation address of DDA3 becomes on the boundary line CUA, DDA3 operates and writes to the virtual frame memory 51 or 52.

When the prohibition signal from the out-of-frame monitoring circuit 4 is input, the DDA 3 prohibits the development of image data in the partial frame memory 51 or 52.

Further, when a termination signal is input, the operation of the DDA 3 is terminated. In addition, in the case of a vector that enters area 12 from area 11 or areas 13 to 16 outside area 12, DD△3 operates from the starting point of the vector, so calculate the X coordinate entering area 12. do not have to. Further, even when a line such as a broken line or a single-point IA line is drawn across multiple areas, it can be drawn continuously.

That is, the DDA 3 develops the image data in the vertical frame memory 51 or 52 only when the image data of the vector existing in the area 12 is output.

As mentioned above, when developing the image data of the area 12 shown in FIG. 5 into the virtual frame memories 51 and 52,
The unnecessary vector determination circuit 2 detects unnecessary vectors ■, (Φ
When it is determined that
, area 11 to 12 or area 13 to 1 as in ■
For vectors that extend from area 12 to area 12, expansion of areas other than area 12 is prohibited, and for vectors that extend from area 12 to area 13 or from area 12 to area 11, the generated data of DDA3 is prohibited from expanding in areas other than area 12. Since the operation of the DDA3 is terminated when it goes out of the area, the time required for the DDA3 to write expanded data to the virtual frame memory 51 or 52 can be reduced by 1 m.
Can process at high speed.

FIG. 7 shows a virtual frame memory 5 according to the present invention.
1.52 is a diagram showing the μ coefficient between the maximum number of drawing vectors that can be expanded to 1.52 and the DDA speed. As is clear from FIG. 7, virtual frame memories 51 and 52 having a memory capacity of 114 MB are used, and the ODA speed is set to 2000 vectors/second.

Further, if the area 10 is output in 60 seconds, the area 10 will be divided into four parts, 11 to 14. In this case, 310,000 vectors can be developed. Also, as a virtual frame memory 51, 52, I
Using MB, 80,000 vectors can be developed at the same ODA speed.

Effects of the Invention As described above, according to the present invention, when image data is stored in the first storage means, out of the image data output from the data buffer, the area to be written to the first storage means is When the data is determined, only that image data is
Then, the same image data is outputted from the data buffer, and at the same time, the image data of only the area to be written to the second storage means is stored in the first storage means. 1Ciil image data is read out, the image data of all the displayable areas outputted from the data buffer 1 is repeatedly outputted, and it is written alternately in the first and second storage means and read out and outputted. Therefore, no matter how large the displayable area is, devices with relatively small memory capacities can be used as the first and second storage means. Moreover, the li required for each area
! Since only the iil#I data is written to the first or second storage means, there is no risk of unnecessary image data being written into the first J5 and second storage means, and writing and reading to and from the first J5 and second storage means can be performed at high speed. It can be done.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a diagram for explaining the invention in detail. FIG. 3 is a concrete block diagram of the unnecessary vector determination circuit shown in FIG. 1. FIG. 4 is a concrete block diagram of the out-of-frame monitoring circuit shown in FIG. 1. FIG. 5 is a diagram for explaining the operation of the unnecessary vector judgment circuit and the out-of-frame monitoring circuit. FIG. 6 is a timing diagram of each vector passing through a predetermined area. FIG. 7 is a diagram showing the maximum number of drawing vectors according to the present invention. FIG. 8 is a diagram showing a state in which image data is developed in a frame memory in a conventional electrostatic plotter. In the figure, 1 is a data buffer, 2 is an unnecessary vector judgment circuit, 3 is an ODA, 4 is an out-of-frame monitoring circuit, 51.
52 is a virtual frame memory, 21.26 is a latch, 22.23.27.28°41.42 is a comparator, 24.29 is an OR gate, 25 is an AND gate, 43
is a NOR gate, and 44.45 is a D-type flip-flop. Kuzu, Figure 5' OcLAcAJA /34Jq-ChiY Figure 8-IsuY Atsushi Figure 6 Pect 11/a) Case D-FF4S's Q output I+t/-Key force 2÷ Base 2B 1 rotation November 14, 1981 Amendment to Procedures

Claims (2)

[Claims] (1) An image data output device for outputting image data to an area capable of displaying an image composed of a large number of dots in a first direction and a second direction perpendicular to the first direction, the device comprising: a data buffer that temporarily stores the image data and sequentially outputs the image data; when the area is divided into a plurality of areas in a second direction, each of the areas includes a storage area corresponding to one divided area; and the image data is sequentially output from the data buffer; first and second storage means for alternately writing and reading image data output from the data buffer; when writing the image data output from the data buffer into the first or second storage means; image data written across the first and second storage means;
a determining means for determining image data outside the area that does not need to be written to the first or second storage means; An image data output device comprising a control means for alternately writing and reading only image data within an area to be written into the first or second storage means into the first or second storage means. Device. (2) The control means, based on the output of the discrimination means, selects data outside the area to be written into the first or second storage means out of the image data output from the data buffer into the first or second storage means. The image data output device according to claim 1, further comprising prohibition means for prohibiting data from being provided to the second storage means.