JPS6156504A - Transversal automatic equalizer - Google Patents

Abstract

PURPOSE:To digitize a circuit and to convert an equalizer into a miniature IC by applying the tap coefficient unit control signals obtained from the output of an adder which adds analog output signals of D/A converters to the reference voltage input terminals of these D/A converters. CONSTITUTION:The delay outputs given from shift registers 131-134 are led to D/A converters 140-144 and converted into analog outputs. These analog output are added together by an adder 15 and delivered to a discriminating part 16. In this case, the tap coefficient unit control signals S0-S4 produced at a controller part 17 are applied to the reference voltage input terminals ref of converters 140-144. Thus the input signal is multiplied by a coefficient inside each of converters 140-144. Therefore each of these converters contains a D/A converting function and also the function of a conventional tap coefficient unit. This can omit the tap coefficient unit.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a transversal automatic equalizer.

The transversal automatic equalizer of the present invention is used, for example, to compensate for multifading that occurs in digital microwave wireless communication systems.

[Conventional technology]

An example of a conventional transversal equalizer is shown in FIG. Figure 2 shows the multi-level QAM modulation method (Quad-ratu modulation method).
This figure shows one channel of the automatic equalizer used for Amplitude Modulation. As shown in FIG. 2, analog input signals are transmitted through a plurality of cascade-connected analog delay elements 21+ to 2.
1. , is input. Analog input signal and analog delay element 21. The outputs of ~21 and 1 are respectively supplied to tap coefficient multipliers 22°~22. ．． and weighting resistor 23°~23
, to the adder 24 manually. The output of the adder 24 is input to the identification circuit 25.

An example of the tap coefficient device of FIG. 2 is shown in FIG. This tap coefficient device is based on a ring modulator system, and is composed of an analog circuit including a diode and a transformer.

[Problem that the invention seeks to solve]

In conventional transversal automatic equalizers, whenever the signal transmission speed changes, it is necessary to redesign the delay circuit to match the signal transmission speed. In addition, in order to increase the compensation accuracy of the equalizer, it is necessary to increase the accuracy of the delay amount.
Therefore, it is necessary to adjust the delay circuit with high precision, but this is quite troublesome. In addition, impedance mismatch of the delay circuit itself and frequency characteristic correction of insertion loss must be taken into account. Therefore, when delay circuits are connected in multiple stages in cascade, a frequency and level compensation circuit is required for each tap output. is required, making design and adjustment complex.

The present inventor proposes a digital transversal type automatic equalizer shown in FIG. 4 as an equalizer that solves these problems. FIG. 4 shows an equalization circuit for one channel in the QAM modulation system when the number of taps is five.

In FIG. 4, an analog input signal input to an input terminal 41 is transferred to an A-D (analog-to-digital) converter 42.
guided by. The output terminal of the A-D converter 42 has four shift registers 43. ~434 are connected in cascade. Output terminal of A-D converter 42 and shift register 4
3. -434 are connected to the input terminal of adder 46 via DA (digital-to-analog) converters 44°-444 and tap coefficient units 45o-454, respectively.

The output terminal of the adder 46 is connected to a buffer amplifier 471 and an A-
amm to which the identification unit 47 consisting of the D converter 472 is connected.
The output of the output section 47 is guided to a demodulator (not shown) and also to a controller section 4.

The controller unit 48 is a circuit including a correlator,
A tap coefficient unit control signal is output to each tap coefficient unit 45° to 454. A-D converter 42 and shift register 43 in FIG. 434, D-A converters 44° to 444, etc., are supplied with a clock signal for timing from a clock generator (not shown).

To explain the operation of the device shown in FIG. 4, an analog input signal input to an input terminal 41 is converted into a digital signal by an A-D converter 42, and then converted to a digital signal by a shift register 43. ~ 434 sequentially, thereby each shift register 431 ~
434, a delayed output delayed by a certain amount of time determined by the clock cycle is taken out. Each delayed output is a D-A converter 4
4.degree. to 444, respectively, are returned to analog quantities, multiplied by coefficients in tap coefficient units 45.degree. to 454, and then added together in an adder 46. The output of the adder 46 is sent to the demodulator via the identification section 47 and is also input to the controller section 48 to generate tap coefficient control signals for each of the coefficient multipliers 450-454.

According to the device shown in FIG. 4, since the amount of delay in the delay circuit can be adjusted by the clock cycle of the clock generator, highly accurate adjustment is possible and changes in signal transmission speed can be easily accommodated.

Furthermore, a frequency compensation circuit is not required regardless of the number of taps.

However, the device shown in Figure 4 still has many analog circuit parts, and in particular uses a ring module type circuit for the tap coefficient unit, so there is a problem that the equalization layer characteristics have frequency dependence. be. Furthermore, the existence of these analog circuit parts prevents the overall digitalization of the circuit, which poses a problem in that it prevents the circuit from being integrated into an integrated circuit and thus from being miniaturized.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention uses an analog input signal that converts an analog input signal into a digital signal.
a digital converter; a digital delay circuit that generates a plurality of digital delay signals by sequentially delaying the digital output signal of the analog-to-digital converter by a predetermined time;
a plurality of digital-to-analog converters for converting each digital delay signal of the digital delay circuit into an analog signal, each having a reference voltage input terminal;
and an adder for adding each analog output signal of the plurality of digital-to-analog converters, and a tap coefficient unit control signal obtained based on the adder output signal is a reference for the plurality of digital-to-analog converters. A transversal automatic equalizer is provided, characterized in that voltages are applied to respective voltage input terminals.

[For production]

An analog input signal is converted into a digital signal by an analog-to-digital converter, and then inputted to a digital delay circuit, and sequentially delayed by a predetermined period of time to obtain a plurality of digital delay signals. The plurality of digital delayed signals are each converted into an analog signal via a digital-to-analog converter, and then added by an adder. A tap coefficient multiplier control signal is obtained based on the output of this adder, and is applied to a reference voltage input terminal provided in each digital-to-analog converter. As a result, multiplication of coefficients, which was conventionally performed in an analog type tap coefficient unit, can be performed inside the digital-to-analog converter itself, and a tap coefficient unit can be made unnecessary. Therefore, the frequency dependence of the equalizer characteristics is reduced, digitization of the circuit is further promoted, and the equalization layer can be integrated into an integrated circuit and miniaturized.

〔Example〕

A transversal type automatic equalizer as an embodiment of the present invention is shown in FIG. FIG. 1 shows an equalization circuit for one channel in the QAM modulation system when the number of taps is five.

In FIG. 1, an analog input signal input to an input terminal 11 is guided to an input terminal of an A/D converter 12. In FIG. A-
Four shift registers 13 are connected to the output terminal of the D converter 12.
+ to 134 are connected in cascade. Output terminal of A-D converter 12 and shift register 13. A D-A converter 14. to 134 is connected to each output terminal. ~144 are connected. The D-A converters 14° to 141 have a reference voltage input terminal ver to which a reference voltage for adjusting the output voltage is input.
are provided for each.

The output terminal of each D-A converter 14° to 144 is connected to the adder 1.
5 input terminals. The output terminal of the adder 15 is connected to an identification section 6 consisting of a buffer amplifier 161 and an A/D converter 162. The output of the identification section 16 is guided to a demodulator (not shown) and also to a controller section 17.

The controller section 17 has a conventionally known configuration, and an example of its configuration is partially shown in FIG. As illustrated, the controller section 17 includes a large number of circuits including a delay element (shift register) 171, an exclusive OR circuit 172 as a correlator, and an integration circuit 173. The control unit 17 outputs a tap coefficient unit control signal corresponding to the correlator output to the base voltage input terminal ref of each DA converter 14° to 144. Note that the A-D converter 12 and shift registers 131 to 13 . , DA converters 14° to 144, etc., are supplied with timing clock signals from a clock generator (not shown).

The operation of the FIG. 1 apparatus will now be described. The analog input signal input to the input terminal 11 is converted into a digital signal by the A-D converter 12, and then sent to the shift register 13. ~1
34 and each shift register 131 to 13.
4 causes a delay of one symbol. This amount of delay can be adjusted by the clock cycle of the clock generator.

Each shift register 131-13. Each delayed output from DA converter 14° to 14. After being converted into an analog quantity, it is added by an adder 15 and sent to an identification unit 16.
is output to. At this time, each D-A converter 14° to 144°
The tap coefficient multiplier control signals 30 to s4 generated by the Jln control unit 17 according to the output of the identification unit 16 are led to the reference voltage input terminal ver of each DA converter 14°. ˜144, multiplication of coefficients with the input signal is performed. Therefore, in addition to the function of converting a digital quantity into an analog quantity, each DA converter/IA converter 14.about.144 has the function of a conventional tap coefficient unit, thereby eliminating the need for a tap coefficient unit.

〔Effect of the invention〕

According to the present invention, it is possible to convert the conventional delay line section, which was composed of an analog circuit, into a digital circuit, thereby making it possible to easily adjust the amount of delay with high precision, and to change the signal transmission speed. It will also be easier to respond to Additionally, since a tap coefficient unit is no longer required, it is possible to reduce the frequency dependence of the symmetrical characteristic, and further promote the digitalization of the symmetrical circuit, which brings us one step closer to realizing an all-digital transversal automatic equalizer. As a result,
The integration of these circuits into integrated circuits makes it possible to miniaturize them.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a transversal type automatic equalizer as an embodiment of the present invention, FIG. 2 is a block diagram of a conventional transversal type automatic equalizer, and FIG. 3 is a block diagram of a transversal type automatic equalizer as an embodiment of the present invention. 4 is a block diagram of a transversal automatic equalizer equipped with a delay circuit made of digital circuits, and FIG. 5 is a partial circuit diagram of the controller section in the device shown in FIG. 1. It is. 12...A-D converter, 13. ~134...Shift register, 14°~144...D-A converter, 15.
... adder, 16 ... identification section, 17 ... controller section,
30 to S4...Tap coefficient unit control signal, raf...
Reference voltage input terminal.

Claims (1)

[Claims] 1. An analog-to-digital converter that converts an analog input signal into a digital signal, generating a plurality of digital delay signals by sequentially delaying the digital output signal of the analog-to-digital converter by a predetermined period of time. A digital delay circuit, a plurality of digital delay circuits each converting each digital delay signal of the digital delay circuit into an analog signal.
An analog converter, each having a reference voltage input terminal, and an adder for adding each analog output signal of the plurality of digital-to-analog converters, and a tap obtained based on the adder output signal. A transversal automatic equalizer, characterized in that a coefficient unit control signal is applied to each of the reference voltage input terminals of the plurality of digital-to-analog converters. 2. The transversal type automatic equalizer according to claim 1, wherein the digital delay circuit is composed of shift registers connected in multiple stages.