JPS6156470A - Manufacture of semiconductor photodetector - Google Patents
Manufacture of semiconductor photodetectorInfo
- Publication number
- JPS6156470A JPS6156470A JP59178606A JP17860684A JPS6156470A JP S6156470 A JPS6156470 A JP S6156470A JP 59178606 A JP59178606 A JP 59178606A JP 17860684 A JP17860684 A JP 17860684A JP S6156470 A JPS6156470 A JP S6156470A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- recess
- film
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 230000035945 sensitivity Effects 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 1
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 229910052790 beryllium Inorganic materials 0.000 description 2
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 241000287462 Phalacrocorax carbo Species 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- PWOSZCQLSAMRQW-UHFFFAOYSA-N beryllium(2+) Chemical compound [Be+2] PWOSZCQLSAMRQW-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- SAOPTAQUONRHEV-UHFFFAOYSA-N gold zinc Chemical compound [Zn].[Au] SAOPTAQUONRHEV-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体受光装置の製造方法に係り、特に光電流
の雪崩増倍効果によって感度の大幅な増大を図った雪崩
型光ダイオード（Ａｖａｌａｎｃｈｅ Ｐｏｔ。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor photodetector, and in particular to an avalanche photodiode (Avalanche Pot .
ｄｉｏｄｅ、以下ＡＰＤと略称する）における、上記雪
崩増倍効果に寄与するｐ−ｎ接合の形成方法に関する。The present invention relates to a method for forming a pn junction that contributes to the avalanche multiplication effect in a diode (hereinafter abbreviated as APD).
半導体受光装置にはＰＩＮフォトダイオード。The semiconductor photodetector is a PIN photodiode.
フォトトランジスタ、ＡＰＤ等があるが、ＡＰＤはｐ−
ｎ接合における光電流の雪崩増倍効果を利用しているた
めに他に比べて遥かに高怒度が得られるので、光通信の
受光装置として広く用いられている。There are phototransistors, APDs, etc., but APDs are p-
Since it utilizes the avalanche multiplication effect of the photocurrent in the n-junction, it can obtain a much higher intensity than others, and is therefore widely used as a light receiving device for optical communications.
該光通信において情報の信頼性を高めるため、均一な感
度を有し、且つ雑音の低いＡＰＤの提供が強く要望され
ており、かかる要望に応える製造方法の確立が重要な課
題となっている。In order to improve the reliability of information in optical communications, there is a strong demand for APDs that have uniform sensitivity and low noise, and establishing a manufacturing method that meets these demands has become an important issue.
通常ＡＰＤは、光電流の雪崩増倍を生じる階段接合部と
、その周辺部での局部的雪崩効果を防ぐ所謂ガードリン
グ効果を持つ傾斜接合部との複合構造を有する。A typical APD has a composite structure of a stepped junction that causes avalanche multiplication of photocurrent and a sloped junction that has a so-called guard ring effect that prevents local avalanche effects in the surrounding area.
第２図は、かかるＡＰＤの従来構造を示す模式側断面図
で、図中、１はｎ型インジウム・燐（ＩｎＰ）基板、２
はｎ型１ｎＰバッファ層、３はｐ型インジウム・ガリウ
ム・砒素・ｌ’Ａ （Ｔ ｎ Ｑ ３ ＡｓＰ）光吸収
層、４はｎ型ＴｎＰウィンドウ層、５はｐ°型拡散領域
、６はｐ°型ガードリング領域、７は反射防止兼絶縁膜
、８は上部電極、９は下部電極、ＳＪは階段接合部、Ｇ
Ｊは傾斜接合部を示している。FIG. 2 is a schematic side sectional view showing the conventional structure of such an APD, in which 1 is an n-type indium phosphorus (InP) substrate, 2
is an n-type 1nP buffer layer, 3 is a p-type indium-gallium-arsenic-l'A (T n Q 3 AsP) light absorption layer, 4 is an n-type TnP window layer, 5 is a p°-type diffusion region, and 6 is a p-type ° type guard ring region, 7 is anti-reflection and insulating film, 8 is upper electrode, 9 is lower electrode, SJ is step junction, G
J indicates an inclined joint.
かかる従来構造において、上記階段接合は熱拡散法によ
り、また傾斜接合はイオン注入法により形成されるのが
一般的であり、例えばウィンドウ層がｎ型のガリウム砒
素（ＱａＡｓ）やＩｎＰである場合、階段接合は亜鉛（
Ｚｎ）やカドミウム（Ｃｄ）の熱拡１１ｋにより形成さ
れ、傾斜接合はベリリウム（Ｂｅ）等のイオン注入によ
って形成されていた。In such a conventional structure, the stepped junction is generally formed by a thermal diffusion method, and the inclined junction is generally formed by an ion implantation method. For example, when the window layer is made of n-type gallium arsenide (QaAs) or InP, Stair joints are made of zinc (
The junction was formed by thermal expansion 11k of Zn) or cadmium (Cd), and the inclined junction was formed by ion implantation of beryllium (Be) or the like.
然しなから上記ドーパントの熱拡散によって階段接合を
形成する場合、接合の深さ、接合面の平坦性、接合の急
峻性を制御するのが必ずしも容易ではなく、また拡散に
よってウィンドウ層表面の結晶性が劣化し易いことが知
られている。However, when forming a stepped junction by thermal diffusion of the dopant, it is not always easy to control the depth of the junction, the flatness of the junction surface, and the steepness of the junction, and the crystallinity of the window layer surface is affected by the diffusion. It is known that it is easy to deteriorate.
そのため上記従来方法を用いて製造したＡＰＤにおいて
は、キャリア増倍率の不拘−即ち感度の′１
不均一や、雑音の増大を生じていた。Therefore, in the APD manufactured using the above-mentioned conventional method, the carrier multiplication factor is not limited, that is, the sensitivity is
This resulted in non-uniformity and increased noise.
〔発明が解決しようとする問題点〕
本発明が解決しようとする問題点は、上記雪崩増倍効果
を生せしめる階段接合の深さ、平坦性、急峻性の制御の
困難性、及び結晶表面の劣化に関してである。[Problems to be Solved by the Invention] The problems to be solved by the present invention are the difficulty in controlling the depth, flatness, and steepness of the step junction that causes the avalanche multiplication effect, and the difficulty in controlling the crystal surface. It's about deterioration.
上記問題点の解決は、ウィンドウ居となる一導電型半導
体層に底面が平坦な凹部を形成し、該凹部内にエピタキ
シャル成長手段によって反対導電型層を埋め込むことに
よって、該ウィンドウ層内に光電流増倍に寄与するｐ−
ｎ接合を形成する工程を有する本発明による半４体受光
装置の製造方法によってなされる。The solution to the above problem is to increase the photocurrent in the window layer by forming a recess with a flat bottom surface in the semiconductor layer of one conductivity type and burying a layer of the opposite conductivity type in the recess by epitaxial growth. p-, which contributes twice as much
This is accomplished by a method of manufacturing a semi-four-piece light receiving device according to the present invention, which includes a step of forming an n-junction.
即ち本発明の方法においては、−導電型を有するウィン
ドウ層にエツチング手段を用いて底面が平坦な所定の深
さの凹部を形成し、該凹部内にエピタキシャル成長手段
によって反対導電型半導体層を埋め込み、且つ成長温度
で成長と同時に該反対導電型半導体層の底面と前記凹部
内に表出する でウィンドウ層の表面をアロ１
゛ングせしめることによって、ウィンドウ層内にその表
面から所定の均一な深さを有し、且つ平坦で急峻な、キ
ャリア増倍に寄与するｐ−ｎ接合を形成するとともに、
該反対導電型半導体層をエピタキシャル成長手段で形成
することによって該半導体層を含むウィンドウ層表面の
結晶性の劣化をなくした。That is, in the method of the present invention, a recess with a flat bottom surface and a predetermined depth is formed in a window layer having a conductivity type using an etching means, and a semiconductor layer of an opposite conductivity type is buried in the recess by an epitaxial growth means. At the same time as it grows at the growth temperature, the bottom surface of the opposite conductivity type semiconductor layer and the surface of the window layer exposed in the recess are
By dipping, a p-n junction is formed in the window layer, which has a predetermined uniform depth from the surface, is flat and steep, and contributes to carrier multiplication, and
By forming the opposite conductivity type semiconductor layer by epitaxial growth means, deterioration of the crystallinity of the surface of the window layer including the semiconductor layer is eliminated.
以下本発明の方法を一実施例について、第１図＋ａ）乃
至（ｆ）に示す工程断面図を参照し具体的に説明する。Hereinafter, one embodiment of the method of the present invention will be specifically explained with reference to process cross-sectional views shown in FIGS. 1+a) to (f).
第１図（ａ）参照
通常の液相エピタキシャル成長技術により、例えばキャ
リア濃度１ｘ １０１ Ｇ ｃｍ −３程度のｎ型Ｉｎ
Ｐ基板１上に、ギヤリア濃度１ ×１ＱｌａＣｆｆｉ−
：ｌ、厚さ１μｍ程度のｎ型１ｎＰバフファ層２と、キ
ャリア濃度Ｉ ＸＩＯ”Ｃｍ−’ｌ厚さ１〜２μｍ程度
のｎ型ＩｎＧａＡｓＰ光吸収居３と、キャリア濃度１×
１０１６ ｃｍ −：Ｉ、厚ざ３／！ｍ程度のｎ型１ｎ
Ｐウィンドウ層４とを順次積層形成する。Refer to FIG. 1(a) For example, n-type In with a carrier concentration of about 1x 101 G cm -3 is grown by ordinary liquid phase epitaxial growth technology.
On P substrate 1, gearia concentration 1 × 1QlaCffi-
:l, an n-type 1nP buffer layer 2 with a thickness of about 1 μm, a carrier concentration I
1016 cm -: I, thickness 3/! m type n type 1n
P window layer 4 is sequentially laminated.
第１図（ｂｌ参照
次いで第１のレジストマスク１１を介しｎ型ＩｎＰウィ
ンドウＮ４に、例えば加゛速エネルギー１４０ＫｅＶ
＋ 照射密度５Ｘ１０１３（ＩＪＩ−”程度の条件でベ
リリウム（Ｂｅ）のイオン注入を行い、レジストマスク
１１を除去し、５００〜７００℃程度の温度で２０〜３
０分程度熱処理を施して上記Ｂｅを活性化再分布せしめ
て深さ２μｍ程度のｐ°型拡散領域１２を形成する。こ
の際形成される接合は傾斜接合ＧＪになる。（Ｂｅ”は
ベリリウム・イオン）
第１図（Ｃ１参照
次いで第２のレジストマスク１３を介し、例えばメタノ
ールに１％程度の臭素（Ｂｒ）を混合してなるエツチン
グ液により上記ｐ゛型拡散領域１２の一部を選択的にエ
ンチングし、該ｐ゛型拡散領域１２内に下部のｎ型つィ
ンドウ層４に達する凹部１４を形成する。このエツチン
グ方法は異方性を持たない。従ってサイドエツチング分
を考慮し且つ凹部底面の周辺にｐ゛型拡散領域１２が残
るようにマスク１３の開口寸法を規定しなければならな
い。この周辺部に残るｐ°型拡散領域１２はガードリン
グとして機能する。そしてこの方法によれば底面の平坦
性の優れた凹部が形成される。また深さの制御も容易で
ある。FIG. 1 (see BL) Then, an acceleration energy of 140 KeV, for example, is applied to the n-type InP window N4 through the first resist mask 11.
+ Beryllium (Be) ion implantation is performed under conditions of an irradiation density of 5×1013 (IJI−), the resist mask 11 is removed, and the ion implantation is performed at a temperature of approximately 500 to 700° C.
A heat treatment is performed for about 0 minutes to activate and redistribute the Be, thereby forming a p° type diffusion region 12 having a depth of about 2 μm. The joint formed at this time is a tilted joint GJ. (Be" is a beryllium ion) FIG. 1 (See C1) Next, the p-type diffusion region 12 is etched with an etching solution of, for example, methanol mixed with about 1% bromine (Br) through the second resist mask 13. A recess 14 reaching the lower n-type window layer 4 is formed in the p-type diffusion region 12 by selectively etching a part of the etching.This etching method has no anisotropy. In consideration of this, the opening dimensions of the mask 13 must be determined so that the p-type diffusion region 12 remains around the bottom of the recess.The p-type diffusion region 12 remaining at the periphery functions as a guard ring. According to this method, a concave portion with excellent flatness of the bottom surface is formed.Furthermore, the depth can be easily controlled.
第１図（ｄ）参照
第２のレジストマスク１３を除去した後、化学気相成長
法により該基板の表面に厚さ２０００人程度０二酸化シ
リコン（Ｓｉｎｇ）膜１５を形成し、第３のレジストマ
スク１６を介し弗酸等でエツチングを行って上記凹部１
４内面のＳｉ○２膜１５を選択的に除去する。この際凹
部周辺のｐ゛型拡散領域１２の上面が僅かに表出されて
も支障はない。After removing the second resist mask 13 (see FIG. 1(d)), a silicon dioxide (Sing) film 15 with a thickness of approximately 2,000 layers is formed on the surface of the substrate by chemical vapor deposition, and a third resist mask 13 is formed on the surface of the substrate by chemical vapor deposition. The recess 1 is etched with hydrofluoric acid or the like through a mask 16.
4. Selectively remove the Si○2 film 15 on the inner surface. At this time, there is no problem even if the upper surface of the p' type diffusion region 12 around the recess is slightly exposed.
第１図（ｅ）参照
次いで通常のスライド式液相成長法により上記Ｓ ｉ
Ｏｚ膜１５をマスクにし、上記凹部１４内に選択的にキ
ャリア濃度Ｉ Ｘ１０１８ｃｍ−”程度のｐ゛型ＩｎＰ
層１７を埋め込む。Referring to FIG. 1(e), the above Si
Using the Oz film 15 as a mask, p-type InP with a carrier concentration of about I
Embed layer 17.
上記成長に際しての６５０℃程度の温度により該ｐ°型
ＴｎＰ埋込み［１７の底面はその下部のｎ型１
ウィンドウ層４とアロイングし、該埋込み層１７の
底面には前記凹部の底面に対応して優れた平坦性を有し
、且つ極めて急峻なキャリア濃度勾配を有する階段接合
ＳＪが形成される。また受光面となる該埋込み層１７の
表面は、該埋込み層１７がエピタギシャル成長で形成さ
れるので欠陥の極めて少ない良質な面になる。At a temperature of about 650°C during the above growth, the bottom surface of the p° type TnP [17 is
A step junction SJ is formed on the bottom surface of the buried layer 17 which is alloyed with the window layer 4 and has excellent flatness and an extremely steep carrier concentration gradient corresponding to the bottom surface of the recess. Further, the surface of the buried layer 17, which becomes the light-receiving surface, is a high-quality surface with extremely few defects because the buried layer 17 is formed by epitaxial growth.
第１図（ｆ）参照
以後上記ＳｉＯ□膜１５を除去し、通常通り該基板上に
反射防止兼絶縁用の窒化シリコン（Ｓｉ：＋Ｎ４）膜１
８を形成し、該Ｓｉ、Ｎ４膜１８に電極コンタクト窓を
形成し、蒸着法により該電極コンタクト窓上に金−亜鉛
・合金よりなる上部ｐ電極１９を形成し、金−ゲルマニ
ウム・合金よりなる下部ｎ電極２０を形成して、同図に
示すようなＩｎＰ・ＡＰＤが完成する。図中、２１は受
光部を示す。After referring to FIG. 1(f), the SiO□ film 15 is removed, and a silicon nitride (Si:+N4) film 1 for antireflection and insulation is placed on the substrate as usual.
8, an electrode contact window is formed on the Si, N4 film 18, and an upper p-electrode 19 made of a gold-zinc alloy is formed on the electrode contact window by a vapor deposition method, and an upper p-electrode 19 made of a gold-germanium alloy is formed. A lower n-electrode 20 is formed to complete an InP APD as shown in the figure. In the figure, 21 indicates a light receiving section.
なお本発明の方法は上記実施例に示したＩｎＰ・ＡＰＤ
に限らず、他の化合物半導体よりなるＡＰＤの製造にも
適用される。Note that the method of the present invention is applicable to the InP/APD shown in the above example.
The present invention is also applicable to the manufacture of APDs made of other compound semiconductors.
以よ説明。よう２０本発明、よゎば、ウィ７．ウ
１）層内に優れた平坦度を有し、且つ極めて急峻
なキャリア濃度勾配を有するキャリア増倍用の階段接合
を正確な深さで容易に形成することができ、化合物半導
体による雪崩型光ダイオード（Ａ Ｐ Ｄ）の感度の向
上及び性能の均一化を図ることが出来る。Here's the explanation. 20 This invention, Yowaba, Wi7. cormorant
1) Avalanche-type photodiodes made of compound semiconductors that have excellent intralayer flatness and can easily form stepped junctions for carrier multiplication with an extremely steep carrier concentration gradient at accurate depths. (A P D) sensitivity can be improved and performance can be made uniform.
第１図（ａｌ乃至（ｆ）は本発明の方法における一実施
例の工程断面図で、第２図は従来のＡＰＤの構造を示す
模式側断面図である。
図において、
１はｎ型１ｎＰ基板、
２はｎ型１ｎＰバッファ層、
３はｎ型１ｎＧａＡｓＰ光吸収層、
４はｎ型１ｎＰウィンドウ層、
１１．１３．１６はレジストマスク、
１２はｐ゛型ガードリング領域１２．
１４は凹部、
１５は二酸化シリコン１模、
１７はｐ０型１ｎＰ埋込み層、
１８は窒化シリコン膜、
１９は上部ｐ電極、
２０は下部ｎｌｉ極形酸形
成１は受光部、
ＳＪは階段接合、
ＧＪは傾斜接合を示す。
鳩Ｉ昭
鴫ｌ 酊
竪２唄Figures 1 (al to f) are process cross-sectional views of one embodiment of the method of the present invention, and Figure 2 is a schematic side cross-sectional view showing the structure of a conventional APD. In the figure, 1 is an n-type 1nP 2 is an n-type 1nP buffer layer, 3 is an n-type 1nGaAsP light absorption layer, 4 is an n-type 1nP window layer, 11.13.16 is a resist mask, 12 is a p-type guard ring region 12. 14 is a recess, 15 is a silicon dioxide 1 model, 17 is a p0 type 1nP buried layer, 18 is a silicon nitride film, 19 is an upper p-electrode, 20 is a lower nli electrode type acid formation 1 is a light receiving part, SJ is a stepped junction, and GJ is a sloped junction. Show.Hato I Shohakul Dokutate 2 songs
Claims (1)
該凹部内にエピタキシャル成長手段によって反対導電型
層を埋め込むことによって、該ウィンドウ層内に光電流
増倍に寄与する接合を形成する工程を有することを特徴
とする半導体受光装置の製造方法。A recess is formed in the one-conductivity type semiconductor layer that will become the window layer,
A method for manufacturing a semiconductor light receiving device, comprising the step of forming a junction contributing to photocurrent multiplication in the window layer by embedding a layer of opposite conductivity type in the recess by epitaxial growth means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59178606A JPS6156470A (en) | 1984-08-28 | 1984-08-28 | Manufacture of semiconductor photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59178606A JPS6156470A (en) | 1984-08-28 | 1984-08-28 | Manufacture of semiconductor photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6156470A true JPS6156470A (en) | 1986-03-22 |
Family
ID=16051390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59178606A Pending JPS6156470A (en) | 1984-08-28 | 1984-08-28 | Manufacture of semiconductor photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6156470A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6451674A (en) * | 1987-08-24 | 1989-02-27 | Hitachi Ltd | Semiconductor photodetector |
-
1984
- 1984-08-28 JP JP59178606A patent/JPS6156470A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6451674A (en) * | 1987-08-24 | 1989-02-27 | Hitachi Ltd | Semiconductor photodetector |
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