JPS6156442A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the attainment of increase in integration by increasing the capacitance without causing the leakage of accumulated charges by a method wherein a plurality of capacitors are allowed to have in common grooves serving as capacitors formed in the main surface of a semiconductor substrate. CONSTITUTION:A plurality of capacitors are allowed to have a groove in common. For example, two capacitors are allowed to have a groove in common by forming a P<-> type inversion preventing layer 20 in the substrate 11 at the bottom and the side surfaces of the groove. This unnecessitates the gap of an element-isolating region to isolate the grooves from each other where the capacitor which has conventionally been necessary is formed; therefore, the increase in integration is facilitated, and the chip size can be markedly reduced. Since the two capacitors are cut off by the P<-> type inversion preventing layer 20, the leakage of accumulated charges to adjacent cell capacitors can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device, and particularly to one used for a memory cell capacitor of a dynamic memory.

(Technical Background of the Invention) Due to the recent demand for miniaturization of all ultra-LSI's, in large-capacity dynamic memories, grooves are formed in the silicon substrate as shown in Figure 3 in order to avoid a decrease in the capacity of memory cells. By using it as a capacitor, we aim to increase the capacity. Note that FIG. 3 shows a memory cell for two pits.

In FIG. 3, a field oxidation layer 1!2 and a field inversion prevention layer 3 are formed on the surface of a P-type silicon substrate 1. A trench is provided in the element region surrounded by the field oxide III 2, and a capacitor electrode 5 made of polycrystalline silicon is buried in the inner surface of the trench with a capacitor oxide film 4 interposed therebetween.

An N+ type scattered layer 6 is formed on the substrate 1 side of the groove. These constitute a cell capacitor. Further, a transfer gate electrode 8 is formed on the substrate 1 via a gate oxide III 7. Furthermore, N1 type source and drain regions 9 and 10 are formed on the surface of the substrate 1 on both sides of the transfer gate electrode 8. These constitute a transfer 7 transistor.

[Problems with background technology]

In the dynamic memory shown in FIG. 3, the capacitance increases in accordance with the depth of the groove constituting the capacitor, so the signal color also increases. However, as the integration becomes higher, the distance between adjacent capacitors becomes narrower. For this reason, the N" type diffusion WJ6 formed in contact with the side surface and near the bottom of the groove.
Electrons accumulated in the memory cell leak from the N+ type resistive diffusion layer 6 of the adjacent memory cell (for example, indicated by the arrow in Fig. 3), and the amount of accumulated charge decreases, resulting in misjudgment of ``1'' and ``O'' as electrical signals. Since the groove is deep, such charge leakage cannot be dealt with only by the P-type anti-inversion layer 3 formed under the field oxide m2. On the other hand, in order to prevent the above-mentioned charge leakage, it is necessary to maintain a certain distance or more between the grooves, which becomes a factor that limits high integration.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device such as a dynamitter memory that can increase the capacity without causing leakage of stored charges and can achieve a significantly higher degree of integration. It is something to do.

[Summary of the invention]

The semiconductor device of the present invention is characterized in that a plurality of capacitors share a groove that is formed on the main surface of a semiconductor substrate and serves as a capacitor.

According to such a semiconductor device, a plurality of capacitors can be separated without requiring the conventional spacing between capacitors, so that high integration can be achieved without causing leakage of stored charges.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described along with the manufacturing method shown in FIGS. 1(a) to (e) and FIGS. 2(a) and (b).

In addition, 11p(a) to (e) are cross-sectional views, and FIG. 2(a)
and (b) are plan views, and the cross section taken along line A-A in FIG. 12(a) is shown in FIG. 1(a) and FIG. 2(b).
The cross section taken along the line B-8- corresponds to FIG. 1(b).

First, a field oxide film 12 and a P' type rough yield inversion prevention layer 13 are formed on the surface of a P type silicon substrate 11 using a well-known technique. Next, CVDW with a film thickness of 3000A was applied to the entire surface.
After I-forming M14ttifHfA, a part thereof is selectively etched to form a pattern of the cvom-formed film 14. Subsequently, using the pattern of the cvou film 14 as a mask, a groove 15 having a depth of 3 mm is formed in the substrate 11 by reactive ion etching. Subsequently, after depositing a CVD oxide film 16 with a thickness of i ooo over the entire surface, a photoresist pattern 17 is formed at the bottom of the groove 15 and the center of the side WJ portion by photolithography, and etching is performed using this as a mask. By this, a pattern of the CVDM film 16 is formed (
(Illustrated in FIG. 1(a) and FIG. 2(a)). Subsequently, after removing the photoresist pattern 17, PS was applied to the entire surface.
By depositing a G film 18 and performing heat treatment, N film 18 is deposited on a part of the side wall and bottom of the groove 15 to become one electrode of the capacitor.
4″ type diffusion ff19.19e is formed. ko17) p,
Since the CV D iI pattern 11116 serves as a mask, the N+ type wide diffusion layer 19 is not formed in the center of the bottom and side surfaces of the groove 15 (see FIG. 1(b) and FIG. 2(1)).
)) As shown).

Next, the PSG film 18 and tFCVDi! 1111
After removing the pattern No. 6, BSGIIlt (not shown) is deposited to a film thickness of 2°000 nm and heat-treated at 900° C1, so that an impurity concentration of 5.
A P'' anti-inversion layer 2o having a thickness of 10"cm" is formed (as shown in FIG. 1C). Next, the CVD oxidation 1
After removing the pattern 114, thermal oxidation is performed to form a gate oxide film 21 which also serves as a capacitor oxide film on the exposed surface of the substrate 11. Subsequently, a polycrystalline silicon film is deposited on the entire surface, buried in the groove 15, and then buttered to form the capacitor electrode 22 and transfer gate electrode 23.2.
3 (as shown in FIG. 1(d)). Next, arsenic is ion-implanted using the gate electrodes 23 and 23 as a mask, and N
+ type resource drain regions 24, 24, 25, '25 are formed. Subsequently, after depositing an interlayer insulating film 26 on the entire surface, contact holes are formed. Next, 1 on the entire surface
After depositing two films, patterning is performed to form wirings 27 and 27 (as shown in FIG. 1(e)).

Therefore, the dynamic memory shown in FIG. 1(e) has a structure in which one trench is shared by two capacitors by forming a P-type anti-inversion layer 20 in the substrate 11 at the bottom and side surfaces of the trench 15. There it is. This eliminates the need for the element-length M region spacing to separate the trenches in which capacitors are formed, which was previously required, making it easier to achieve higher integration and significantly reduce the chip size. be able to. In addition, two capacitors are connected to the P-type anti-inversion layer 2.
0, it is possible to prevent leakage of accumulated charges to adjacent cell capacitors.

Note that although the above description has been made regarding the case where one trench is shared by two capacitors, a cell capacitor of a dynamic memory may be configured by having one trench shared by three or more capacitors.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device such as a dynamic memory, which can increase the capacity without causing leakage of stored charges and can achieve a significantly higher degree of integration.

[Brief explanation of drawings]

1(a) to 1(e) are cross-sectional views showing the manufacturing process for obtaining a dynamic memory in an embodiment of the present invention;
Figures (a) and (b) are plan views showing the manufacturing process for obtaining a dynamic memory according to an embodiment of the present invention, and Figure 3 is a cross-sectional view of a conventional dynamic memory. 11... P-type silicon substrate, 12... Field oxide film, 13... Field inversion prevention layer, 14.16.
...CVD oxidation, 15...groove, 17...photoresist pattern, 18...PSGII! , 19...N
+ type scattering layer 20...P- type anti-inversion layer, 21...
Gate oxide film: X (capacitor oxide film), 22... Capacitor N pole,
ψ23...Transfer gate electrode, 24.
25...N++ source and drain regions, 26... Interlayer insulating film, 27... Wiring. Applicant's agent Patent attorney Takehiko Suzue N- 1 - 1 Hehe Φ He 1

Claims (3)

[Claims] (1) A semiconductor device in which a conductive layer is embedded in a groove formed on the main surface of a semiconductor substrate via an insulating film and used as a capacitor, characterized in that one groove is shared by a plurality of capacitors. . (2) A semiconductor device according to claim 1, in which the capacitor is used as a cell capacitor of a dynamic memory. (3) An impurity region for preventing reversal of the same conductivity type as the substrate for isolating a plurality of capacitors is formed in the substrate at the bottom and side surfaces of the groove. Semiconductor equipment.