JPS6154537A - Addition and subtraction system of floating point - Google Patents

Abstract

PURPOSE:To decrease the number of arithmetic circuits down to just one for comparison between exponents of two floating point data A and B, by using a single arithmetic circuit to calculate the difference between both exponents of A and B. CONSTITUTION:Two floating point data A and B are registered to operand registers A1 and B2 respectively, and an arithmetic circuit 3 executes the exponent of A and the exponent of -B for both exponent parts 12 and 22. When the exponent of B is large, the output of the circuit 3 is negative. Thus the value with which two complements of the arithmetic result are obtained is supplied to a right shift register 5' in the form of a shift degree. The output of the register 5' is gated by an OR circuit 7, and a bypass output is outputted from an OR circuit 8 and supplied to an addition/subtraction circuit of a mantissa part. This action is reversed when the exponent of A is large.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a floating point addition/subtraction method for two floating point data consisting of a mantissa part, an exponent part, and a sign part.
In particular, the present invention relates to a right shift method for digit alignment of the mantissa part of floating point data, which is performed prior to algebraic addition and subtraction of the mantissa part.

Generally, when adding or subtracting two pieces of floating point data consisting of a mantissa part, an exponent part, and a sign part, the operations are performed in the order of digit alignment, algebraic addition of the mantissa parts, and normalization.

To do this, first the exponents of two floating point data are compared, and the mantissa of the data with the smaller exponent is shifted to the right. For example, each time the exponent is shifted by one digit as a hexadecimal number, Increase by 1 until the two index parts lose once.
The process of continuing the right shift described above is executed.

In the above digit alignment operation, if the exponent parts match -
Then, the mantissa parts are added algebraically and the intermediate sum is output.

At this time, if there is a carry as a result of the addition of the mantissa part, the intermediate sum is shifted to the right, the carry becomes a superposition, and 1 is added to the exponent part.

In the above floating point data addition/subtraction method,
If you try to find the shift amount of a two-note right shift operation on the mantissa, which continues until the exponent part of two floating-point data fails, it is more A method for simply determining the above shift amount has been awaited.

[Conventional technology]

FIG. 2 shows a conventional method for calculating shift (shift) ffl for digit alignment.

In this figure, 1 is the operand register A, 11 is the mantissa part of the operand data A, 12 is the exponent part of the operand data A, and 2 is the operand register B.

21 is a mantissa part of operand data B, 22 is an exponent part of operand data B, 3 is an arithmetic circuit that performs "exponent of A - exponent of B", 4 is an arithmetic circuit that performs "exponent of B - exponent of A", 5.6 is a right shifter, 7.8 is an OR circuit, and when the magnitude determination (positive, negative) signal of the arithmetic circuit is negative, it outputs the output of the right shifters 5 and 6, and when it is positive, it outputs the bypass output. Configured to gate.

Now, two floating point data (operand data) A,
When B is placed in each operand register △1° operand register B2, each exponent part 12.2
In the arithmetic circuit 3, "the exponent of .DELTA.-the exponent of B" and in the arithmetic circuit 4, "the exponent of B-the exponent of A" are simultaneously calculated by '6'.

If the exponent to the floating point data is large, the output of the arithmetic circuit 3 (i.e., "the exponent of A - the exponent of B") will be positive, and the output of the arithmetic circuit 4 (i.e., "the exponent of B -") will be positive. index”)
is negative, so the output value of the arithmetic circuit 3 is input to the shifter 6 as the right shift i of the floating point data B, the output of the shifter 6 is input to the OR circuit 8, and the bypass output is input to the OR circuit 7. The signal is gated and output to a mantissa addition/subtraction circuit (not shown).

Similarly, when the exponent of floating point data B is large, the output of the arithmetic circuit 4 (i.e., "the exponent of B - the exponent of A") is positive, and the output of the arithmetic circuit 3 (i.e., "the exponent of A") is positive. Since the exponent "-B") is negative, the output value of the arithmetic circuit 4 is input to the shifter 5 as the right shift amount to floating point data, and the output of the shifter 5 is input to the OR circuit 7. The bypass outputs are respectively gated and output to a mantissa adder/subtractor circuit (not shown).

[Problem that the invention seeks to solve]

In this way, in the conventional method, it is necessary to prepare two arithmetic circuits to calculate the shift amount by comparing the magnitudes of the exponent parts of two floating point data A and B, and to adjust the digits of the mantissa parts. There was a problem in that the right shift mechanism for this purpose became complicated.

In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a method for comparing the exponent parts of two floating point data A and B and calculating the shift amount using one arithmetic circuit. .

[Means for solving problems]

The purpose of this is to provide only one arithmetic circuit that compares the exponent parts of the above two floating point data A and B in order to align the digits of the mantissa part prior to algebraic addition and subtraction of the mantissa part. The circuit calculates the exponent of Δ - the exponent of B, and if the exponent to is larger than the exponent of B, the above calculation result is shifted as a right shift l of the mantissa part of the floating point data B, and the floating point data The mantissa part of A is not shifted, and if the exponent of B is larger than the exponent of B in the above calculation result, for example, the two's complement of the calculation result is
This is achieved by the floating point addition/subtraction method of the present invention, which controls the mantissa part of floating point data to be shifted as ffl, and the mantissa part of floating point data B is not shifted, and the mantissa parts are aligned. .

[Effect]

That is, according to the present invention, one arithmetic circuit calculates "the exponent of A - the exponent of B", and if the exponent to the floating point data is large, then ij)1. (Shift the result as the right shift amount of floating point data B, and
is not shifted, and if the exponent of floating point data B is large, for example, the value obtained by taking the two's complement of the above calculation result is shifted as the right shift amount to the floating small fault data,
? Since the 7j floating point data B is not shifted, there is an effect that only one arithmetic circuit is required for the magnitude ratio of the exponents of the two floating point data Δ and B.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the same symbols as in FIG. The exponent parts of the two floating point data A and B are compared by calculating "the exponent of A - the exponent of B" in the arithmetic circuit 3, and when the exponent of the floating point data B is large, for example, the exponent part of the arithmetic circuit 3 The feature is that the two's complement of the operation result is used as the shift amount of the operand data A. Also, for the OR circuits 7 and 8, depending on whether the output of the operation circuit 3 is positive or negative, if positive: OR The circuit 7 is configured to gate the bypass output, and the OR circuit 8 is configured to gate the output of the shifter 6.

1'1. In this case, the OR circuit 7 is configured to gate the output of the shifter 5', and the OR concave j1°()8 is configured to gate the bypass output.

Now, for operand data A, [3, A = 0.5
Assuming 670×102 B = 0.7890 x 103 and considering the addition process of A+8, first, for the operation “Exponent of A − Exponent of B” performed in the arithmetic circuit 3, “Exponent of A − Exponent of B” = 0010 ■-0O11(2
) = 1111 (2°. Therefore, the actual shift to m = 1111 ■ 2's complement = 00
By setting 01t2+, the mantissa of the mantissa part B to = 0. '0567+0.7890
=0.8457 can be obtained.

Therefore, the addition result of the floating point data is A +
13=0.8457X103.

The above 41τ calculation process will be explained using the example shown in FIG.
First, the above two floating point data Δ and B are respectively stored in operand registers A1. The number is placed in operand register B2.

For each exponent part 12.22 of the floating point data, the arithmetic circuit 3 executes "exponent of A - exponent of B".

At this time, in the above example, since the exponent of B is large, the output of the arithmetic circuit 3 is negative, but in the present invention,
The right shifter 5' is controlled so that, for example, a value obtained by taking the two's complement of the calculation result is inputted as shift l-=.

However, since the magnitude determination output of the arithmetic circuit 3 is a negative signal, the OR circuit 7 outputs the signal from the right shifter 5'.
The output of is gated, and the OR circuit 8 outputs a bypass output (ie, the value of the mantissa part 21 of the operand register B), which is output to a mantissa addition/subtraction circuit (not shown).

In the above example, the exponent of floating point data B is larger than the exponent of floating point data, but if the exponent of floating point data is larger than the exponent of floating point data B, the above “°Δ Since the result of the calculation of ``exponent of - exponent of B'' is positive, the calculation result is input to the right shifter 6 as the shift amount for floating point data B (i.e., the value of operand register B2). S-Applicable? 5
Since the magnitude determination output of the 1j arithmetic circuit 3 is a positive signal, the OR circuit 7 gates the bypass output (that is, the value of the mantissa part 11 to the operand register), and the OR circuit 8 gates the bypass output (that is, the value of the mantissa part 11 to the operand register). FIX to gate the output of right shifter 6 and output it to the mantissa addition/subtraction circuit! jf: Yes.

In this way, in the present invention, when adding and subtracting two floating point data A and H, only one arithmetic circuit is required to compare the exponent parts of the two floating point data A and B. Addition and subtraction can be performed on the floating point data.

In the above embodiment, the shift m for the right shifter 5' was explained using a value obtained by taking the two's complement of the 6-count result (however, negative data) of the arithmetic circuit 3. , for example, 1111(2) : I digit shift 1110.21 : 2 digit shift 1101(2) 23 digit shift As shown in 8, the negative output data of the arithmetic circuit 1 circuit 3 is transferred to its blood, right 5 It goes without saying that the right thick 5' may be constructed so that a regular right shift can be performed by inputting the input ".".

〔Effect of the invention〕

As explained in detail above, the floating point addition/subtraction method of the present invention uses one arithmetic circuit to perform "exponent of A - exponent of B".
is calculated, and if the exponent to the floating point data is large, the calculation result is shifted as a right shift ■ of the floating point data B, the floating point data A is not shifted, and if the exponent of the floating point data B is large, For example, 6 above
The value obtained by taking the two's complement of the calculation result is shifted as the right shift amount to the floating point data, and the floating point data B is not shifted, so the exponent of the two floating point data △ and +3 is This has the advantage that only one arithmetic circuit is required for size comparison.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a conventional shift mechanism for digit alignment -Q. In the drawing, l is operand register A. 11 is the mantissa portion to the operand register. I2 is the exponent part of operand register A. 2 is operan l: register B. 21 is the mantissa part of operand register B. 22 is the exponent part of operand register B. 3 is an arithmetic circuit 14 that performs "exponent to ' - exponent of B" is "
17' circuit that performs 'B's exponent -'. 5.5', 6 are right shifters, 7.8 is OR circuit.

Claims (1)

[Claims] This is an addition/subtraction method for floating point data A and B, and an arithmetic circuit that compares the exponent parts of the two floating point data A and B in order to align the digits of the mantissa part prior to algebraic addition and subtraction of the mantissa part. The calculation circuit calculates "the exponent of A - the exponent of B." If the exponent of A is larger than the exponent of B, the above calculation result is applied to the right side of the mantissa part of the floating point data B. Shift as the shift amount, floating point data A
If the exponent of B is larger than the exponent of A in the above calculation result, the two's complement of the calculation result, or its equivalent, is transferred to the floating point data A.
A floating point addition/subtraction method characterized in that the mantissa part of floating point data B is shifted by the amount of shift of the mantissa part of the floating point data B, and the mantissa part of floating point data B is not shifted, and the digits of the mantissa part are aligned.