JPS6154260B2 - - Google Patents
Info
- Publication number
- JPS6154260B2 JPS6154260B2 JP54098133A JP9813379A JPS6154260B2 JP S6154260 B2 JPS6154260 B2 JP S6154260B2 JP 54098133 A JP54098133 A JP 54098133A JP 9813379 A JP9813379 A JP 9813379A JP S6154260 B2 JPS6154260 B2 JP S6154260B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- base region
- short
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 8
- 238000005259 measurement Methods 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0839—Cathode regions of thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
この発明はエミツタ領域と、このエミツタ領域
に隣接するベース領域とを短絡するためエミツタ
領域にエミツタ短絡孔を分布させている型のサイ
リスタ，トライアツク等の半導体装置製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device such as a thyristor or a triax in which emitter shorting holes are distributed in the emitter region to short-circuit an emitter region and a base region adjacent to the emitter region. .
例えばサイリスタでは、高温耐圧特性を改善
し、臨界オフ電圧上昇率dV／dtを向上させ、タ
ーンオフ時間を短縮させるために、N+エミツタ
領域（カソード領域）の一部に隣接するＰベース
領域を露出させ、オーミツク接触する電極導体で
両領域を短絡している。この構造は所謂エミツタ
短絡構造として知られている。第１図にこの一例
のサイリスタの簡略断面図を示す。P1型アノード
領域１上にN1型ベース領域２，P2型ベース領域
３が、又P2型ベース領域中にはN2型エミツタ領
域４が順次分布し、N2型エミツタ領域４にはこ
のエミツタ領域を貫通するエミツタ短絡孔５ｎが
複数個、それぞれ内部にP2型ベース領域３を案内
して分布している。そしてアノード領域表面にア
ノード電極６を、エミツタ領域表面にカソード電
極７を備えている。カソード電極７はエミツタ領
域４及びエミツタ短絡孔５ｎでP2型ベース領域の
両領域を短絡接続している。この構造により順電
流はオフ時にエミツタ領域を通らず、ベース領域
から直接外部電極に流れ、注入を抑制するために
前述の効果を奏することになる。 For example, in a thyristor, the P base region adjacent to a part of the N + emitter region (cathode region) is exposed in order to improve the high-temperature withstand voltage characteristics, increase the critical off-voltage rise rate dV/dt, and shorten the turn-off time. The two regions are short-circuited by an electrode conductor in ohmic contact. This structure is known as a so-called emitter short circuit structure. FIG. 1 shows a simplified cross-sectional view of this example of a thyristor. An N 1 type base region 2 and a P 2 type base region 3 are disposed on the P 1 type anode region 1, and an N 2 type emitter region 4 is sequentially distributed in the P 2 type base region. A plurality of emitter shorting holes 5n passing through this emitter region are distributed, each guiding a P2 type base region 3 inside. An anode electrode 6 is provided on the surface of the anode region, and a cathode electrode 7 is provided on the surface of the emitter region. The cathode electrode 7 short-circuits both regions of the P2 type base region through the emitter region 4 and the emitter short-circuit hole 5n. With this structure, the forward current does not pass through the emitter region when off, but flows directly from the base region to the external electrode, which suppresses injection, producing the above-mentioned effect.
第１図の構造で特性の良いサイリスタを形成さ
せる為には、N1型ベース領域とN2型エミツタ領
域との間にはさまれたP2型ベース領域の領域幅を
適正に設定する必要がある。この幅が広い時には
順電流通電時の電圧降下ＶFMが高くなり、又ゲー
ト点弧電流を大にして、電力損失を大にし且つサ
イリスタ感度を低下させる欠点を招く。又この幅
が反対に狭いときには順阻止電圧を低下しdV／
dT耐量を低下して、サイリスタの誤動作を招
く。この為P2型ベース領域幅を適正に管理する必
要から、拡散ウエハの断面を露出させて、拡散深
さを測定することが行われている。この手段は破
壊検査であるから、ウエハの全数について行うこ
とは出来ず、ロツト内の１〜２枚について代表的
に測定してロツト評価にあてゝいる。 In order to form a thyristor with good characteristics using the structure shown in Figure 1, it is necessary to appropriately set the width of the P2 type base region sandwiched between the N1 type base region and the N2 type emitter region. There is. When this width is wide, the voltage drop V FM when forward current is applied increases, and the gate firing current increases, resulting in disadvantages of increasing power loss and reducing thyristor sensitivity. On the other hand, when this width is narrow, the forward blocking voltage is reduced and dV/
This will reduce the dT tolerance and cause thyristor malfunction. For this reason, since it is necessary to appropriately manage the width of the P2 type base region, the diffusion depth is measured by exposing a cross section of the diffusion wafer. Since this method is a destructive test, it cannot be performed on all the wafers, but one or two wafers in the lot are typically measured for evaluation of the lot.
このようにサイリスタは電気的特性の向上を要
請され、理論設計値或いは相関データによる定数
設定にもとずいて製造工程での條件許容範囲が狭
められてきている。工程條件が狭められるにつれ
てロツト内の所望電気的特性は当然或る値に集中
するようになる。従つて万一條件設定を誤まると
ロツトのウエハ全数が不良品になる事態が起きか
ねない。この意味で半成品からその時点での特性
情報を正確に得て次工程の條件設定に活用させる
ことが必要となる。 As described above, thyristors are required to have improved electrical characteristics, and the allowable range of conditions in the manufacturing process is being narrowed based on constant settings based on theoretical design values or correlation data. As the process conditions become narrower, the desired electrical characteristics within the lot naturally become concentrated at a certain value. Therefore, if the conditions are incorrectly set, all of the wafers in the lot may be defective. In this sense, it is necessary to accurately obtain characteristic information from semi-finished products at that point in time and use it to set conditions for the next process.
製品特性を良好にし、ロツト内ウエハの全数不
良を招来しないように工程を管理するためにはウ
エハをサンプリングし、特性を破壊検査するより
も、非破壊で全数検査出来ることが好ましい。こ
の発明はこのような要請にこたえてなされたもの
であつて、エミツタ領域とこのエミツタ領域に隣
接するベース領域とを短絡するためにエミツタ領
域を貫通するようにベース領域を分布させている
エミツタ短絡孔の、何れか二個に設けられた電極
間で抵抗値を測定し、測定された抵抗値により引
き続く工程を制御する半導体装置製造方法にあ
る。 In order to improve the product characteristics and control the process so that all wafers in a lot are not defective, it is preferable to conduct a non-destructive inspection of all wafers rather than sampling the wafers and destructively inspecting the characteristics. The present invention has been made in response to such demands, and provides an emitter short circuit in which the base region is distributed so as to penetrate through the emitter region in order to short-circuit the emitter region and the base region adjacent to the emitter region. A semiconductor device manufacturing method includes measuring a resistance value between electrodes provided in any two holes, and controlling subsequent steps based on the measured resistance value.
この発明で得られる半導体装置は、エミツタ短
絡孔を分布させているサイリスタ，トライアツク
などの半導体装置である。又エミツタ短絡孔が、
エミツタ領域隣接のベース領域に係る抵抗値測定
に際して露出している場合には、この発明の２
項、即ち関与する少なくとも二個のエミツタ短絡
孔を他のエミツタ短絡孔よりも径大に設けておく
規定に従うと良い。短絡孔周辺のエミツタ領域に
測定用電極をはみ出させないように出来るからで
ある。この配慮は抵抗値測定に際して短絡孔が、
ウエハ表面の酸化膜に開孔している場合には不要
である。低抗値測定にあてて短絡孔に設ける電極
はインジウムガリウムで形成するとよい。インジ
ウムガリウムは常温で液状で塗布，払拭容易であ
つて、使用を容易にしオーミツク接続を確実にす
る。電圧印加用電極は測定用電極で兼ねてよく、
別の短絡孔に設けたものとしてもよい。 The semiconductor device obtained by the present invention is a semiconductor device such as a thyristor or a triac in which emitter shorting holes are distributed. Also, the emitsuta short circuit hole is
If the base region adjacent to the emitter region is exposed when measuring the resistance value, the second aspect of the present invention
In other words, it is preferable to follow the rule that at least two emitter short-circuit holes involved are provided with a larger diameter than other emitter short-circuit holes. This is because the measurement electrode can be prevented from protruding into the emitter region around the shunt hole. This consideration is due to the fact that the short circuit hole is
This is not necessary when holes are formed in the oxide film on the wafer surface. The electrode provided in the shorting hole for low resistance measurement is preferably made of indium gallium. Indium gallium is liquid at room temperature and is easy to apply and wipe off, making it easy to use and ensuring ohmic connections. The electrode for voltage application may also serve as the electrode for measurement,
It may be provided in another short circuit hole.
以下実施例について述べる。 Examples will be described below.
(1) 第２図はサイリスタの半成品について示す簡
略断面図である。P1型アノード領域１上にN1
型ベース領域２，P2型ベース領域３が、P2型ベ
ース領域中にはN2型エミツタ領域４が分布
し、又N2型エミツタ領域には、このエミツタ
領域を貫通するエミツタ短絡孔５ｎが、第１図
例のエミツタ短絡孔５ｎと同様に分布している
点で第１図例と変らない。第２図例が第１図例
と相違する点は、短絡孔５ｎの他にP2型ベース
領域にかゝる抵抗測定にあてられ測定用電極が
設けられているエミツタ短絡孔５ｌ，５ｍを少
くとも二個備えていることである。従つてこの
第２図サイリスタは、この断面を呈するまでの
製造工程を経過した時点で、エミツタ短絡孔５
ｌ，５ｍに設けられた電極９ｌ，９ｍ間に電源
１０を挿入して電圧を印加し、抵抗値を測定す
ることが出来る。印加された電圧によつて第２
図で矢印方向に電流が流れ、このP2型ベース領
域内通路の抵抗分ＲPにより電圧降下が起こ
る。この抵抗分ＲPは、P2型ベース領域の不純
物濃度に関係し、N1型ベース領域に接近する
ほど大となる。従つてN2型エミツタ領域が深
くあるほどＲPは大になることになる。例えば
この例のサイリスタで、N2型エミツタ領域４
を形成するためにP2型ベース領域３の表面にリ
ンのマスク堆積を施し、リン源を除いてスラン
ピングを行い、酸化膜を除去してちようど第２
図形状を呈したとする。マスク堆積に際してマ
スク下方に形成されたエミツタ短絡孔５ｌ，５
ｍにインジウムガリウム電極９ｌ，９ｍを作
り、直流電源を接続して抵抗ＲPを測定する。
ＲPが所望値に達するまで引き続く以後のガリ
ウムスキン拡散工程でリンのスランピングを制
御追加する。この結果抵抗ＲPの過不足が終極
的に解消される。(1) Figure 2 is a simplified sectional view showing a semi-finished product of a thyristor. N 1 on P 1 type anode region 1
A type base region 2, a P2 type base region 3 are distributed, an N2 type emitter region 4 is distributed in the P2 type base region, and an emitter shorting hole 5n is provided in the N2 type emitter region passing through this emitter region. However, they are the same as the example in FIG. 1 in that they are distributed in the same way as the emitter shorting holes 5n in the example in FIG. The difference between the example in FIG. 2 and the example in FIG. 1 is that in addition to the shorting hole 5n, there are emitter shorting holes 5l and 5m, which are used to measure the resistance of the P2 type base region and are provided with measurement electrodes. It is important to have at least two of them. Therefore, the thyristor shown in FIG.
A power source 10 is inserted between the electrodes 9l and 9m provided at the electrodes 9l and 5m, a voltage is applied, and the resistance value can be measured. The second voltage is determined by the applied voltage.
In the figure, a current flows in the direction of the arrow, and a voltage drop occurs due to the resistance R P of the path in the P 2 type base region. This resistance R P is related to the impurity concentration of the P 2 type base region, and increases as it approaches the N 1 type base region. Therefore, the deeper the N2 type emitter region is, the larger R P becomes. For example, in this example thyristor, the N2 type emitter region 4
In order to form a P 2 type base region 3, a mask of phosphorus is deposited on the surface of the P 2 type base region 3, slumping is performed by removing the phosphorus source, and the oxide film is removed.
Suppose that it has a figure shape. Emitter short-circuit holes 5l, 5 formed below the mask during mask deposition
Make indium gallium electrodes 9l and 9m on m, connect a DC power supply, and measure the resistance R P.
Subsequent gallium skin diffusion steps add controlled phosphorus slumping until R P reaches the desired value. As a result, the excess or deficiency of the resistor R P is finally resolved.
エミツタ短絡孔の直径は0.2〜0.4mmの範囲で
サイリスタ特性を良好にする。第２図例ではエ
ミツタ短絡孔５ｎの直径はこの理由でこの範囲
に開孔されている。抵抗値測定に用いられる短
絡孔５ｌ及び５ｍは、この径では、電極として
インジウムガリウムを塗布する際、孔径をはみ
出して不都合である。従つて少くとも１〜２mm
径大に設けてある。 The diameter of the emitter short circuit hole should be in the range of 0.2 to 0.4 mm to improve the thyristor characteristics. In the example shown in FIG. 2, the diameter of the emitter shorting hole 5n is set within this range for this reason. With this diameter, the shorting holes 5l and 5m used for resistance measurement are inconvenient because they protrude beyond the hole diameter when indium gallium is applied as an electrode. Therefore, at least 1 to 2 mm
It is provided with a large diameter.
(2) 第３図は第２図例に比較してP2型ベース領域
３の表面が、N2型エミツタ領域表面とともに
酸化膜１１で被覆されている点のみを異にして
いる。従つてこの例では抵抗値測定に用いる短
絡孔５ｌ，５ｍは、この用途にない他の短絡孔
５ｎと孔径を等しくして設けられても、酸化膜
開孔に際して注意すれば電極をN2型エミツタ
領域に接触させることはない。(2) The only difference in FIG. 3 from the example in FIG. 2 is that the surface of the P 2 type base region 3 is covered with an oxide film 11 together with the surface of the N 2 type emitter region. Therefore, in this example, even if the shorting holes 5l and 5m used for resistance measurement are provided with the same diameter as the other shorting holes 5n that are not used for this purpose, if care is taken when opening the oxide film, the electrodes can be made of N2 type. It does not touch the emitter area.
このようなこの発明の製造方法によるとエミツ
タ短絡孔に設けられた電極により測定された抵抗
値により次工程を管理出来るため、例えば前述の
例でP2型ベース領域幅を適正に得させる。従つて
電力損失を大にし又はサイリスタ感度を低下させ
る如き過不足を招くことがない。また測定用のエ
ミツタ短絡孔を他のエミツタ短絡孔よりも径大に
設けることは抵抗値を測定する上で、エミツタ短
絡孔内の縦方向の抵抗値を減少させることが可能
であり、抵抗値ＲPの精度を向上させる。 According to the manufacturing method of the present invention, the next process can be controlled based on the resistance value measured by the electrode provided in the emitter shorting hole, so that, for example, in the above-mentioned example, the width of the P2 type base region can be appropriately obtained. Therefore, there will be no excess or deficiency that would increase power loss or reduce thyristor sensitivity. In addition, by providing the emitter short circuit hole for measurement with a larger diameter than other emitter short circuit holes, it is possible to reduce the vertical resistance value in the emitter short circuit hole when measuring the resistance value, and the resistance value Improve the accuracy of R P.
第１図はエミツタ短絡型サイリスタ断面図、第
２図及び第３図はこの発明の実施例方法に係るサ
イリスタ半成品断面図である。
第２図及び第３図で４……エミツタ領域、３…
…隣接するベース領域、５ｍ，５ｌ……エミツタ
短絡孔、９ｍ，９ｌ……電極。
FIG. 1 is a sectional view of a short-circuited emitter type thyristor, and FIGS. 2 and 3 are sectional views of a semifinished thyristor according to an embodiment of the present invention. In Figures 2 and 3, 4...emitter area, 3...
...Adjacent base area, 5m, 5l... Emitter short circuit hole, 9m, 9l... electrode.
Claims (1)
ベース領域とを短絡するためにエミツタ領域を貫
通するようにベース領域を分布させているエミツ
タ短絡孔の、何れか二個に設けられた電極間で抵
抗値を測定し、測定された抵抗値により引き続く
工程を制御することを特徴とする半導体装置製造
方法。 ２ エミツタ短絡孔の抵抗値測定に用いられる少
くとも二個が、他の短絡孔に比較して径大に設け
られているものであることを特徴とする特許請求
の範囲第１項に記載の半導体装置製造方法。[Claims] 1. In order to short-circuit an emitter region and a base region adjacent to the emitter region, an emitter short-circuit hole is provided in any two of the emitter short-circuit holes in which the base region is distributed so as to penetrate the emitter region. A method for manufacturing a semiconductor device, comprising: measuring a resistance value between electrodes, and controlling subsequent steps based on the measured resistance value. 2. Claim 1, characterized in that at least two of the emitter shorting holes used for measuring the resistance value are provided with a larger diameter than other shorting holes. Semiconductor device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9813379A JPS5623777A (en) | 1979-08-02 | 1979-08-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9813379A JPS5623777A (en) | 1979-08-02 | 1979-08-02 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5623777A JPS5623777A (en) | 1981-03-06 |
| JPS6154260B2 true JPS6154260B2 (en) | 1986-11-21 |
Family
ID=14211742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9813379A Granted JPS5623777A (en) | 1979-08-02 | 1979-08-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5623777A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5482147A (en) * | 1977-12-14 | 1979-06-30 | Yagi Antenna | Directional antenna feeder |
-
1979
- 1979-08-02 JP JP9813379A patent/JPS5623777A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5482147A (en) * | 1977-12-14 | 1979-06-30 | Yagi Antenna | Directional antenna feeder |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5623777A (en) | 1981-03-06 |
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