JPS6154093A - Memory device - Google Patents

Abstract

PURPOSE:To decrease the number of external terminals of a memory device by decoding with a decoder an assembly of a signal inputted from an external connecting terminal and outputting a necessary control signal. CONSTITUTION:The assembling of an input signal from three terminals T11- T13 installed besides a terminal T1 for data signal output and terminals T8 and T9 for electric power source is decoded by a decoder 9. A read signal is outputted from the terminal Q'0 of the decoder 9, a write signal is outputted from Q'1, an address resetting signal is outputted from Q'2 and an address increment signal is outputted from Q'3, and a memory element 4 is written. On the other hand, comparing with the case when an element 4 is read by an input from terminals T11 and T12, and an assembling signal is not used when all outputs of these terminals Q'0-Q'3 are L, the number of external terminals of a memory device is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a removable storage device used as an auxiliary external memory in desktop electronic computers and various information processing devices.

[Prior art]

An example of a conventional storage device will be described with reference to FIGS. 3 and 4. In FIG. 3, 1 is an address setter using a ]] bit binary counter, and when the terminal R8T is set to a high level potential (hereinafter referred to as "H"), the terminal Qo=
All Qxo are at low level potential (hereinafter referred to as "L").

), each time the terminal CL is changed from @H" to "L", the count value (which becomes the address of the memory element described later) set by the terminals Qo to Qlo is updated one by one. 2 is a serial number. This is an 8-bit shift register that outputs the data input to the A' parallel.When the terminal OE is "H", the data signal input serially from the terminal SI is read by the rising edge of the clock signal input to the terminal CL. Temporarily store it and set it to terminals Qo to Q7.
When is 'L#, terminal Qo=Qy becomes a high impedance state. 3 reads the data signal that is input in parallel to terminals 1 to 8 by setting the terminal P/S to "H", and when the terminal P/S is "L#", the clock is input to the terminal CL. Terminal Q is synchronized with the rising edge of the signal.
This is a shift register that serially outputs the data signal. 4 is static RAM with 0MO8 structure
(Random Access Memory) etc., which has a storage capacity of 2 kilobytes, and the address terminals Ao = Ato are respectively connected to the terminals Qo = Qto of the address setter 1, and the data terminals Do-Dt are respectively connected to the terminals Qo = of the shift register 2. Qy and is connected to terminals 1 to 8 of the shift register 3. This memory element 4 stores the data set at the terminals Do-D7 at the address set by the terminals AO-Alo when the terminal OE is "H", the terminal WE is "L", and the terminal C8 is "H". Also, terminal OE is “H”, terminal WE is H#, and terminal C8
When is "H", the data stored at the address set by the terminals AO to A40 is outputted from the terminals D0 to D7. Tt to T9 are external connection terminals for connecting this storage device to various information processing devices that use it as auxiliary memory, etc. The terminal Tl is connected to the terminal Q8 of the shift register 3 and outputs a data signal, and the terminal T2 is connected to each terminal. Terminal CLK of shift register 2.3 is connected to input a clock signal, terminal T3 is connected to terminal SIK of shift register 2 to input a data signal, and terminal T4 is connected to terminal OE of shift register 2 and memory register 4. The terminal OB is connected to one terminal of the capacitor 5a constituting the differentiating circuit 5 and one input terminal of the Nant gate 6 to input a read signal, and the terminal Ts is connected to the terminal WE of the storage element 4 and the other terminal of the Nant gate 6. Connect to the input terminal to input the light signal. Terminal T6 is connected to terminal R8T of address setter 1 to input an address reset signal, and terminal T7 is also connected to terminal CL.
is connected to input the address increment signal.

Terminals Ta and Ts are power supply terminals.

Also, the output of the differentiating circuit 5 is input to the inperturf, and the output of the inperturf is input to the terminal P/S of the shift register 3.
is input. 8 is a register for input delta fi or pulldown, and 5b is a register for the differentiating circuit 5.

Note that power for the memory element 4 is supplied by a built-in battery (not shown) to back up the memory, and power for other elements is supplied from terminals Ts and Ts.

The operation of the conventional device having the above configuration will be explained with reference to FIG.

FIG. 4 shows each terminal T1 to T7. C8, shows the voltage waveform of P/S. - As an example, this storage device is connected to each SE II information processing device (not shown) K! Next, the operation of writing data from this information processing device will be explained. First, from terminal T6 at time 1. An address reset signal that remains "H" for a predetermined period of time is input to the address reset signal. As a result, all the terminals Q and o=Qto of the address setter l are set to L''. Next, from time t2, the clock signal and the
Input the pit data signal. As a result, the data signal input to the terminal Qo=Qy of the shift register 2 is set. After that, at time t3, the signal is "L" from the terminal T5 for a predetermined period of time.
” When a write signal is input, the terminal C of the memory element 4
8 is simultaneously held at "H#" for a predetermined period of time, whereby the data set at the terminal QoQy of the shift register 2 is written to the address set at that time.

Next, in order to confirm whether or not the first written data has been correctly stored in the storage element 4, the external information processing device performs an operation to read the data at the previously set address. First, at time t4, a read signal that remains "H" for a predetermined period of time is input from terminal T4.

For this, write it down! At the same time, the terminal C8 of the element 4 remains ``H'' for a fixed period of time, and a pulse as shown in the figure is input to the terminal P/S of the shift register 3 at 9 o'clock when the read signal rises. Therefore, the corresponding data in the storage element 4 is input to the shift register 3 at the A' parallel at time t4.

Thereafter, a clock signal is input from the terminal T, and the data read by the shift register 3 is serially output from the terminal Tr. The external information processing device compares this read data with the first 11 input data, and if they do not match, it issues an alarm, but if they match, it updates the address and uses the next one. Write data. To update the address, a predetermined period of time is required from terminal T7 at time ts.
Input an address increment signal that goes low.

~Qlo An output is placed that specifies the K next address. From now on, data will be written each time the address is updated in this way.

[Problem that the invention seeks to solve]

Although conventional storage devices reduce the number of external connection terminals by serially transmitting data as described above, they still require nine terminals including the power supply terminals Ts and Ts, which is a large number of terminals. (reliability during connection decreased)
There were problems such as the connector becoming larger. Furthermore, if a microprocessor is used in the data transmission circuit, the number of external connection terminals can be easily reduced, but a dedicated program must be developed and measures against runaway are also required.

Therefore, the present invention has been made to solve the above-mentioned problems, and by using a well-known logic circuit without using a microprocessor, and by devising input signals from external connection terminals, The purpose is to reduce the number of external connection terminals.

[Means for solving problems]

In addition to the two power supply terminals Ta and Ts and a data signal output terminal (fourth terminal) Ts, the present invention provides three external connection terminals, first, second, and third. A decoder is provided that decodes the combination of signals input from the connection terminals and outputs a read signal, write signal, address reset signal, and address increment signal.

[Effect]

The first . Second. It decodes the combination of signals input from the third terminal and outputs a read signal, write signal, address reset signal and address increment signal, and when no signal is output, the first... A data signal input from one of the second terminals is serially input to the shift register 2 in synchronization with a clock signal input from the other terminal. Also, 1st. Second
The data signal temporarily stored in the shift register 3 is transferred to the terminal T in synchronization with the clock signal input from one terminal of the terminal.
sl) Output serially from 1 to 1.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In Fig. 1, Tl1-Tls are external connection terminals, respectively, and 9 is any one of the four output terminals Qo = Qs for binary input of two terminals A and B when terminal E is @L#. If the decoder is capable of selecting , and the terminal E is @H'', the terminal Qo=Q3 is set to "H". This input/output relationship is shown in the table below.

East is H or L. Terminal Tll is connected to terminal A of decoder 9 and terminal SI of shift register 2, terminal Tsz is connected to terminal B of decoder 9 and terminal CLK of each shift register 2 and 3, and terminal T1z is connected to terminal E of decoder 9. are connected to each other.

The terminal Qo that outputs the read signal of the decoder 9 is connected to the terminal T4 in FIG. Connected to one input terminal. The terminal q that also outputs the write signal is the terminal TsK in Fig. 3.
A corresponding shift is connected to the terminal WE of the storage element 4 and the other input terminal of the Nant gate 6. Similarly, each terminal that outputs an address reset signal corresponds to terminal T6 in FIG.
Connected to the inverter 100 input terminal, the inverter 10
The output terminal of the address setter 1 is connected to the terminal R8TK of the address setter 1. Similarly, the terminals outputting the address increment signal correspond to the terminal T7 in FIG. 3, and are connected to the terminal CL of the address setter 1. Other connections are the same as in FIG.

Next, the operation of the above configuration will be explained using the time chart shown in FIG. Tl+ Tll~T13 + Qo −
Q3 indicates the voltage waveform of the external connection terminal with the same sign and each terminal of the decoder 9. As an example of the operation, the operation of writing data from an external information processing device will be described similarly to the description of the conventional device.

First, at time t6, "L" and 'H' are input from terminals T1+1T12, respectively, and at time 11, "L" is input from terminal T13 for a predetermined period of time. For this, decoder 9
terminal outputs an address reset signal for a predetermined period of time ゛L#, address setter 1 is reset, and all its terminals Q
o=Qlo is set to 1L''. Next, from time t2, a data signal and a clock signal are inputted from the terminals Tlt+T+z, respectively, and the connecting terminals Tst and T12 are input.
are set to "L" and "L", respectively, and "L" is input from terminal T13 for a predetermined time at the time of day. As a result, the terminal Q1 of the decoder 9 outputs a write signal for a predetermined time "'L#", and in the primary period in which data is written into the memory element 4, the terminals Tll and Txz are both set to K"L", and at time t4 Then input a predetermined time 1L'' from the terminal T13. Accordingly, the terminals of the decoder 9 output a read signal of ``L'' for a predetermined period of time, and data is read from the memory element 4.
It is temporarily stored in the shift register 3. After that, terminal T1
It inputs a clock signal from terminal 2 and outputs data from terminal TI. Next, at time t7, both terminals Tl and TI2 are set to "L", and at time tls, "L" is input from terminal T13 for a predetermined period of time. As a result, the terminals of the decoder 9 output an address increment signal of "L" for a predetermined period of time, and the set address of the address setter 1 is updated. Thereafter, data is written into the storage element 4 every time the address is updated.

〔Effect of the invention〕

As described above, in the present invention, four external connection terminals are provided for signal transmission, and a decoder decodes the combination of signals input from the first to third terminals to generate a read signal, a write signal, and an address signal. It outputs a reset signal and an address increment signal, and when this decoder does not output any of these four signals, the first . A data signal is serially inputted from one of the second terminals, and inputted to the first shift register in synchronization with a clock signal VC inputted from the other terminal. The configuration is such that the data signal temporarily stored in the second shift register is output serially from the fourth terminal in synchronization with the clock signal input from one terminal of the second terminal, and is different from the conventional external connection terminal. The number can be reduced.

[Brief explanation of the drawing]

1 and 2 are a circuit diagram and an operation explanatory diagram of a storage device according to the present invention, respectively, and FIGS. 3 and 4 are a circuit diagram and an operation explanatory diagram of a conventional device. Setting device, 2... First shift register, 3... Second shift register, 4... Storage element, 9... Decoder, Tl... Fourth terminal, Tll.
...First terminal, Tsz...Second terminal, T13...
・Third terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] a decoder that decodes a combination of signals input from the first, second, and third terminals and outputs a read signal, a write signal, an address reset signal, and an address increment signal; an address setter that updates the address one address at a time each time the address increment signal is input, and outputs the signal; and a data signal that is serially input from one of the first and second terminals. a first shift register that reads and temporarily stores data in synchronization with a clock signal input from the other side; and a first shift register that reads and temporarily stores data in synchronization with a clock signal inputted from the other side, and stores the data temporarily stored in the first shift register at an address specified by an address setter in parallel in accordance with the write signal. A memory element that inputs and stores the data and outputs the data stored at the address designated by the address setter in parallel in accordance with the read signal, and a memory element that temporarily stores the data signal from this memory element and 1. A storage device comprising a second shift register that serially outputs the data signal from a fourth terminal in synchronization with a clock signal input from one of the first and second terminals.