JPS6153757A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent misoperation of LSI by dividing power supply lines for output buffers in different timings in view of supplying the power supply voltages. CONSTITUTION:The individual power supply pads 2a, 2b are respectively provided in accordane with the output buffers 1a1,1a2,..., 1an which operate in synchronization with the clock phi1 and the output buffers 1b1,..., 1bm which operate in synchronization with the clock phi2 in different timing from the clock phi1 or not synchronized with the clock. simultaneously, a power supply voltage VSS is supplied through the different power supply lins 3a, 3b extended from the pad 2a, 2b. Here, if noise n' is applied on the output An of buffer 1an due to the influence of change in output of the output buffers 1a1-1a(n-1), such noise n' is generated at the timing T1 which is different from the timing T2 in which the outputs of 1a1,..., 1an are stabilized. Therefore, there is no fear that an erroneous output signal is latched.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to the formation of power supply wiring in a semiconductor integrated circuit device.
This invention relates to a technique that is effective for forming power supply wiring to output buffers in I (large-scale integrated circuits).

[Background Art] Conventionally, the power supply wiring from the power supply pad 2 to the output buffer in an LSI is generally performed by a common power supply wiring 3 as shown in FIG. 2 in many cases. However, if the power supply wiring method described above is applied to a logic LSI having a large number of output buffers, such as a CRT controller, for example, as shown in FIG. Output A1~A
When n operates so as to change from a high level to a low level all at once as shown in Figure 3, a large transient current flows through the power supply wiring 3, and the impedance component of the power supply wiring 3 causes the power supply wiring 3 to become common. , another output buffer 1 that operates in synchronization with a clock φ2 having a different timing.
The low level of output B of b rises momentarily and noise n is added. As a result, there is a risk that the circuit receiving the output B of the output buffer 1b may malfunction or may latch incorrect data.

By the way, as a method for preventing malfunctions due to power supply noise between circuits that share a common power supply wiring, an invention has been proposed in which power supply voltage is supplied by drawing out separate power supply wiring from the power supply pad for each circuit block. (For example, Japanese Patent Application No. 59-38519).

However, these configurations are characterized by dividing the wiring depending on the magnitude of current consumption, and are not effective against output buffer noise.

[Object of the Invention] An object of the present invention is to provide a power supply wiring system that can prevent malfunction of an LSI by making it difficult for the operation of one output buffer to generate noise in the output signal of another output buffer. It's about doing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, the output signals of an LSI are not all taken in by other LSIs at the same timing, and if there is no noise when the output signal is launched, even if there is noise at other times, it will not cause malfunction of other LSIs. By focusing on the fact that the power supply voltage is not caused by dividing the power supply wiring for each output buffer with different timing and supplying the power supply voltage, it is possible to solve the problem of how to output a certain timing when one output signal is latched. This achieves the above object of preventing malfunction of the LSI by preventing noise from being generated due to changes in the output of the output buffer at different timings.

[Example 1] Figure 1 shows how the present invention is applied to the output buffer of an LSI by applying
The basic configuration when applied to wiring for supplying ss is shown.

In this embodiment, a plurality of output buffers la1, 1a2 . Separate power supply pads 2a and 2b are provided according to the output buffers lb and 1bm, which are operated in synchronization with the clock φ2 having a timing different from the clock φ1, or not synchronized with the clock at all, and Separate power supply wiring 3a, 3b drawn out from the power supply pads 2a, 2b
A power supply voltage Vss, such as a ground potential, is supplied through the terminal.

According to the above wiring system, for example, as shown in FIG.
Only the output An of LAN among LAN remains at low level and does not change, and the other output buffers 771a1-1a (n
Suppose that the outputs A1 to A(n-1) of t) all change from high level to low level at the same time, causing a large transient current to flow through the power supply wiring 3a. Then, the potential of the power supply voltage Vss rises due to this transient current, and the output Banoff 7
Noise n appears at the output An' of 1an. Therefore, the outputs A1 to A of these output buffers lal to lan
In the circuit receiving n, the outputs A1 to An are output at a timing shown by T2, when the outputs of the output buffers la1 to 1an become stable, a little later than the timing of the change (rising in the embodiment) of the normal clock φ1. It is often made to latch. Therefore, if output buffer 1a
The output An is affected by the output change of 1 to 1a (n-1).
Even if a noise n' is superimposed on the signal, since the noise n' occurs at a timing T1 different from the timing T2, there is no possibility that an erroneous output signal will be latched.

On the other hand, an LS to which the conventional wiring method is applied as shown in Figure 2
In I, the output B of the output buffer 1b has different operation timing due to the change in the output of the output buffers 1a1 to fan.
Noise n is generated.

Therefore, if the latch timing of this output B matches the change timing T1 of the output buffers A1 to An,
According to the wiring method of the above embodiment, the output buffers la, ~1an Since the power supply wiring for and 1b, ~1bm is separated, the outputs B1~B of output buffers 1b, ~1bm change depending on the output changes of output buffers 1a1~lan.
Since only a very small noise n'' is generated in m by the impedance component of the common power supply pin, for example, erroneous data will not be latched even if output B is latched at timing T1. Further, even if there is a circuit that receives the output B and performs latching, there is no risk of erroneously performing latching due to small noise n''.

Note that, as can be seen from the above description, the best way to divide the power supply wiring is to divide it into output buffers whose outputs are latched at different timings or whose outputs are operated at different timings.

However, output buffers whose outputs are usually latched or operated at different timings are often operated using signals (clocks) at different timings, so they are operated using clocks with different timings as in the above embodiment. The power supply wiring can be divided into the output buffer and the output buffer.

In this way, by separating the power supply wiring for each output buffer with different timing, malfunctions can be reliably prevented.

Note that if there are three or more types of output buffer groups with different output timings, the power supply wiring may be divided accordingly.

Next, as a more specific example, a graphic display system 1 using a CRT display device according to the present invention will be described.
A description will be given of how to divide the power supply wiring when applied to an ACRTC (at-burnest CRT controller) LSI constituting the present invention.

FIG. 5 shows a block diagram of the ACRTC. The ACRTC of this embodiment includes a system bus interface circuit 11 that interfaces with a microprocessor (not shown), and a refresh memory, frame buffer, and buffer that store display image data to a CRT display device. A CRT interface circuit 12 provides an interface with an image memory (not shown) called a microprocessor, and a drawing processor 13 performs drawing processing on the image memory by interpreting commands from the microprocessor. A display processor 14 that calculates the display address of the frame buffer according to the screen format to be displayed on the CRT, and a horizontal/vertical synchronization signal H.
A timing processor 15 that generates timing signals for the display device and each circuit block in the ACRTC, such as the timing of SYNC and VSYNC1 screen division.
It is composed of. Although not particularly limited.

The drawing processor 13, display processor 14, and timing processor 15 are each independently controlled by control information written in a microprogram ROM (read-only memory) to enable parallel processing.

The ACRTC also includes a DMA control circuit 16 that generates appropriate control signals such as DREQ when performing DMA transfer with the main memory on the system side by a DMA (direct memory access) controller (not shown). , interrupt signal IR for the microprocessor
An interrupt control circuit 17 for generating Q is also provided.

The ACRTC with the above configuration has a system data bus (D.

~D,5), which are also connected to the microprocessor via a 16-bit wide frame buffer address/data bus (MAD15) and a 5-bit wide memory or raster address bus (MA16~ 1
/RAO~3 and RA4) to the frame buffer and refresh memory.

Therefore, when the ACRTC receives drawing commands and their parameters from the microprocessor, or supplies internal register information to the microprocessor, the system data bus (Do-D) is used.

5) are operated simultaneously. Also, when driving the image memory, the frame buffer address/data bus (MAD0 to MA
20 or more output buffers connected to D15) etc. are operated simultaneously.

The ACRTC has five types of clocks internally, and an output buffer on the microprocessor side,
The output buffer on the image memory side and the output buffer that outputs various control signals such as horizontal and vertical synchronization signals H3YNC and VSYNC are operated at different timings.

Therefore, in this embodiment, the output buffers in the ACRTC are divided into a group of output buffers that output onto the system data bus (Do to D15) and a frame buffer address/
data bus (MAD0-MAD1s) and memory or raster address bus (MAXe~, 9/RAo
~3 and RA4) are divided into three groups: an output buffer group for outputting on the top and an output buffer group for outputting various control signals, and a power supply pad is provided corresponding to each group.

Separate power supply lines are drawn out from each power supply pad to supply power supply voltage Vss to each output buffer.

As a result, 20 or more output buffers on the image memory interface side are operated, and even if the outputs change simultaneously, the control signal and the low level output of the output buffer on the system data bus side are prevented from rising.

In addition, in the embodiment shown in FIG. 5, DREQ, D○NE,
IRQ and DTACK are control signals supplied from ACRTC to the microprocessor side, and DRA
W, MRD, CHR, CUDl, 2. H3YNC,VS
YNC, DISPI.

Retrospective 2. What is indicated by AS is the control or timing signal supplied from the ACRTC to the CRT display side.
RES is a reset signal for ACRTC, CLOCK
and MCYC are clocks input and output to ACRTC.

In addition, DACK, C3, RS, and R/W are control signals supplied to ACRTC from the microprocessor side, and LPS
TB, EXSYNC are control and timing signals supplied to the ACRTC from the CRT display side.

In the above embodiment, the ground potential Vs has a relatively small margin.
Although we have explained the case where it is applied to the power supply wiring on the s side, the power supply wiring that supplies the power supply voltage Vcc to each output buffer can be similarly divided by providing a power supply pad for each output buffer with a different timing. if,
It is possible to prevent the occurrence of noise that appears in the high level of the output.

more effective.

Furthermore, in the above embodiment, the power supply wiring and power supply pads are divided for each output buffer with different timing, but if the power supply pins that supply the power supply voltage to the power supply pads are similarly divided and provided with a plurality of them, the effect will be even more effective. It is true.

Also, even if the output buffers have the same timing, if the power supply wiring cannot be shared due to layout reasons,
It may be arranged separately.

[Effects] Since the power wiring is divided for each output buffer with different timing to supply the power supply voltage, when the output signal of the output buffer at a certain timing is latched, the output change of the output buffer at another timing is different. This prevents noise from being generated by
The LSI that takes in the output may launch incorrect data.

This has the effect that an LSI having a circuit that performs latching using the output is prevented from malfunctioning.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, only the power supply wiring may be divided into output buffers with different timings, and the power supply pads may be shared. Further, in the above embodiment, a case has been described in which the present invention is applied to a power supply wiring to an output buffer through which a particularly large current flows, but it is also possible to similarly apply the present invention to a power supply wiring to an internal circuit.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to logic LSIs, which is the field of application that formed the background of the invention. can do.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a power wiring system in a semiconductor integrated circuit device according to the present invention, and FIG. 2 is an explanation showing a conventional general power wiring system. Fig. 3 is a waveform diagram showing the output state of the output buffer according to the conventional method, Fig. 4 is a waveform diagram showing the output state of the output buffer when the present invention is applied, and Fig. 5 is a waveform diagram showing the output state of the output buffer when the present invention is applied. FIG. 2 is a block diagram showing a configuration example of an ACRTC as an example of an LSI that can provide an effective effect in the case of the present invention. 1 al ~ tan, 1 bl ~ l bm, 1
b - output buffer, 2a, 2b, 2... power supply pad, 3a, 3b, 3... power supply wiring, 11...
System bus interface, 12...CRT
Interface, 13... Drawing processor, 14...
... Display processor, 15 ... Timing processor, 16 ... DMA control circuit, 17 ... Interrupt control circuit.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a plurality of output buffers with different timings, at least one of the power supply voltages of the circuit is provided by separate power supply wirings for each output buffer with different timings. A semiconductor integrated circuit device, characterized in that it is made to be supplied. 2. The semiconductor integrated circuit device according to claim 1, wherein the divided power supply wirings are each connected to separate power supply pads. 3. Has multiple clocks with different phases or periods,
A patent characterized in that, in a semiconductor integrated circuit device having an output buffer operated at different timings depending on the clock, a power supply voltage is supplied to the output buffer through a separate power supply wiring for each operating clock. A semiconductor integrated circuit device according to claim 1 or 2.