JPS6152587B2 - - Google Patents
Info
- Publication number
- JPS6152587B2 JPS6152587B2 JP54083932A JP8393279A JPS6152587B2 JP S6152587 B2 JPS6152587 B2 JP S6152587B2 JP 54083932 A JP54083932 A JP 54083932A JP 8393279 A JP8393279 A JP 8393279A JP S6152587 B2 JPS6152587 B2 JP S6152587B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- etching
- conductor
- conductors
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001894 space-charge-limited current method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823406—Combination of charge coupled devices, i.e. CCD, or BBD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明は電荷結合素子(以下CCDと略称す
る)の転送電極部の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a transfer electrode portion of a charge coupled device (hereinafter abbreviated as CCD).
従来のCCDの例としては、第1図に示すよう
に、N型シリコン基板10表面上に薄い酸化膜2
をつけ、入出力部分に酸化膜2に選択エツチング
によりコンタクト穴31,32をあけ、P+拡散
層111,112を形成した後、全面にアルミニ
ウム導電膜を蒸着により形成し、パターニングに
より入出力ゲート電極43,44(動作時にそれ
ぞれVS,VEなる電圧が与えられる)と転送電極
511,512,513,521,522,52
3とこれら転送電極間の配線61,62,63と
入出力部の配線41,42とを形成する。配線6
1は転送電極511および521が端子に接続
されるように、また配線62は転送電極512お
よび522が端子に接続されるように、さらに
配線63は転送電極513および523が端子
に接続されるように形成される。出力部の配線4
2は出力端子VOに接続されかつあらかじめ公知
の方法で形成された抵抗6の一端に接続されかつ
コンタクト穴32を通してP+拡散層112に接
続されるように形成される。入力部の配線41は
入力端子VDに接続されかつコンタクト穴31を
通してP+拡散層111に接続されるように形成
される。抵抗6の他端は動作時にVDDなる電圧が
与えられる。 As an example of a conventional CCD, as shown in FIG. 1, a thin oxide film 2 is formed on the surface of an N-type silicon substrate 10.
After forming contact holes 31 and 32 in the oxide film 2 at the input/output area by selective etching and forming P + diffusion layers 111 and 112, an aluminum conductive film is formed on the entire surface by vapor deposition, and the input/output gates are formed by patterning. Electrodes 43, 44 (to which voltages V S and V E are applied, respectively, during operation) and transfer electrodes 511, 512, 513, 521, 522, 52
3, wirings 61, 62, 63 between these transfer electrodes, and wirings 41, 42 of the input/output section are formed. Wiring 6
1 so that the transfer electrodes 511 and 521 are connected to the terminals, wiring 62 so that the transfer electrodes 512 and 522 are connected to the terminals, and wiring 63 so that the transfer electrodes 513 and 523 are connected to the terminals. is formed. Output section wiring 4
2 is connected to the output terminal V O and to one end of a resistor 6 formed in advance by a known method, and is connected to the P + diffusion layer 112 through a contact hole 32 . The input wiring 41 is connected to the input terminal V D and is connected to the P + diffusion layer 111 through the contact hole 31 . The other end of the resistor 6 is applied with a voltage of V DD during operation.
このようなCCD転送電極部の動作は、転送電
極電圧がV1のとき転送電極下のシリコン基板1
0の表面に反転層が形成され、V2のとき形成さ
れないとすると、転送時は適当な隣合う2個の電
極例えば511,512に各々V1,V2を与えて
いたものをV2,V1にすることにより電極511
に蓄えていた電荷を電極512の方に転送する。
この転送は空間電荷制限電流ICの形で電荷を移
動することであり、転送電極間の距離をLC、隣
合う両転送電極下のシリコン基板表面のポテンシ
ヤル差をVC、電荷移動断面積をSとすると下式
が成立する。 This kind of operation of the CCD transfer electrode section is such that when the transfer electrode voltage is V1 , the silicon substrate 1 under the transfer electrode
Assuming that an inversion layer is formed on the surface of 0 and is not formed when the voltage is V 2 , then during transfer, V 1 and V 2 are applied to two appropriate adjacent electrodes, for example, 511 and 512, respectively . By setting V 1 , the electrode 511
The charges stored in the electrode 512 are transferred to the electrode 512.
This transfer is to move charges in the form of a space charge limited current I C , where L C is the distance between the transfer electrodes, V C is the potential difference between the silicon substrate surfaces under both adjacent transfer electrodes, and the charge transfer cross section is Let S be the following formula.
IC=KS/LC 3VC 2(但しKは定数) (1)
第1図において酸化膜2の厚みを一定、V1お
よびV2のそれぞれの値を固定、Sを一定とみな
せば、ICを大きくして電荷の転送スピードを上
げようとするにはLCを小さくすればよい。とこ
ろが第1図の構造では転送電極間の間隔LCはパ
ターニングできる限界以上に小さくはできない
し、又エツチングその他による寸法のバラツキが
存在するため、転送スピードを速くできず、転送
電極毎の転送スピードにバラツキがあり、しかも
集積度面においても不利であるなどの欠点があ
る。 I C = KS/L C 3 V C 2 (K is a constant) (1) In Fig. 1, if we assume that the thickness of the oxide film 2 is constant, the values of V 1 and V 2 are fixed, and S is constant, then , In order to increase the charge transfer speed by increasing I C , it is sufficient to decrease L C. However, in the structure shown in Figure 1, the spacing L C between the transfer electrodes cannot be made smaller than the limit that can be patterned, and there are variations in dimension due to etching and other factors, so the transfer speed cannot be increased, and the transfer speed of each transfer electrode is It has drawbacks such as variations in the amount of data and disadvantages in terms of integration.
本発明の目的は、上述した欠点に鑑み、転送電
極間の離間距離を著しく小さくすることができる
電荷結合素子の製造方法を提供することである。 SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide a method for manufacturing a charge-coupled device in which the distance between transfer electrodes can be significantly reduced.
本発明の他の目的は、転送電極間を絶縁する絶
縁層を、特定の位置にのみ無駄なく容易に形成さ
せることができる電荷結合素子の製造方法を提供
することである。 Another object of the present invention is to provide a method for manufacturing a charge-coupled device that can easily form an insulating layer that insulates between transfer electrodes only at specific positions without waste.
本発明の究極の目的は、転送効率の高い電荷結
合素子の製造方法を提供することである。 The ultimate objective of the present invention is to provide a method for manufacturing a charge coupled device with high transfer efficiency.
本発明によれば、半導体基板表面上に第1の絶
縁膜を形成する工程と、該第1の絶縁膜上の全面
に第1の導電膜を形成する工程と、前記第1の導
電膜を所定のエツチングマスクパターンを用いて
選択的にエツチングし、所定の方向に配列された
複数の第1の導電体を形成する工程と、該複数の
第1の導電体上及び前記第1の絶縁膜上に第2の
絶縁膜を形成する工程と、前記エツチングマスク
パターンを、前記第1の導電膜のエツチングの場
合よりも、前記複数の第1の導電体の配列方向に
移動させた状態で用いて、前記第2の絶縁膜のう
ち、各第1の導電体の一方の側面を含む部分を被
つている箇所をエツチングし、前記各第1の導電
体の前記一方の側面を含む部分を露出させる工程
と、前記各第1の導電体のうち、露出された前記
一方の側面を含む部分の表面を、該第1の導電体
材料の化合物からなる第3の絶縁膜に変換する工
程と、前記第2の絶縁膜を選択エツチングにより
除去し、前記各第1の導電体のもう一方の側面を
含む部分を露出させる工程と、前記各第1の導電
体のうち露出された前記もう一方の側面と、それ
に対面する隣りの第1の導電体に形成された前記
第3の絶縁膜の側面と、それら側面間に挟まれた
前記第1の絶縁膜の表面とに少なくとも付着する
第2の導電体を形成する工程とを含み、互に接続
した前記第1及び第2の導電体が複数の転送電極
の各々を構成し、かつ各転送電極間の絶縁が前記
第3の絶縁膜によりなされている電荷結合素子を
得ることを特徴とする電荷結合素子の製造方法が
得られる。 According to the present invention, the steps include: forming a first insulating film on the surface of a semiconductor substrate; forming a first conductive film on the entire surface of the first insulating film; a step of selectively etching using a predetermined etching mask pattern to form a plurality of first conductors arranged in a predetermined direction; and a step of forming a plurality of first conductors and the first insulating film on the plurality of first conductors. forming a second insulating film thereon; and using the etching mask pattern moved in the direction in which the plurality of first conductors are arranged, compared to when etching the first conductive film. etching a portion of the second insulating film that covers a portion including one side surface of each first conductor to expose a portion including the one side surface of each first conductor; converting the surface of a portion of each of the first conductors including the exposed one side surface into a third insulating film made of a compound of the first conductor material; removing the second insulating film by selective etching to expose a portion including the other side surface of each of the first conductors; A second insulating film that adheres at least to a side surface, a side surface of the third insulating film formed on the adjacent first conductor facing thereto, and a surface of the first insulating film sandwiched between the side surfaces. forming a conductor, the first and second conductors connected to each other constitute each of a plurality of transfer electrodes, and insulation between each transfer electrode is provided by the third insulating film. A method for manufacturing a charge-coupled device is obtained, which is characterized in that a charge-coupled device is obtained.
第2図に本発明の一実施例によるCCDを製造
工程順に示す。 FIG. 2 shows a CCD according to an embodiment of the present invention in the order of manufacturing steps.
まず、第2図Aに示すように、N型シリコン基
板10表面上に薄い酸化膜2を形成した後、該酸
化膜2上の全面に高濃度不純物を含むポリシリコ
ン層を形成し、該ポリシリコン層を、パターン幅
dC、パターン間のすきまdD、パターン繰り返し
間隔d(d=dC+dD)のエツチングマスクパタ
ーンを用いてエツチングしてポリシリコンパター
ン511a,512a,513a,512a,…
を形成し、全面に窒化膜7を被着する。 First, as shown in FIG. 2A, a thin oxide film 2 is formed on the surface of an N-type silicon substrate 10, and then a polysilicon layer containing high concentration impurities is formed on the entire surface of the oxide film 2. Polysilicon patterns 511a , 512a , 513a, 512a , ...
A nitride film 7 is deposited on the entire surface.
次に、第2図Bに示すように、上記エツチング
マスクパターンを上述のポリシリコン層のエツチ
ングの場合よりも転送方向にdO(ただしdO<d
C)だけ移動せしめた状態で窒化膜7をエツチン
グし、露出したポリシリコンパターン511a,
512a,513a,521a,…の表面を厚み
tに酸化し厚みtの酸化膜8を形成する。窒化膜
7はこの酸化の際のマスクとしての作用をする。 Next, as shown in FIG. 2B, the etching mask pattern is etched in the transfer direction by d O (where d O <d
C ), the nitride film 7 is etched, and the exposed polysilicon pattern 511a,
The surfaces of 512a, 513a, 521a, . . . are oxidized to a thickness of t to form an oxide film 8 of a thickness of t. The nitride film 7 acts as a mask during this oxidation.
次に第2図Cに示すように窒化膜7を選択エツ
チングにより除去し、全面にアルミニウム導電膜
を被着した後、酸化膜8上のアルミニウム導電膜
をエツチング除去することによつて、それぞれ酸
化膜8の側面に密着し酸化膜8の該側面とそれに
対面するポリシリコンパターン511a,512
a,513a,521a,…の側面との間の酸化
膜2上を覆いポリシリコンパターン511a,5
12a,513a,521a,…につながるアル
ミニウム導電膜511b,512b,513b,
521b,…を残す。各転送電極は互いに接続さ
れた、高濃度不純物を含むポリシリコン層511
a,512a,513a,521a,…とアルミ
ニウム導電膜511b,512b,513b,5
21b,…との組合せよりなり、各転送電極間の
絶縁は厚みtの酸化膜8によりなされている。な
お、第2図Cでは図示を省略したが、第2図Cに
おいても第1図と同様に配線41,42,61,
62,63やP+拡散層111,112や抵抗6
などが形成されている。 Next, as shown in FIG. 2C, the nitride film 7 is removed by selective etching, an aluminum conductive film is deposited on the entire surface, and the aluminum conductive film on the oxide film 8 is removed by etching. Polysilicon patterns 511a and 512 closely adhere to the side surfaces of the film 8 and face the side surfaces of the oxide film 8.
a, 513a, 521a, ... covering the oxide film 2 between the polysilicon patterns 511a, 5
Aluminum conductive films 511b, 512b, 513b, connected to 12a, 513a, 521a, ...
521b,... are left. Each transfer electrode is connected to a polysilicon layer 511 containing high concentration impurities.
a, 512a, 513a, 521a, ... and aluminum conductive films 511b, 512b, 513b, 5
21b, . . . , and insulation between each transfer electrode is provided by an oxide film 8 having a thickness of t. Although not shown in FIG. 2C, the wirings 41, 42, 61,
62, 63, P + diffusion layer 111, 112 and resistor 6
etc. are formed.
このようにすれば、CCD動作上の各転送電極
寸法は(d―t)となり、各転送電極間寸法LC
は酸化膜8の厚みtとなるためLCの値を小さく
抑えることができ、製造上の寸法バラツキも小さ
く抑えることができ、転送スピードの高速化およ
び転送電極毎の転送スピードの均一化など転送特
性の改善が図れるとともに高集積化に適している
という効果もある。 If this is done, the dimensions of each transfer electrode in CCD operation will be (d-t), and the dimension between each transfer electrode L C
is the thickness t of the oxide film 8, so the value of L C can be kept small, dimensional variations in manufacturing can be kept small, and transfer speeds can be increased and transfer speeds made uniform for each transfer electrode. It has the effect of not only improving characteristics but also being suitable for high integration.
なお、本発明は上述した実施例に限定されるこ
となく請求の範囲に記載した範囲内で種々の変形
や変更が可能である。例えば上記実施例では第1
の導電膜として高濃度の不純物を含むポリシリコ
ンを用いたが、酸化などして化合物を形成した場
合絶縁膜となるような導電膜(例えばアルミニウ
ム)であれば使用できる。また上記実施例では端
子,,を有する3相の電荷結合素子の場合
を説明したが、本発明は2相の電荷結合素子にも
同様に適用でき同様の効果を有するものである。 Note that the present invention is not limited to the embodiments described above, and various modifications and changes can be made within the scope of the claims. For example, in the above embodiment, the first
Although polysilicon containing a high concentration of impurities was used as the conductive film, any conductive film (for example, aluminum) that becomes an insulating film when a compound is formed by oxidation or the like can be used. Further, in the above embodiment, a three-phase charge-coupled device having terminals, .
以上説明したように本発明によれば、複数の第
1の導電体(ポリシリコンパターン)を形成する
ためのエツチングマスクパターンを、その際の設
定位置から、該第1の導電体の配列方向に適宜移
動させるだけで、第3の絶縁膜(酸化膜)を形成
すべき各第1の導電体の一方の側面を露出させる
ためのエツチング位置を設定することができる。 As explained above, according to the present invention, an etching mask pattern for forming a plurality of first conductors (polysilicon patterns) is formed from the set position at that time in the direction in which the first conductors are arranged. By simply moving it appropriately, it is possible to set the etching position for exposing one side surface of each first conductor on which the third insulating film (oxide film) is to be formed.
このように、エツチングマスクパターンを、前
記各第1の導電体を形成するための設定位置か
ら、その配列方向に単に移動させるだけで、第3
の絶縁膜を形成すべきエツチング位置を容易に決
定することができるから、改めて個別にエツチン
グ位置を設定する煩しさがない。 In this way, by simply moving the etching mask pattern from the set position for forming each of the first conductors in the arrangement direction, the third etching mask pattern can be formed.
Since the etching position where the insulating film is to be formed can be easily determined, there is no need to set the etching position individually.
しかも、各第1の導電体のうち上記一方の側面
以外は露出せず、必然的にエツチングされること
はないから、不要な場所に絶縁膜を形成するロス
を回避することもできる。 Moreover, since only the one side surface of each first conductor is exposed and is not inevitably etched, it is possible to avoid the loss of forming an insulating film in an unnecessary location.
一方、第1の導電体の上記一方の側面に形成さ
れた第3の絶縁膜と、対向する他の第1の導電体
の側面との間に、第2の導電体(アルミニウム導
電膜)を形成することにより、第1の導電体と第
2の導電体とからなる1個の転送電極が形成され
る。即ち、一方の側面を第3の絶縁膜で絶縁した
第1の導電体間の間隙に、第1の導電体の他方の
側面に直接接続される第2の導電体を充填するこ
とにより、第3の絶縁膜の厚さのみを転送電極間
の離間距離とすることができ従つて、第3の絶縁
膜を特定の位置にのみ無駄なく正確に形成させる
ことができ、しかも、転送電極間を第3の絶縁膜
のみを介して隣接させることができるから、歩留
り及び転送効率の高い電荷結合素子を提供するこ
とができ、転送スピードの高速化が可能な、転送
電極毎の転送スピードのバラツキの少ない、高集
積化が可能な電荷結合素子が得られる。 On the other hand, a second conductor (aluminum conductive film) is provided between the third insulating film formed on the one side surface of the first conductor and the opposing side surface of the other first conductor. By forming one transfer electrode made of the first conductor and the second conductor. That is, by filling the gap between the first conductors whose one side surface is insulated with the third insulating film with the second conductor directly connected to the other side surface of the first conductor, Only the thickness of the third insulating film can be used as the separation distance between the transfer electrodes. Therefore, the third insulating film can be formed accurately only at specific positions without waste, and the distance between the transfer electrodes can be Since they can be adjacent to each other through only the third insulating film, it is possible to provide a charge-coupled device with high yield and transfer efficiency. A charge-coupled device that can be highly integrated with a small number of cells can be obtained.
第1図は従来のCCDの断面図、第2図A,B
およびCは本発明の一実施例によるCCDの転送
電極部を製造工程順に示した断面図である。
10……N型シリコン基板、2……薄い絶縁
膜、511a,512a,513a,521a…
…高濃度不純物を含むポリシリコンパターン、5
11b,512b,513b,521b……アル
ミニウム導電膜、8……511a,512a,5
13a,521aの表面を酸化して形成した酸化
膜。
Figure 1 is a cross-sectional view of a conventional CCD, Figure 2 A and B
and C are cross-sectional views showing the transfer electrode portion of a CCD according to an embodiment of the present invention in the order of manufacturing steps. 10... N-type silicon substrate, 2... Thin insulating film, 511a, 512a, 513a, 521a...
...Polysilicon pattern containing high concentration impurities, 5
11b, 512b, 513b, 521b...aluminum conductive film, 8...511a, 512a, 5
An oxide film formed by oxidizing the surfaces of 13a and 521a.
Claims (1)
工程と、該第1の絶縁膜上の全面に第1の導電膜
を形成する工程と、前記第1の導電膜を所定のエ
ツチングマスクパターンを用いて選択的にエツチ
ングし、所定の方向に配列された複数の第1の導
電体を形成する工程と、該複数の第1の導電体上
及び前記第1の絶縁膜上に第2の絶縁膜を形成す
る工程と、前記エツチングマスクパターンを、前
記第1の導電膜のエツチングの場合よりも、前記
複数の第1の導電体の配列方向に移動させた状態
で用いて、前記第2の絶縁膜のうち、各第1の導
電体の一方の側面を含む部分を被つている箇所を
エツチングし、前記各第1の導電体の前記一方の
側面を含む部分を露出させる工程と、前記各第1
の導電体のうち、露出された前記一方の側面を含
む部分の表面を、該第1の導電体材料の化合物か
らなる第3の絶縁膜に変換する工程と、前記第2
の絶縁膜を選択エツチングにより除去し、前記各
第1の導電体のもう一方の側面を含む部分を露出
させる工程と、前記各第1の導電体のうち露出さ
れた前記もう一方の側面と、それに対面する隣り
の第1の導電体に形成された前記第3の絶縁膜の
側面と、それら側面間に挟まれた前記第1の絶縁
膜の表面とに少なくとも付着する第2の導電体を
形成する工程とを含み、互に接続した前記第1及
び第2の導電体が複数の転送電極の各々を構成
し、かつ各転送電極間の絶縁が前記第3の絶縁膜
によりなされている電荷結合素子を得ることを特
徴とする電荷結合素子の製造方法。1. A step of forming a first insulating film on the surface of a semiconductor substrate, a step of forming a first conductive film on the entire surface of the first insulating film, and etching the first conductive film with a predetermined etching mask pattern. a step of selectively etching a plurality of first conductors using a method to form a plurality of first conductors arranged in a predetermined direction; and etching a second conductor on the plurality of first conductors and on the first insulating film. forming an insulating film, and using the etching mask pattern moved in the direction in which the plurality of first conductors are arranged, compared to when etching the first conductive film, and etching the second conductive film. etching a portion of the insulating film that covers a portion including one side surface of each first conductor to expose a portion including the one side surface of each first conductor; each first
converting the surface of a portion of the conductor including the exposed one side surface into a third insulating film made of a compound of the first conductor material;
removing the insulating film by selective etching to expose a portion including the other side surface of each of the first conductors; and the exposed other side surface of each of the first conductors; a second conductor that adheres at least to the side surface of the third insulating film formed on the adjacent first conductor facing thereto and the surface of the first insulating film sandwiched between the side surfaces; the first and second conductors connected to each other constitute each of a plurality of transfer electrodes, and the third insulating film provides insulation between the transfer electrodes. A method for manufacturing a charge-coupled device, the method comprising obtaining a coupled device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8393279A JPS568877A (en) | 1979-07-04 | 1979-07-04 | Charge coupling element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8393279A JPS568877A (en) | 1979-07-04 | 1979-07-04 | Charge coupling element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS568877A JPS568877A (en) | 1981-01-29 |
JPS6152587B2 true JPS6152587B2 (en) | 1986-11-13 |
Family
ID=13816363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8393279A Granted JPS568877A (en) | 1979-07-04 | 1979-07-04 | Charge coupling element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS568877A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS574162A (en) * | 1980-06-10 | 1982-01-09 | Sony Corp | Manufacture of charge transfer device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5313951A (en) * | 1976-07-26 | 1978-02-08 | Citizen Watch Co Ltd | Watchcase |
-
1979
- 1979-07-04 JP JP8393279A patent/JPS568877A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5313951A (en) * | 1976-07-26 | 1978-02-08 | Citizen Watch Co Ltd | Watchcase |
Also Published As
Publication number | Publication date |
---|---|
JPS568877A (en) | 1981-01-29 |
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