JPS6151934A - Hybrid ic device - Google Patents

Hybrid ic device

Info

Publication number
JPS6151934A
JPS6151934A JP59174653A JP17465384A JPS6151934A JP S6151934 A JPS6151934 A JP S6151934A JP 59174653 A JP59174653 A JP 59174653A JP 17465384 A JP17465384 A JP 17465384A JP S6151934 A JPS6151934 A JP S6151934A
Authority
JP
Japan
Prior art keywords
solder
chip
power
copper
insulation substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59174653A
Other languages
Japanese (ja)
Inventor
Toshio Hiroe
廣江　敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59174653A priority Critical patent/JPS6151934A/en
Publication of JPS6151934A publication Critical patent/JPS6151934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain the titled device having a lifetime of the same as convention or more even in power-up by a method wherein, using Sn-Sb solder as the mounting material connecting a power chip within a copper chip, the copper chip to an in insulation substrate and the insulation substrate to a heat sink are connected with eutectic solders. CONSTITUTION:The power chip 21 is connected to the copper chip 22 with an Sn-Sb solder (Sb=8.5%) 31, and the copper chip is connected to the insulation substrate 23 with an eutectic solder 32; further; the insulation substrate is connected to the heat sink 24 with an eutectic solder 33. This manner allows the strain caused by the difference in coefficient of thermal expansion between the power chip and the copper chip generating by heat cycles evolving in the power chip to be aoplied to the solder part therebetween. However, in the case of Sn- Sb solder, elongation is larger then the case of using the conventional Sn-Sb solder; therefore, the degree of fatigue caused by the repeated strains of the solder part becomes relived, and the lifetime of the power chip caused by thermal fatigue becomes prolonged.

Description

【発明の詳細な説明】 （分野） 本発明は、パワー部を少なくとも１ケ所以上有するパワ
ー混成集積回路装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field) The present invention relates to the structure of a power hybrid integrated circuit device having at least one power section.

（従来技術） 従来、パワー部の構造は、銅片にＮ１メッキあるいにさ
らにＡｕメッキを施こしたものに、５１１−九系のはん
だ（Ｐｂ＝９２〜９５ｗｔ％）でパワーチップ全接続し
、それ全絶縁基板に共晶はんだで接続し、さらに、絶縁
基板とヒートシンク間金共晶はんだで接続していた。ま
現、最近のパワー混成集積回路装置の要求は小型化と共
にパワーアップの傾向にある。(Prior art) Conventionally, the structure of the power section was to connect all the power chips to a copper piece plated with N1 or further plated with Au using 511-9 series solder (Pb = 92 to 95 wt%). , it was connected to a fully insulated board with eutectic solder, and then connected between the insulated board and the heat sink with gold eutectic solder. Currently, the recent demand for power hybrid integrated circuit devices is toward smaller size and higher power.

（目的） しかし、パワーアップの要求に対して、従来の構造では
、パワーチップの断続的な発熱（熱サイクル）や、外部
からの熱的変化で、熱膨張率が異なる材料の組合せによ
って生じる歪の殆んどを吸収しているはんだ部の寿命が
短かくなってしまい。(Purpose) However, in response to the demand for increased power, the conventional structure is unable to handle the distortion caused by the intermittent heat generation (thermal cycle) of the power chip and the combination of materials with different coefficients of thermal expansion due to external thermal changes. The life of the solder part, which absorbs most of the heat, is shortened.

パワーチップの特性劣化につながるという問題がある。There is a problem in that it leads to deterioration of the characteristics of the power chip.

本発明は、最も歪が大きい、パワーチップと銅片間のは
んだｆｆ１ｆえる事によりパワーアップになっても従来
と同等以上の寿命を有する混成集積回路装置を提供する
ものである。The present invention provides a hybrid integrated circuit device which has a lifespan equal to or longer than that of the conventional device even when the power is increased by reducing the solder ff1f between the power chip and the copper piece, which has the largest distortion.

（構成） 本発明はパワーチップと銅片とを接続するマウント材と
して５ｎ−Ｓｂ’Ｌんだ全使用し、銅片と杷傍基板間を
共晶はんだで接続し、さらに絶縁基板とヒートシンク間
？共晶にんだで接続した事を特徴とするものである。(Structure) The present invention uses 5n-Sb'L solder as a mounting material to connect the power chip and the copper piece, connects the copper piece and the base board with eutectic solder, and furthermore, connects the insulating board and the heat sink with eutectic solder. ? It is characterized by being connected using eutectic solder.

この場合Ｓｂの量によって、寿命に差があり。In this case, the lifespan varies depending on the amount of Sb.

５ｂ＝８〜１０　ｗ　ｔ％　が最も適量である。5b=8 to 10 wt% is the most appropriate amount.

（効果） 本発明によればパワーチップで発生する熱サイクルに：
り発生する、パワーチップ（Ｓｉ）と銅片の熱膨張率の
差による歪は、それらの間のはんだ部に加わるが５ｎ−
Ｓｂはんだの喝合、従来の構造５ｎ−ｐｂＨんだ使用）
に比べ伸びが大きい為、はんだ部のくり返し歪による疲
労度が柔らぎ、熱疲労にＬるパワーチップの寿命が長く
なる。(Effects) According to the present invention, thermal cycles occurring in power chips:
5n-
Sb solder combination, conventional structure using 5n-pbH solder)
Since the elongation is larger than that of the solder part, the degree of fatigue caused by repeated strain in the solder part is reduced, and the life of the power chip, which is less susceptible to thermal fatigue, is extended.

パワーチップ２１を銅片２２に５ｎ−３ｂはんだ（Ｓｂ
二８，５％）３１で接伏し、銅片と絶縁基板（八６２０
３）２゛３　ｉ共晶はんだ３２で接続し、さらに絶縁基
板とヒートシンク（Ａｄ）２４全共晶にんだ３３で接続
した例を第３図に示す。Connect the power chip 21 to the copper piece 22 with 5n-3b solder (Sb
28,5%) 31, copper piece and insulating board (8620
3) FIG. 3 shows an example in which the 2-3i eutectic solder 32 is used for connection, and the insulating substrate and the heat sink (Ad) 24 are connected using all-eutectic solder 33.

本構造金有する混成集積回路装置にてパワーサ２倍以上
の寿命がある事が確認された。It has been confirmed that a hybrid integrated circuit device with this structure has a lifespan that is more than twice as long as the power sensor.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、パワー部を有する混成集積回路装置全表わす
平面図。第２図はパワー部を有する混成集積回路装置の
パワー部断面図を表わす。第３図［ａｌ、　ｔｂｌに２
本発明の実施例を示す平面図および断面図。 ｌ、２１・・・・・・パワーチップ、２．２２・・・・
・・銅片。 ３・・・・・・絶縁基板、４・・・・・・ヒートシンク
、５・・・・・ドライバ一部、　１　ｘ−＝・５ｎ−Ｐ
ｂはんだ、１２，１３゜３２．３３・・・・・・共晶に
んだ、２３・・・・・・絶縁基板（ＡＪ２０ｓ　）　、
　　２４・・・・・・ヒートシンク（ＡＪ）、３１・・
・・・Ｓｎ−Ｓｂ（５ｂ＝８．５ｗ　ｔ％〕。 叉二FIG. 1 is a plan view showing the entire hybrid integrated circuit device having a power section. FIG. 2 shows a sectional view of a power section of a hybrid integrated circuit device having a power section. Figure 3 [al, tbl 2
1 is a plan view and a sectional view showing an embodiment of the present invention. l, 21... Power chip, 2.22...
...Copper piece. 3...Insulating board, 4...Heat sink, 5...Part of driver, 1 x-=・5n-P
b Solder, 12,13°32.33...eutectic solder, 23...Insulating board (AJ20s),
24...Heat sink (AJ), 31...
...Sn-Sb (5b=8.5wt%).

Claims (1)

【特許請求の範囲】[Claims] パワー部を有する混成集積回路装置において、パワーチ
ップと銅片間をＳ＿ｎ−Ｓ＿ｂ（Ｓ＿ｂ＝８〜１０ｗｔ
％）で接続、銅片と絶縁基板間を共晶はんだで接続、さ
らに、絶縁基板とヒートシンク間を共晶はんだで接続し
たことを特徴とする混成集積回路装置。In a hybrid integrated circuit device having a power section, the distance between the power chip and the copper piece is S_n-S_b (S_b=8~10wt
%), a copper piece and an insulating substrate are connected by eutectic solder, and an insulating substrate and a heat sink are connected by eutectic solder.
JP59174653A 1984-08-22 1984-08-22 Hybrid ic device Pending JPS6151934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59174653A JPS6151934A (en) 1984-08-22 1984-08-22 Hybrid ic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59174653A JPS6151934A (en) 1984-08-22 1984-08-22 Hybrid ic device

Publications (1)

Publication Number Publication Date
JPS6151934A true JPS6151934A (en) 1986-03-14

Family

ID=15982350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59174653A Pending JPS6151934A (en) 1984-08-22 1984-08-22 Hybrid ic device

Country Status (1)

Country Link
JP (1) JPS6151934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283741A (en) * 2008-05-23 2009-12-03 Fuji Electric Device Technology Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283741A (en) * 2008-05-23 2009-12-03 Fuji Electric Device Technology Co Ltd Semiconductor device

Similar Documents

Publication Publication Date Title
US20050218426A1 (en) Power semiconductor module
EP1154471A4 (en) Semiconductor chip and manufacture method thereof
JPH1012790A (en) Semiconductor integrated circuit device
JPH03142847A (en) Semiconductor integrated circuit device
US20070290303A1 (en) Dual leadframe semiconductor device package
JPS6151934A (en) Hybrid ic device
JPH0418694B2 (en)
JPWO2007141851A1 (en) Semiconductor package and electronic device
JP3561671B2 (en) Semiconductor device
JPH0278265A (en) Lead frame and compound semiconductor device provided therewith
JPS6151837A (en) Hybrid integrated circuit device
JPS58218130A (en) Hybrid integrated circuit
JPS61139054A (en) Semiconductor device
JPH0778903A (en) Method of bias voltage application in hybrid integrated circuit
KR100321149B1 (en) chip size package
JPS60138945A (en) Sealed semiconductor device
KR0119755Y1 (en) Semiconductor package
JPH051079Y2 (en)
JPH01185957A (en) Semiconductor device
KR100203338B1 (en) Semiconductor module of power control
JPH0496240A (en) Semiconductor integrated circuit device and device thereof
JPS60241240A (en) Semiconductor device
KR20000041033A (en) Ball grid array package and mounting method thereof
JPH09283887A (en) Semiconductor device and metal insulation substrate used for this device
JPH05335480A (en) Power supply semiconductor module