JPS6151809B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic sweep device that performs sweep selection within a range between an upper limit value and a lower limit value of a reception band.

In general, the reception band limits are determined by each country. For example, in Japan, for FM broadcasting, the upper limit is 90.0MHZ and the lower limit is 90.0MHZ.
It is 76.0MHz. Therefore, when performing automatic sweep channel selection, it is necessary to set the upper and lower limits of the receiving band in advance, and in the conventional voltage synthesizer method, the upper and lower limit voltages of the DC voltage for local oscillation frequency control are semi-fixed. It was set using volume etc.

However, this method lacks accuracy because the upper and lower limits of the receiving band tend to fluctuate due to factors such as power supply voltage.

The present invention has been developed in view of this problem, and it is possible to store the upper and lower limits of the reception band in advance, and to detect when the reception frequency becomes higher than or equal to the stored upper limit or lower than the stored lower limit during sweeping. If detected,
The present invention provides a new automatic sweep device that operates a PLL loop and locks the reception frequency at the upper or lower limit of the reception band.

Hereinafter, the present invention will be explained based on examples and with reference to the drawings.

In Fig. 1, 1 is a general FM receiver. The signal received by the antenna 2 is amplified by a radio frequency amplifier 3, and then sent to a local oscillation circuit 5 by a mixing circuit 4.
It is mixed with the signal from and converted into an intermediate frequency signal. Then, the intermediate frequency signal is amplified by an intermediate frequency amplification circuit 6, further detected by a detection circuit 7, and then amplified by a low frequency amplification circuit 8 and outputted through a speaker 9.

Reference numeral 10 denotes a voltage generating means for generating a DC tuning voltage V _T for controlling the local oscillation frequency, and is composed of a window comparator 11, a low-pass filter 12, and a constant-current charge pump 13 for controlling charging and discharging of a capacitor in the low-pass filter 12. Ru. When the input voltage Sout becomes higher than the high threshold level V _IH of the window comparator 11, the DC tuning voltage V _T is reduced by discharging the capacitor.
to lower the low threshold hold level V _IL
When the voltage becomes lower, the DC tuning voltage V _T is increased by charging the capacitor.

14 is a window comparator that generates an SH signal and an SL signal according to the S curve signal Sin input through the amplifier circuit 15; 16 is an H/L signal that controls the sweep speed; and a U/D signal that controls the sweep direction. and a sweep control circuit that generates a three-value sweep signal of "H", "L", and "high impedance" (hereinafter referred to as "∞") according to the SR signal that controls the start and stop of the sweep operation; 17 is a control circuit; , 18 count the local oscillation frequency via a prescaler 19 and a gate circuit 20, and count the local oscillation frequency through a frequency division ratio data setting latch 2.
1 and a frequency division detection circuit 22.
During PLL loop operation, the up counter 23, which functions as a program divider, compares the frequency and phase of the frequency-divided output signal from the frequency division detection circuit 22 and the reference signal from the timing generation circuit 24, and outputs "H".
A phase difference signal generation circuit that generates a three-value phase difference signal of "L" and "∞"; 25 is a time base generation circuit that generates a time base for controlling the gate circuit 20;
26 is a lock detection circuit that detects that the PLL loop is locked. In addition, the phase difference signal generation circuit 2
3 and the sweep control circuit 16 are set higher than the V _IH of the window comparator 14, and the output "L" is set lower than the V _IL .

Furthermore, 27 is a frequency conversion circuit that converts the local oscillation frequency into a reception frequency, 28 is an IF fine adjustment circuit that corrects deviations in the intermediate frequency due to variations in ceramic filters, etc., and 29 is a memory that stores the upper and lower limits of the reception band. A circuit, 30, is a detection circuit for detecting whether the receiving frequency has become above the upper limit value or below the lower limit value of the receiving band, and 31 is a circuit for converting the upper limit value and lower limit value of the receiving band into frequency division ratio data of the programmable divider. This is a frequency ratio data conversion circuit.

Next, the operation of the present invention will be explained based on FIG.

When the auto/manual selector switch 32 is set to automatic sweep mode and one of the up keys 33 and down keys 34 is pressed, for example, the H/L signal, U/D, SR from the control circuit 17 is activated.
All the signals become "H" and the sweep signal Sout becomes "L". Therefore, the voltage generating means 10 increases the DC tuning voltage V _T and a high-speed upward sweep is started. During the sweep, when the S curve signal is captured, the SH signal and SL are output from the window comparator 14.
A signal is generated, and the H/L signal is used to switch between high-speed sweep and low-speed sweep, and the SR signal is used to stop the sweep.

On the other hand, the local oscillation frequency is counted by the up counter 18 at a predetermined time base via the prescaler 19 and the gate circuit 20, and is mixed with the intermediate frequency corrected by the IF fine adjustment circuit 28 in the frequency conversion circuit 27, and then is converted to

Now, if the S-curve signal is not captured while sweeping in the upward direction and the reception frequency exceeds the upper limit f _BH of the reception band, an output signal is generated from the detection circuit 30, and based on this signal, the storage circuit 29 The upper limit value f _BH of the receiving band stored in is converted by the frequency division ratio data exchange circuit 31 into frequency division ratio data of the program divider composed of 18, 21, and 22.

The converted frequency division ratio data is transferred to division ratio setting latch 2.
1, the local oscillation frequency is divided by the up counter 18 based on the division ratio data, and the divided output signal is compared with the reference signal by the phase difference generation circuit 23. Then, by applying the phase difference signal to the voltage generating means 10 , the PLL loop operates, and as shown in FIG. 2, the DC tuning voltage V _T stabilizes at the DC voltage V _BH corresponding to the upper limit value of the reception band. The receiving frequency is locked to the upper limit f _BH of the receiving band.

Next, when the lock detection circuit 26 detects that the reception frequency is locked to the upper limit f _BH of the reception band, the control circuit 17 controls the storage circuit 29
The lower limit value f _BL of the receiving band is read from the lower limit value f _{BL of the receiving band, this lower limit value f BL} is converted into frequency division ratio data by the frequency division ratio data conversion circuit 31, and the PLL loop is similarly operated to change the receiving frequency to the lower limit value f of the receiving band. Lock on _BL .

Then, when the lock detection circuit 26 detects the lock state again, the control circuit 17
By generating the SR signal, the sweep control circuit 16 applies a sweep signal to the voltage generating means 10 , and the above-mentioned sweep channel selection is started again.

In the above explanation, when the receiving frequency exceeds the upper limit value _fBH of the receiving band, it first locks to the upper limit value _fBH by PLL operation, then locks to the lower limit value _fBL of the receiving band, and then resumes sweep tuning. However, it is also possible to lock the reception frequency not at the upper limit value f _BH but at the lower limit value f _BL and then restart sweep tuning.

In addition, when the sweep direction is in the down direction, when the reception frequency becomes below the lower limit value _fBL , an output signal is generated from the detection circuit 30, and the reception frequency is adjusted to both the lower limit value _fBL and the upper limit value _fBH by PLL operation. Alternatively, it locks only to the lower limit value f _BH and, after detecting the lock, starts sweep channel selection again.

As described above, the automatic sweep device of the present invention stores the upper limit value and lower limit value of the reception band in the storage circuit, and when the reception frequency becomes higher than the upper limit value or lower limit value, the stored upper limit value and lower limit value are stored. The lower limit value is converted to division ratio data of the programmable divider and the receiving frequency is locked to the upper or lower limit value of the receiving band by PLL operation, so the receiving frequency can be swept accurately within the limit range of the receiving band. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an automatic sweeping device according to the present invention, and FIG. 2 is a characteristic diagram showing the operation of the automatic sweeping device according to the present invention. Explanation of main drawing numbers 1 ...FM receiver, 10 ...
Voltage generating means, 11...window comparator,
12...Low pass filter, 13...Constant current charge pump, 14...Window comparator, 1
6... Sweep control circuit, 17... Control circuit, 18... Up counter, 21... Frequency division ratio data setting latch, 22... Frequency division detection circuit, 23...
... Phase difference signal generation circuit, 26 ... Lock detection circuit, 27 ... Frequency conversion circuit, 28 ... IF fine adjustment circuit, 29 ... Memory circuit, 30 ... Detection circuit, 3
1... Frequency division ratio data conversion circuit.

Claims (1)

[Claims] 1. Voltage generation means for generating a DC tuning voltage for controlling the local oscillation frequency, and sweep tuning control means for generating a sweep signal for controlling the voltage generation means in response to a tuning instruction signal indicating the tuning state of the received signal. , an automatic sweep device configured to perform sweep channel selection using a voltage synthesizer method, a storage means for storing an upper limit value and a lower limit value of a reception band; A detection means for detecting that the local oscillation frequency has become below, a frequency division means for dividing the local oscillation frequency, and a phase difference signal for generating a signal corresponding to the frequency and phase difference between the frequency division output signal of the frequency division means and the reference signal. a PLL loop including a generation means, and a conversion means for converting the upper limit value and lower limit value of the receiving band into frequency division ratio data of the frequency dividing means, and the receiving frequency is greater than or equal to the upper limit value or less than the lower limit value of the receiving band. When the detection means detects that the upper limit value or the lower limit value is stored in the storage means, the conversion means converts the upper limit value or the lower limit value into frequency division ratio data, applies it to the frequency division means, and receives the data by the frequency division means. The PLL loop is operated by dividing the frequency and applying a signal corresponding to the phase difference between the output signal and the reference signal from the phase difference signal generation means to the voltage generation means, and the reception frequency is adjusted to the reception band. An automatic sweeping device characterized in that the automatic sweeping device is locked to at least one of an upper limit value and a lower limit value.