JPS6049375B2 - electronic tuning device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic tuning devices, and more particularly to automatic sweep tuning.

In automatic sweep tuning using the conventional PLL synthesizer method, tuning is performed at a predetermined local oscillation frequency, so the reception point is determined independently of the detection characteristics of the receiver.

For this reason, there was a drawback that the signal was not received at the optimum tuning point due to errors in the ceramic filter in the intermediate frequency stage. Furthermore, for reasons such as stopping accuracy and shortening the sweep time, it is only possible to select stations on a specified channel basis, and it is not possible to adapt to destinations with different channel bases. On the other hand, automatic sweep tuning using a voltage synthesizer system can be adapted to all broadcast frequencies and can easily obtain the optimum tuning point, but compared to the PLL system, it has problems with reception stability. In view of the above, the present invention provides a novel electronic tuning device in which the channel selection operation is performed by a voltage synthesizer method using an S-curve signal indicating the tuning state of the received signal, and the reception operation is performed by a PLL synthesizer method. It is.

Hereinafter, an explanation will be given based on an example with reference to the drawings.

In FIG. 1, 1 is a general FM receiver. The signal received by the antenna 2 is amplified by a radio frequency amplifier 3, mixed with a signal from a local oscillation circuit 5 by a mixing circuit 4, and converted into an intermediate frequency signal. And the intermediate frequency signal is an intermediate frequency amplification circuit! 6, and further detected by a detection circuit 7, and then amplified by a low frequency amplification circuit 8 and sent to a speaker 9.
The sound is emitted through. Reference numeral 10 denotes a voltage generating means for generating a DC tuning voltage VT for controlling the local oscillation frequency, and is composed of a window comparator 11, a low-pass filter 12, and a constant current charge pump 13 for controlling charging and discharging of a capacitor in the low-pass filter 12. be done.

When the input voltage SOut becomes higher than the high threshold level (SHCA) of the window comparator 11, the DC tuning voltage V is lowered by discharging the capacitor, and when it becomes lower than the low threshold level (4), the capacitor is charged. By doing so, the DC tuning voltage ■τ is increased. 14 is a window comparator that generates the SH signal and SL signal as shown in FIG. 2 in response to the S curve signal inputted through the amplifier circuit 15; 16 is the H/L signal that controls the sweep speed; and the H/L signal that controls the sweep direction. a sweep control circuit that generates a three-value sweep signal of RHJrLJ to impedance J (hereinafter referred to as ROO.u) in response to a U/D signal to control the sweep operation and an SR signal to control the start and stop of the sweep operation; 1 is a control circuit, and 18 is an analog switch circuit.

Here, the high threshold level VSH (1) and the low threshold level SL (1) of the window comparator 14 are the high threshold level VsHCA) and the low threshold level VSL (4) of the window comparator 11. Compare, VsH(A)
is lower than ■, H(5), and V$L(A) is VSL(S)
set higher. Also, 19 is prescaler 2
0 and a gate circuit 21 to count the local oscillation frequency, and the division ratio data setting latch 2
By adding 2 and a frequency division detection circuit 23, it functions as a programmable divider during PLL loop operation.

Further, 24 is a frequency division ratio data conversion circuit that converts the contents of the up counter 19 into frequency division ratio data of the programmable divider, and 25 is a frequency division output signal from the frequency division detection circuit 23 and a reference signal from the timing generation circuit 26. 27 is a time base generation circuit that generates a time base for controlling the gate circuit 21.

Note that the output RHJ of the phase difference signal generation circuit 25 and the sweep control circuit 16 is set higher than (SHCA) of the window comparator 11, and the output r'Lj is set lower than (LCA). Next, the operation of the present invention will be explained based on FIG.

When the automatic sweep mode is set using the auto/manual changeover switch 28 and the up key 29, for example, is pressed among the up key 29 and the down key 30, the H/L signal, U/D signal, and SR signal from the control circuit 17 all become RHJ. Therefore, the sweep signal SOut becomes RL and a high-speed upward sweep is started (period t1).

After the period, when the S curve signal Sin becomes lower than (1), the window comparator 14 generates the SL signal,
The H/L signal is powered up and switched to LJ, and the sweep signal SOut intermittently repeats RLJ as shown at the beginning of FIG. 2, and is switched to low-speed up sweep (T2 period). Here, the low-speed sweep speed is proportional to the duty at which the sweep signal indicates RLJ.
For example, the period in which RLj is shown during one cycle is 115.
If so, the slow sweep speed becomes 115, which is the fast sweep speed. The sweep further progresses, and the S curve signal Sin changes to ■3H (5
), the control circuit 17 detects the SH signal generated from the window comparator 14 and outputs the SR signal.
The signal is set to RLJ and the sweep is stopped.

Next, the PLL loop can be operated to perform a reception operation, but in order to supplement the optimum tuning point for the lower layer, in this embodiment, the following MC operation is performed. That is,
The analog switch circuit 18 is turned on by the layer temperature signal (Fig. 2 C) from the control circuit 17, and the S curve signal S
in is now applied to the window comparator 11.

Since the input signal SOut of the window comparator 11 has the same potential as the S-curve signal Sjn, it instantaneously becomes RH and works to lower the DC tuning voltage. Since the high threshold level (4) of the window comparator 11 is set lower than the high threshold level (2, H, 5) of the window comparator 14, the input signal SOut is approximately (SHCA). As a result, as shown in period T3 in FIG. 2, the DC tuning voltage (2) is pulled down to the optimal tuning point for the saw layer when the sweep is stopped. On the other hand, the local oscillation frequency is counted by the up counter 19 at a predetermined time base via the prescaler 20 and the gate circuit 21 at the same time as the start of the sweep, converted into a reception frequency by the frequency conversion circuit 31, and displayed as a frequency by the frequency display device 32. Ru. Incidentally, an IF fine adjustment circuit 33 is added to the frequency conversion circuit 31 to correct deviations in the intermediate frequency due to variations in the ceramic filter or the like. By the way, the local oscillation frequency counted by the up counter 19 is converted into frequency division ratio data for the programmable divider by the frequency division ratio data conversion circuit 24 during the above-mentioned AFC operation period (period T3 in FIG. 2). The local oscillation frequency at the optimum tuning point will be converted to frequency division ratio data.

The frequency division ratio data obtained in this way is set in the up counter 19 via the frequency division ratio data setting latch 22, and the local oscillation frequency is divided according to this frequency division ratio data and the frequency division detection circuit 23 generates a frequency-divided output signal. Then, a phase difference signal corresponding to the frequency and phase difference between the frequency-divided output signal and the reference signal is applied from the phase difference signal generation circuit 25 to the window comparator 11, and the receiving operation is performed by the PLL operation as shown in period T4 in FIG. After the local oscillation frequency is locked, the MUTE signal (FIG. 2) is released and sound generation begins. Here, the division operation of the local oscillation frequency will be explained in more detail.

For explanation, the up counter 19 has a maximum count value of 29.
It is assumed that the value is set to 999 and is reset to 00000 with the next pulse.

Now, for example, the local oscillation frequency corresponding to the received broadcast frequency is 65.40r! 4HZ, the frequency division ratio of the prescaler is 11100, and the time base for controlling the gate circuit 21 is 10n1S, then 29999-6540=23459 is set in the up counter 19 as frequency division ratio data.

Therefore, when the up counter 19 counts the local oscillation frequency and is reset, the frequency division detection circuit 23 is configured to generate one frequency division output signal. The up-counter 19 used for the frequency division operation is also used as an up-counter for counting the local oscillation frequency in order to obtain frequency display and frequency division ratio data in order to simplify the circuit configuration. one
By the way, as shown in FIG. 3, the low-pass filter 12 is configured to turn off the switch 34 and change the time constant during PLL loop operation.

This is because a tamping resistor is inserted to converge the local oscillation frequency to a predetermined frequency during PLL operation. Further, after the layer temperature operation, a reception operation is normally performed using a PLL loop, but when a broadcast signal is present, it is also possible to continue the AFC operation and generate sound.

However, if there is no broadcast signal or if the broadcast radio waves become extremely weak, it is necessary to switch to a receiving operation using a PLL loop. Therefore, in the device of the present invention, the detection circuit 35
The SD signal indicating the presence or absence of a broadcast signal obtained from A
It also has a function of switching from FC operation to reception operation using a PLL loop. Next, manual sweep tuning and preset tuning will be explained (abbreviated). First, for manual sweep tuning, switch to manual sweep mode with the auto/manual changeover switch 28, and select the desired broadcast frequency while watching the frequency display device 32. This is done by continuously pressing the up key 29 or down key 30.

Also, when the up key 29 or down key 30 is lightly touched, the current receiving frequency is set to a predetermined channel base by the receiving frequency control circuit 36, for example, 0.1 MHz in the case of FM broadcasting.
is added or subtracted, and this reception frequency is converted to a corresponding local oscillation frequency by the frequency conversion circuit 31, and then converted to the division ratio data of the programmable divider by the frequency division ratio data conversion circuit 24, and the channel selection is performed by the PLL loop. It is done.

Furthermore, for preset tuning, the local oscillation frequency or frequency division ratio data of the optimum tuning point obtained as described above is stored in the memory key 37.
By pressing the channel key 38, the local oscillation frequency or frequency division stored in the channel memory 39 is stored in the channel memory 39 by pressing the desired channel key 38 when selecting a channel. The ratio data is read out, and in the case of a local oscillation frequency, the frequency division ratio data is selected to the programmable divider via the frequency division ratio data conversion circuit 24, thereby operating the second PLL loop and performing preset tuning. As mentioned above, the electronic tuning device of the present invention uses a voltage synthesizer method that uses an S curve signal to capture the correct tuning point during sweep tuning and to stop the sweep, so it has good tuning accuracy and can sweep all broadcast frequencies. Also, since the local oscillation frequency at the positive tuning point is converted into PLL loop frequency division ratio data and reception is performed using the PLL synthesizer method, highly stable reception is possible.

Furthermore, in sweep channel selection, the TS-
By performing the Fc operation, the optimum tuning point of the saw layer can be obtained.

Furthermore, if the present invention is applied, the correct tuning point can be easily selected using the PLL synthesizer method even during preset tuning.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an electronic tuning device according to the present invention, FIG. 2 is a characteristic diagram showing the tuning and reception process of the electronic tuning device according to the present invention, and FIG. 3 is a low-pass diagram in FIG. This is a specific circuit example of the filter 12. Explanation of main drawing numbers, 1...FM receiver, 10...
・Voltage generation means, 11...Window comparator, 12...Low pass filter, 13...
Constant current charge pump, 14...window comparator, 16...sweep control circuit, 17...
・Control circuit, 18... Analog switch circuit, 19... Up counter, 22...
... Frequency division ratio data setting latch, 23... Frequency division detection circuit, 24... Frequency division ratio data conversion circuit, 2
5... Phase difference signal generation circuit, 31... Frequency conversion circuit, 32... Frequency display circuit, 36...
...Reception frequency control circuit, 39...Preset memory.

Claims (1)

[Scope of Claims] 1. Voltage generating means for generating a DC tuning voltage for controlling the local oscillation frequency, and a sweep for performing sweep tuning by controlling the voltage generating means in response to a tuning instruction signal indicating the tuning state of the received signal. A PLL comprising a tuning control means, a frequency dividing means for dividing a local oscillation frequency, and a phase difference signal generating means for generating a signal according to the frequency and phase difference between the frequency divided output signal of the frequency dividing means and a reference signal. a loop, a counting means for counting the local oscillation frequency, and a converting means for converting the contents of the counting means at the optimum tuning point obtained by the sweep selection into frequency division ratio data of the frequency division means, After playing the game, the P
An electronic tuning device characterized in that a receiving operation is performed by operating an LL loop and applying the phase difference signal to the voltage generating means. 2. The electronic tuning according to claim 1, wherein the output stage of the voltage generating means is constituted by a low-pass filter, and when the PLL loop performs a receiving operation, the time constant of the low-pass filter is switched. Device. 3. In claim 1, there is provided a counter that sets the frequency division ratio data and divides the local oscillation frequency, a frequency division ratio data setting latch that sets the frequency division ratio data in the counter, and a frequency division ratio data setting latch that sets the frequency division ratio data in the counter; An electronic tuning device characterized in that said frequency dividing means is constituted by a frequency division detection circuit that generates said frequency divided output signal in response to said frequency division output signal, and said counter is also used as said counting means that counts a local oscillation frequency. 4. In claim 1, the sweep tuning control means includes an analog switch circuit connected to the voltage means and inputting the tuning instruction signal, and the sweep tuning control means includes:
An electronic tuning device comprising an AFC operation performed by turning on the analog switch circuit. 5. In claim 4, the input stage of the voltage generating means has a first threshold voltage and a second threshold voltage higher than the first threshold voltage. The input stage of the sweep tuning control means includes a second window comparator having a third threshold voltage and a fourth threshold voltage higher than the third threshold voltage. characterized in that the first threshold voltage is higher than the third threshold voltage, and the second threshold voltage is lower than the fourth threshold voltage. electronic tuning device. 6 In claim 4, the AFC is controlled by a signal indicating the presence or absence of a broadcast signal.
An electronic tuning device characterized in that the operation is switched to a reception operation using the PLL loop.