JPS5915143Y2 - Digital display switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching circuit between a received frequency display and a time display in a clock radio or a car stereo with a clock and radio.

When using a clock radio or a car stereo with a clock and radio, etc., to share the receiving frequency display and time display on one digital display, it is necessary to automatically and It is necessary to appropriately switch between frequency display and time display.

The purpose of this invention is to automatically display and display the receiving frequency digitally when it is necessary to know the receiving frequency, such as when turning on the power switch, performing a tuning operation, or changing the band. The object of the present invention is to provide a digital display switching circuit that displays the time digitally after maintaining the display for a certain period of time.

The feature of the present invention is that it has a PLL type receiving device,
The signal generated when the circuit becomes unlocked is delayed for a certain period of time by a delay circuit, so that the digital display that normally displays the time displays the reception frequency for the delay time.

According to the present invention having such characteristics, the PLL circuit becomes unlocked when it is necessary to know the receiving frequency, such as when turning on the power, selecting a station, or switching bands. The received frequency is automatically displayed digitally and this display is maintained for a certain period of time.
There is no need to perform a manual display switching operation, and there is no need to miss a display.

Furthermore, since the display automatically switches to the time display after a certain period of time has elapsed, the user has the advantage of being able to concentrate on channel selection, etc., without being distracted by the display switching operation.

Furthermore, the PLL circuit automatically issues an error signal when the lock is released, and the present invention displays a frequency based on the output of such an error signal. There is no need to provide a source, and the intended purpose can be achieved with a simple configuration.

Hereinafter, the present invention will be explained with reference to illustrated embodiments.

In FIG. 1, a high frequency amplifier 1, a mixer 2, an intermediate frequency amplifier 3, and a detector 4 constitute a well-known FM receiving circuit, and a high frequency amplifier 5 and a mixer 6, an intermediate frequency amplifier 7, and a wave detector 8 constitute a well-known AM receiving circuit.

The output signals of each of the detectors 4 and 8 are amplified by a low frequency amplifier 9 and then emitted as sound from a speaker 10.

Also, a phase detector 12 that compares the reference signal emitted from the reference signal oscillator 11 and the signal from the pregramma pull divider 15 and outputs a signal according to the phase difference between the two signals;
A low-pass filter 13 extracts a DC signal corresponding to this output, a voltage controlled variable frequency oscillator circuit 14 generates a signal with a frequency corresponding to this DC signal, and the frequency of the output signal of this circuit 14 is set by a control device 18 described later. A loop formed by the programmable divider 15 which divides the frequency at an appropriate frequency division ratio constitutes a well-known PLL circuit.

The output of the variable frequency circuit 14 is applied to a mixer 6 in the AM receiving circuit.

Further, the output of the filter 13 is applied to another voltage controlled variable frequency circuit 16, and the output of the same circuit 16 is applied to the mixer 2 in the FM receiving circuit, and also to the prescaler 17.
It is adapted to be added to the programmable divider 15 via the programmable divider 15.

Note that when the reception mode is AM, one variable frequency circuit 14 is inserted into the PLL circuit, whereas
When the reception mode is FM, the other variable frequency circuit 16 and prescaler 17 are inserted into the PLL circuit.

The control device 18 has, for example, a push button type channel selection operation section, and adds a signal corresponding to the selected push button to the programmable divider 15 to set the frequency division ratio of the divider, and also controls the switching circuit. The above signal is added to 19.

Further, a reference signal emitted from the reference oscillator 11 is applied to a clock device 20, and a count signal from the clock device 20 is applied to a switching circuit 19.

As is well known, the phase detector 12 in the PLL circuit is
When the circuit is unlocked, an error signal is automatically generated, and this error signal is sent to the delay circuit 2.
1 and then applied to the switching circuit 19 after being delayed for several seconds.

The switching circuit 19 allows the time measurement signal from the time measurement device 20 to pass in a normal state in which no signal is sent from the delay circuit 21, and allows the passage of the time measurement signal from the time measurement device 20 while the signal is sent from the delay circuit 21. It allows the passage of signals depending on the station.

The signal passed through the switching circuit 19 is applied to a digital display 22 for digital display.

Note that the control device 18, the switching circuit 19, and the timing device 20
It is convenient to use the circuit part consisting of the following, since it is commercially available in one package as an integrated circuit or a high-density integrated circuit.

Details of the phase detector 12 and delay circuit 21 in the PLL circuit are shown in FIG.

Terminal 12a in the phase detector 12 is an input terminal to which the signal from the programmable divider 15 is applied, terminal 1
2b is an input terminal to which the signal from the reference oscillator 11 is applied, and terminal 12C is the input terminal to which the signal from the divider 15 and the oscillator 1 are applied.
Terminal 12 d is an error signal output terminal that outputs a signal when the PLL circuit including phase detector 12 is unlocked, and terminal 12 e is a power supply. It is a terminal.

Since the configuration of the phase detector 12 is already well known, detailed explanation of the configuration will be omitted.

As shown in FIG. 2, the delay circuit 21 includes a backflow prevention diode D that receives the error signal from the error signal output terminal 12d of the phase detector 12, a protective resistor R1, and a resistor R2. Two inverters ■1. ■2. ■3 and
The output of the inverter 2 is connected to the second output terminal 21b, and is also connected to the input terminal of the inverter 11 via a feedback resistor R4. ing.

In addition, the connection point between the diode D and the resistor R1 is grounded via a normally open manual switch S, and the resistors R1 and R2
The connection point with is connected to the power supply via resistor R3, and
It is grounded via capacitor C.

The output terminals 21a and 21b of the delay circuit 21 are respectively added to the switching circuit 19 (see FIG. 1), and the output terminal 21a
When the output terminal 21b is at a high level, the switching circuit 19 allows the passage of the signal according to the channel selection from the control device 18, and when the output terminal 21b is at a high level, the switching circuit 19 allows the passage of the timing signal from the timing device 20. It is assumed that it is allowed.

Now, in the AM reception mode, when a desired broadcasting station is selected by pressing a button on the control device 18, a signal corresponding to the selected station is applied from the control device 18 to the divider 15, and the divider 15 responds to the signal. The frequency division ratio can be switched to the specified frequency division ratio.

As is well known, the PLL circuit including the divider 15 operates so that the voltage controlled oscillation circuit 14 oscillates a signal according to the frequency division ratio of the divider 15, and locks its operating mode when a predetermined oscillation frequency is reached. .

The signal of the variable frequency circuit 14 locked in this way is AM
It is added to the mixer 6 of the receiving circuit, and the AM receiving circuit selects a broadcasting station with a frequency that has a certain relationship with the output frequency of the voltage controlled oscillation circuit 14.

On the other hand, at the moment when the frequency division ratio of the divider 15 is switched, PL
Since the L circuit is unlocked, terminal 1 of the phase detector 12
An error signal is generated from 2d, and this error signal is applied to the delay circuit 21.

The signal at the terminal 12d of the phase detector 12 is always at a high level when the PLL circuit is locked, as shown in FIG.
As shown in the figure, it becomes low level momentarily.

Due to this low-level pulse signal, the charge in the capacitor C of the delay circuit 21 is discharged through the diode D and the resistor R1, and the terminal voltage of the capacitor C becomes low.

At this time, the forward resistance of capacitor C and diode D,
By selecting a small time constant of resistor R1, the terminal voltage of the capacitor quickly falls below the threshold level as shown in FIG.

Since the input terminal of the inverter 1 is connected to the capacitor C via the resistor R2, the output of the inverter 11 is at a high level, and the output of the inverter I2 is at a low level.

The output of inverter 2 is connected to inverter 1 via resistor R4.
1, and the output of inverter I2 is fixed at a low level. Therefore, the output of inverter I3
a becomes a high level, and the output 21b becomes a low level.

Therefore, the switching circuit 19 allows the signal from the control device 18 to pass through and causes the display 22 to digitally display the reception frequency.

Output 2 at the first pulse of the low level pulse error signal
After 1a and H121b are set to L until the next pulse enters the delay circuit 21, capacitor C is charged from the power supply via resistor R3, increasing the terminal voltage.
By selecting large charging time constants C and R of the capacitor C and resistor R3 as shown in FIG. 4, it takes time to reach the threshold level.

If a falling pulse of the error signal is input again before reaching the threshold level, it is discharged and becomes low level.

Due to this repetition, the threshold level is not reached while the error signal is being output.

When the tuning operation is finished and the PLL circuit is locked, the error signal disappears, so the terminal voltage of capacitor C increases, and when it reaches the threshold level, inverters II, I2. I
3, output 21 a to low level, output 21
Since the signal b is switched to high level, the switching circuit 19 allows the signal from the clock device 20 to pass through, causing the display 22 to digitally display the time.

Next, in the FM reception mode, when a desired broadcasting station is selected by pressing a button on the control device 18, the FM reception circuit operates in substantially the same manner as in the case of AM reception described above to select the desired broadcasting station. Play.

However, in the case of FM reception, a voltage controlled oscillation circuit 16 is installed in the PLL circuit instead of the voltage controlled oscillation circuit 14, and a prescaler 1 that divides the frequency of the output signal of the circuit at a fixed ratio.
7 is inserted, the frequency of the output of the voltage controlled oscillation circuit 16 in the case of FM reception is higher than the frequency of the output of the voltage controlled oscillation circuit 14 in the case of AM reception, and it is possible to adapt to differences in reception frequency bands. It looks like this.

Even when you select a channel in FM reception mode,
Since an error signal is generated at the terminal 12d of the phase detector 12 in the same way as when a channel selection operation is performed in the reception mode, the receiving side frequency is digitally displayed only during the channel selection operation and for a few seconds thereafter.

The time is displayed as described above under normal conditions without any channel selection operations, but there are times when you may want to check the frequency of a certain broadcasting station while it is being received. closes the switch S by manual operation.

Closing the switch S has the same result as adding an error signal to the delay circuit 21, so the terminal 21a of the delay circuit 21 becomes high level, and the display 22 indicates that the received frequency is digital as in the previous case. Is displayed.

When the switch S is released, the display returns to the time display after a few seconds.

The display for a few seconds during the tuning operation may be the frequency of the selected broadcasting station, a simple identification number if it is a preset type tuning device, or a channel number if it is a multi-channel transceiver. But that's fine.

In addition, by pressing the start button, the timing pulses are sequentially added and subtracted, and the added and subtracted values are used to select the divider 1.
The output frequency of the PLL circuit is continuously changed by continuously changing the frequency division ratio of 5, and the receiving frequency of the receiving circuit is continuously changed based on this, and by receiving any broadcast station, the PL
Even in the case of a so-called electronic tuner in which the frequency division ratio of the divider 15 in the L circuit is fixed and the above-mentioned broadcasting station is fixed as it is thereafter received, an error signal is output from the phase detector 12 during the channel selection operation. Based on this error signal, the received frequency can be digitally displayed during the tuning operation and for several seconds after tuning.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a part of the same embodiment in detail, and Figs. 3 and 4 are the same embodiments. FIG. 3 is a signal waveform diagram for explaining the operation of FIG. 12... Phase detector, 15... Programmable divider, 18... Control device, 19...
...Switching circuit, 20... Timing device, 21
...Delay circuit, 22...Display device.

Claims (1)

[Scope of utility model registration request] A phase-locked loop (hereinafter referred to as PLL) type receiving device, an electronic timekeeping device that measures time based on a reference signal, and a frequency tuning operation are used to control the P in the receiving device.
a delay circuit that detects an error signal automatically generated from the phase comparator when the LL circuit is unlocked and delays it for a certain period of time; and a delay circuit that allows the clock signal from the clock device to pass while the PLL circuit is locked; A digital display comprising a switching circuit that allows the reception frequency signal to pass while receiving the delayed signal from the delay circuit, and a display that digitally displays the time or reception frequency based on the signal that has passed through the switching circuit. switching circuit.