JPS6151542U - - Google Patents
Info
- Publication number
- JPS6151542U JPS6151542U JP10887985U JP10887985U JPS6151542U JP S6151542 U JPS6151542 U JP S6151542U JP 10887985 U JP10887985 U JP 10887985U JP 10887985 U JP10887985 U JP 10887985U JP S6151542 U JPS6151542 U JP S6151542U
- Authority
- JP
- Japan
- Prior art keywords
- pcm
- pcm signal
- polarity bit
- absolute value
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Complex Calculations (AREA)
Description
第１図は本考案によるＰＣＭ信号演算回路のブ
ロツク図、第２図は本考案によるＰＣＭ信号演算
回路の別の実施例のブロツク図、第３図は本考案
によるＰＣＭ信号演算回路の更に別の実施例のブ
ロツク図、及び第４図は本考案によるＰＣＭ演算
回路の更に別の実施例のブロツク図である。
１０，１１…入力端子、２０…出力端子、３０
…メモリ。
FIG. 1 is a block diagram of a PCM signal calculation circuit according to the present invention, FIG. 2 is a block diagram of another embodiment of the PCM signal calculation circuit according to the present invention, and FIG. 3 is a block diagram of yet another embodiment of the PCM signal calculation circuit according to the present invention. FIG. 4 is a block diagram of still another embodiment of the PCM arithmetic circuit according to the present invention. 10, 11...input terminal, 20...output terminal, 30
…memory.
補正 昭６０．８．１６
考案の名称を次のように補正する。
考案の名称 ＰＣＭ信号乗除算装置
実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。Amendment August 16, 1980 The name of the invention is amended as follows. Title of the invention: PCM signal multiplication/division device The scope of the utility model registration claims and the brief description of the drawings are amended as follows.
【実用新案登録請求の範囲】
２つの非線形ＰＣＭ信号を乗除算する装置にお
いて、入力ＰＣＭ信号の絶対値のすべての組み合
わせについての演算結果を記録したデイジタルメ
モリと、入力ＰＣＭ信号の極性ビツトの排他的論
理和を求める排他的論理和回路とを設け、入力Ｐ
ＣＭ信号の内極性ビツトを除いた絶対値部分を組
み合わせてアドレス情報として前記メモリ内容を
読み出すことにより演算結果の絶対値部分を得、
この演算結果の絶対値部分に前記排他的論理和回
路の出力を極性ビツトとして付加して出力するこ
とを特徴とするＰＣＭ信号乗除算装置。[Claims for Utility Model Registration] A device for multiplying and dividing two nonlinear PCM signals, comprising a digital memory that records calculation results for all combinations of absolute values of input PCM signals, and exclusive polarity bits of input PCM signals. An exclusive OR circuit for calculating a logical sum is provided, and an input P
Obtaining the absolute value portion of the calculation result by combining the absolute value portions of the CM signal excluding the inner polarity bits and reading out the memory contents as address information;
A PCM signal multiplication/division device characterized in that the output of the exclusive OR circuit is added to the absolute value portion of the operation result as a polarity bit and outputted.
【図面の簡単な説明】
第１図は本考案による装置の動作原理を示すブ
ロツク図、第２図は本考案によるＰＣＭ信号乗除
算装置の実施例を示すブロツク図である。
１０，１１…入力端子、２０…出力端子、３０
，４０…メモリ、４１…排他的論理和回路。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the operating principle of the device according to the present invention, and FIG. 2 is a block diagram showing an embodiment of the PCM signal multiplication/division device according to the present invention. 10, 11...input terminal, 20...output terminal, 30
, 40...Memory, 41...Exclusive OR circuit.
Claims (1)
算が乗算および除算の場合、入力ＰＣＭ信号の絶
対値のすべての組み合わせについての演算結果を
記録したデイジタルメモリを設け、入力ＰＣＭ信
号の内極性ビツトを除いた絶対値部分をアドレス
情報として前記メモリの内容を読み出すことによ
り前記演算結果の絶体値部分を得、入力ＰＣＭ信
号の極性ビツトの論理処理により前記演算結果の
極性ビツト部分を得ることを特徴とするＰＣＭ信
号演算装置。 In a device that calculates nonlinear PCM signals, when the calculations are multiplication and division, a digital memory is provided that records the calculation results for all combinations of absolute values of the input PCM signal, and the absolute value of the input PCM signal excluding the inner polarity bit is A PCM characterized in that the absolute value part of the calculation result is obtained by reading the contents of the memory using the value part as address information, and the polarity bit part of the calculation result is obtained by logical processing of the polarity bit of the input PCM signal. Signal calculation device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10887985U JPS6151542U (en) | 1985-07-18 | 1985-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10887985U JPS6151542U (en) | 1985-07-18 | 1985-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6151542U true JPS6151542U (en) | 1986-04-07 |
Family
ID=30668051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10887985U Pending JPS6151542U (en) | 1985-07-18 | 1985-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151542U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5386135A (en) * | 1977-01-07 | 1978-07-29 | Nippon Hoso Kyokai <Nhk> | High-speed multiplier |
-
1985
- 1985-07-18 JP JP10887985U patent/JPS6151542U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5386135A (en) * | 1977-01-07 | 1978-07-29 | Nippon Hoso Kyokai <Nhk> | High-speed multiplier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6151542U (en) | ||
| JPS6151543U (en) | ||
| JPS59122642U (en) | linear multiplier | |
| JPS60166048U (en) | multiplication circuit | |
| JPS6119859U (en) | diagnostic circuit | |
| JPS6140038U (en) | phase comparator | |
| JPS62127599U (en) | ||
| JPS6056098U (en) | Reverberation adding device with analog mixer circuit | |
| JPS6140635U (en) | Temperature detection signal input circuit | |
| JPS5963742U (en) | Computer input/output device | |
| JPS60127099U (en) | Sound addition device | |
| JPS6370732U (en) | ||
| JPS5897799U (en) | Sampling hold circuit | |
| JPS5963513U (en) | Detection circuit | |
| JPS61139030U (en) | ||
| JPS5871846U (en) | digital multiplication circuit | |
| JPS5866713U (en) | amplifier | |
| JPH0163225U (en) | ||
| JPS58185000U (en) | stereo wide circuit | |
| JPS5980858U (en) | square root calculator | |
| JPS59152811U (en) | power amplifier | |
| JPS5873614U (en) | Amplifier | |
| JPS60636U (en) | multiplication circuit | |
| JPS58124895U (en) | Alarm signal holding circuit | |
| JPS61192349U (en) |