JPS6150376A - Semiconductor device and integrated circuit thereof - Google Patents

Semiconductor device and integrated circuit thereof

Info

Publication number
JPS6150376A
JPS6150376A JP60171373A JP17137385A JPS6150376A JP S6150376 A JPS6150376 A JP S6150376A JP 60171373 A JP60171373 A JP 60171373A JP 17137385 A JP17137385 A JP 17137385A JP S6150376 A JPS6150376 A JP S6150376A
Authority
JP
Japan
Prior art keywords
region
semiconductor region
thin film
semiconductor
opposing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60171373A
Other languages
Japanese (ja)
Other versions
JPH0481354B2 (en
Inventor
Yutaka Hayashi
豊 林
Hidekazu Suzuki
英一 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60171373A priority Critical patent/JPS6150376A/en
Publication of JPS6150376A publication Critical patent/JPS6150376A/en
Publication of JPH0481354B2 publication Critical patent/JPH0481354B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/88Tunnel-effect diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To effect the implantation from the opposite region to the semiconductor region effectively by selecting the material in which the barrier of thin film seen from the semiconductor is high for the carrier of opposite polarity to that of the main carrier and the barrier of thin film seen from the opposite region is lower for the main carrier. CONSTITUTION:When a metallic thin film, e.g., of aluminum as an opposite region 10, an insulating film, e.g., clean SiO2 film of about 30Angstrom as a thin film 1, and Si single crystal including phosphorus atoms of 10<17> pieces/cm<3> as a semiconductor region are used, the positive holes produced by the high-energy carriers implanted from the opposite region 10 are gathered by the p type semiconductor region 101B which is arranged within the reach distance of diffusion drift of the holes with being in contact with the n type semiconductor region 100. Consequently a positive potential can be taken out from the region 101B altough a negative bias has been applied to the opposite region 10. In addition to the functions of light accepting and emitting, thus the device can be used at the same time for the power source being capable of reversal of polarity and comprising the characteristics shown in the figure.

Description

【発明の詳細な説明】 本発明は直接トンネル、ファウラー・ノルドハイムトン
ネル、トラップ準位を介した伝導。
DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to direct tunneling, Fowler-Nordheim tunneling, and conduction through trap levels.

等キャリアが禁制帯内を少なくとも一部通り抜けるで以
後総合的にトンネルという言葉で代表させる。)程薄い
膜厚を有し、かつ、広い禁制帯幅を有する半導体薄膜又
は絶縁性薄膜を介して、導電性の対向領域から上記薄膜
よりは禁制帯幅の小さい半導体へキャリアの注入を行い
、半導体領域表面で電子・正孔対を発生させ、発光およ
び受光とそれに伴う増幅、スイッチ、発振、電圧又は電
流の発生、負性抵抗の発生等の光′を素子及びその複合
機能を行う半導体デバイス及びその集積回路に関するも
のτおる。
The term "tunnel" will be used to refer to the term "tunnel" in which a carrier passes through at least part of the forbidden zone. ) Injecting carriers from a conductive opposing region into a semiconductor having a narrower bandgap than the thin film through a semiconductor thin film or an insulating thin film having a relatively thin film thickness and a wide bandgap, A semiconductor device that generates electron-hole pairs on the surface of a semiconductor region and performs light emission and light reception, accompanying amplification, switching, oscillation, voltage or current generation, negative resistance generation, etc., and its multiple functions. and related to its integrated circuits.

従来のpn接合において、一方の領域にキャリアの注入
が効率よく行なわれる条件は、接合を形成するpn両方
の領域について欠陥及びトラソフ准位カニ少ない等の結
晶性が良好でおること、しかも不純物濃度関係が限定さ
れ注入を受ける方の領域の不純物濃度は他方の領域に比
べて一桁以上低いこと等の制限がち)、必ずしもデバイ
ス設計において各部分の抵抗、容量まで含め1考えた場
合の最適な設計が行なわれてはいなd−った。また、半
導体表面に直接注入を行なったわ、頁に注入したキャリ
アが半導体表面で電子・正孔対を発生嘔せて、発光した
シ、入射光で前記注入キャリアの注入を促進した夛、更
に少ない領域の数で有用な機能を実現したシ、新し一動
作を行なうデバイスを実現することは困難であった。
In a conventional p-n junction, the conditions for efficient carrier injection into one region are that both p-n regions forming the junction have good crystallinity, with few defects and Torasov level crabs, and that the impurity concentration is low. (The relationship tends to be limited and the impurity concentration in the region receiving implantation is an order of magnitude lower than that in the other region.) However, when designing a device, it is not always the best to consider the resistance and capacitance of each part. No design had been done. In addition, when direct injection was performed on the semiconductor surface, the carriers injected into the surface generated electron-hole pairs on the semiconductor surface and emitted light, and the injection of the injected carriers was promoted by incident light. Although useful functions were achieved with a small number of areas, it was difficult to realize a device that performed a new operation.

本発明はこれら従来の欠点を除去し、新しいデバイスの
提供を目的とする。このために、本発明では薄膜を介し
たキャリアの注入と、注入されたキャリアが半導体表面
で電子・正孔対を発生させることをデバイスの動作原理
として用いる。この薄膜がキャリアの直接トンネルまた
は間接トンネル等バルク材料から予測される量よ)厚さ
が薄いために大きな量のキャリア輸送力可能な程薄く、
しかもキャリア注入を受ける半1導体よりも禁制帯幅が
大きければ、注入を受けする半導体の不純物濃度又は対
向領域からの電ブによって誘起されたキャリア濃度が犬
きくでも薄膜を介した対向領域−半導体領域間で主とし
て輸送されるキャリア(以後主キャリアと称する)の導
電形を半導体のキー? IJア濃度に関係なく設定でき
る。すなわち、半導体からみた薄膜がより低い材料関係
を選ぶことによって、!突内領域から半導体領域への注
入を効率よ< d−tうことができる。また、このよう
な材料関係1“用いなくても、この薄膜を輸送されるキ
ャリアが主として単一のキャリアであるような薄膜を選
択するか又は対向領域を薄膜中を輸送したいジャリアの
極性を有する導電形の半導体領域で形成すれば、本発明
の目的を達することができる。このような構成によれば
、薄膜および対向領域は必ずしも結晶性の良好な単結晶
である必要はなく、多結晶でもアモルファスでもよい。
The present invention aims to eliminate these conventional drawbacks and provide a new device. To this end, the present invention uses injection of carriers through a thin film and generation of electron-hole pairs on the semiconductor surface by the injected carriers as the operating principle of the device. This thin film is thin enough to allow a large amount of carrier transport force due to its thin thickness (as expected from the bulk material, such as direct or indirect tunneling of carriers).
Moreover, if the forbidden band width is larger than that of the semiconductor conductor receiving carrier injection, even if the impurity concentration of the semiconductor receiving injection or the carrier concentration induced by the electric current from the opposing region is small, there is a gap between the opposing region and the semiconductor through the thin film. Is the conductivity type of carriers mainly transported between regions (hereinafter referred to as main carriers) the key to semiconductors? Can be set regardless of IJA concentration. In other words, by choosing a material relationship that has a lower thin film as seen from the semiconductor,! Injection from the inner region to the semiconductor region can be efficiently performed. In addition, even if you do not use such material relationship 1, select a thin film such that the carriers transported in this thin film are mainly single carriers, or have the opposite region have the polarity of the jaria that you want to transport in the thin film. The object of the present invention can be achieved by forming a conductive type semiconductor region.According to such a structure, the thin film and the opposing region do not necessarily have to be a single crystal with good crystallinity, but can also be polycrystalline. It may be amorphous.

勿論、対向領域は金属電極でもよく、薄膜はS、02等
の絶縁膜でもよい。
Of course, the opposing region may be a metal electrode, and the thin film may be an insulating film such as S or 02.

1以下、具体例を通して本発明の詳細な説明紀行なう。Hereinafter, the present invention will be explained in detail through specific examples.

一1第1図は本発明の実施例を示し、100は注入を受
ける半導体領域、1は禁制帯幅の大きい材料の薄膜、1
0は対向領域である。第1図(b)は(α)に断面図を
示したデバイスのバンドダイアグラム例を示し、対向領
域10と半導体領域の間で主として電子が輸送される場
合を示す。以下の実施例においても薄膜を輸送される主
キャリアを電子と仮定して説明を行なうが、主キャリア
が正孔の場合は注入を受ける半導体および対向領域が半
導体でおる場合は対向領域の導電形を含めてpn関係を
逆にすればよい。
11 FIG. 1 shows an embodiment of the present invention, in which 100 is a semiconductor region to be implanted, 1 is a thin film of a material with a large forbidden band width, 1
0 is the opposing area. FIG. 1(b) shows an example of a band diagram of the device whose cross-sectional view is shown in (α), and shows a case where electrons are mainly transported between the facing region 10 and the semiconductor region. The following examples will also be explained assuming that the main carriers transported through the thin film are electrons, but if the main carriers are holes, the semiconductor receiving injection and the opposing region are semiconductors, the conductivity type of the opposing region will be explained. The pn relationship may be reversed by including .

第1図(a)に示す断面構造において、薄膜1がトンオ
ル電流を流すけれども対向領域10の電位を半導体領域
100に対して半導体領域100の禁制帯幅Eoの電圧
換算値よりも大きい値(トンイ・ルするキャリアが電子
である場合は負側に)と    1、シ1でも破壊の生
じない程度の妥当な電流を流す程i度の厚さである場合
は、第1図(b)のバンドダイアグラムに示すように対
向領域10を半導体領域100の伝導帯よりも禁制帯幅
の電圧換算値分板上にバイアスすると、トン坏ル注入さ
れた電子は高エネルギー状態(e町にあり半導体領域1
00表面近くで電子・正孔対を生成することができる。
In the cross-sectional structure shown in FIG. 1(a), although the thin film 1 allows a certain amount of current to flow, the potential of the opposing region 10 is set to a value larger than the voltage conversion value of the forbidden band width Eo of the semiconductor region 100 with respect to the semiconductor region 100.・If the carriers flowing are electrons, then on the negative side) and 1, if the thickness is i degrees that allows a reasonable current to flow without causing destruction, the band in Figure 1 (b) As shown in the diagram, when the opposing region 10 is biased above the conduction band of the semiconductor region 100 and above the voltage-equivalent value of the forbidden band width, the injected electrons are in a high energy state (in the e town and in the semiconductor region 1
Electron-hole pairs can be generated near the 00 surface.

生成した正孔は半導体領域100の表面に集められ、半
導体領域]00がn形である場合は表面空乏層幅が小さ
くなるのでますます対向領域10からの電子の注入が促
され、オン状態となる。
The generated holes are collected on the surface of the semiconductor region 100, and when the semiconductor region 00 is n-type, the width of the surface depletion layer becomes smaller, which further promotes the injection of electrons from the opposing region 10, resulting in an on state. Become.

この結果、第1図(e)に示すような電IAw制御形の
負性抵抗が得られる。第1図(b)においてノ5ンドダ
イアグラムaは電子・正孔対発生以前の状態を示し、バ
ンドダイアグラムbは発生した正孔が表面に蓄積されて
同一電流を流すために必要が電圧が少なくてもよいこと
を示す。
As a result, an electric IAw control type negative resistance as shown in FIG. 1(e) is obtained. In Figure 1(b), band diagram a shows the state before the generation of electron-hole pairs, and band diagram b shows that the generated holes are accumulated on the surface and that less voltage is required to flow the same current. Indicates that it is acceptable.

第1図の具体例の実験結果の一例を次に述べる。対向領
域10として金属薄膜−たとえばアルミニウム、薄膜1
とし上絶縁膜−たとえば30A前後の清浄な5ift膜
、半導体領域として1011個/C’11”の燐原子を
含むSt単結晶を用いたとき、第1−59 (c)に示
された負性抵抗特性のブレークオー/(ヨ電圧V、は一
4V〜−5V、保持電圧vHは−3,1〜43.2v、
保持電流密度(−保持電流II/デ・くイモ面積)は約
2μA/、、lであった。又この実験サンプルの対向領
域を半導体領域に対して−3,2vから一4vの間にバ
イアスし、発光ダイオード又は約500mW タングス
テンランプの光をノくルス状に入射するとオフ状態から
オン状態に遷移する。この状態はバイアス電圧を保持電
圧vhよりロボルト側に変化させなければ光を取去った
後も持続した。この実験例は本発明によれば、簡単な構
造で光スィッチを実現可能であることを実証している。
An example of experimental results for the specific example shown in FIG. 1 will be described next. Metal thin film, for example aluminum, thin film 1 as counter region 10
When using a top insulating film - for example, a clean 5ift film of around 30A, and a St single crystal containing 1011/C'11" phosphorus atoms as the semiconductor region, the negative polarity shown in No. 1-59 (c) Resistance characteristic break-o/(Yo voltage V, -4V to -5V, holding voltage vH -3.1 to 43.2V,
The holding current density (-holding current II/de cuimo area) was about 2 μA/.l. Furthermore, when the opposing region of this experimental sample is biased between -3.2 V and -14 V with respect to the semiconductor region, and light from a light emitting diode or about 500 mW tungsten lamp is incident in a spiral pattern, the state transitions from the OFF state to the ON state. do. This state continued even after the light was removed unless the bias voltage was changed to the lower voltage side than the holding voltage vh. This experimental example demonstrates that according to the present invention, it is possible to realize an optical switch with a simple structure.

半導体領域100がGaAs、 Gap、 Inp、 
GILXAII−LAS。
The semiconductor region 100 is made of GaAs, Gap, Inp,
GILXAII-LAS.

GaAsxP+−xのような発光性物質の場合は、高エ
ネルギーキャリア(e町がエネルギーを失う時 又電子
・正孔対を発生した場合は正孔が表面で再結合して消滅
する時に発光を得ることができる。
In the case of a luminescent material such as GaAsxP+-x, when high-energy carriers (e) lose energy, or when electron-hole pairs are generated, light is obtained when the holes recombine on the surface and disappear. be able to.

−1のような非発光性の物質でも高エネルギーキャリア
による電子・正孔対の発生Fi種々のデパ刊スの動作原
理として用いることができる。
Even a non-luminescent substance such as Fi-1 can be used as the operating principle of various electronic devices, in which electron-hole pairs are generated by high-energy carriers.

−第2図はその具体例の1つで、対向領域10から注入
された高エネルギーキャリアによって発生した正孔を、
n形半導体領域100に接して正孔の拡散又はドリフト
による到達距離以内に設けられたp形半導体領域101
Bで集めると、対向領域10に負バイアスを印加したに
も拘らず領域101Bからは正電位を取シ出すことがで
きる。要するに受光・発光作用の他に同時に第3図に示
すような特性を有する極性反転をした電源としても用い
ることができる。これは集積回路等において極性の異シ
るバイアスを得るのに好都合である。なお第2図におい
て領域101Bは一般的には半導体領域100と整流性
接合を有すればよく、異なるれ料で構成でれることがで
きる。第4図はこの応用の具体例を示す。図に示すよう
に高不純物濃度n影領域100b上に10′〜1016
のオーダーのn影領域100aを形成した基板表面中に
pチャ坏ル給縁ゲートトランジスタとp形ベースを持つ
マルチコレクタのnp!1バイポーラトランジスタを同
時に作シ込むことができるがこの−1つの素子を同一基
板内で同時に動作させるた創には負電源と正電源が必要
となる。ところが」1図に示した本発明の具体例を更に
応用すれば、必要な外部電源は一8類ですますことがで
きる。断面図(α)において、領域110 、 111
はそれぞれ絶縁ゲートトランジスタのソースおよびトレ
イン傾城を示し、112は絶縁ゲートを示し、113は
ゲート絶縁膜を示す。領域10Fi対向領域、1は薄膜
、l0IBは薄膜lをトン坏ル等で通過して来た高エイ
・ルギーキャリアによって値域100α表面で発生した
少数キャリアを収集する領域であり薄膜lと半導体領域
100aの接合面から少数キャリアの到達範囲内に設け
られる。、領域1nIBは領域100aの逆導電形の領
慧で、本へ体例ではp形である。領域104A 、!:
 104Bは領域101B中に形成された領域101B
、とは逆4電形の領域で、npnトランジスタのマルチ
コレクタを形成する。上−記npn )ランジスタのベ
ースは前述のキャリア収集領域101Bと共通で、エミ
ッタは基板1()0α。
- Figure 2 shows one of the specific examples, in which holes generated by high-energy carriers injected from the opposing region 10 are
A p-type semiconductor region 101 provided in contact with the n-type semiconductor region 100 and within the reachable distance due to hole diffusion or drift.
When collected at B, a positive potential can be extracted from the region 101B even though a negative bias is applied to the opposing region 10. In other words, in addition to receiving and emitting light, it can also be used as a power source with reversed polarity having the characteristics shown in FIG. This is convenient for obtaining biases with different polarities in integrated circuits and the like. In FIG. 2, the region 101B generally only needs to have a rectifying junction with the semiconductor region 100, and can be made of a different material. Figure 4 shows a concrete example of this application. As shown in the figure, on the high impurity concentration n shadow region 100b, 10' to 1016
np! of a multi-collector with a p-type base and a p-type gate transistor in the substrate surface forming an n-shaded region 100a of the order of . Although one bipolar transistor can be fabricated at the same time, a negative power source and a positive power source are required to operate one bipolar transistor at the same time on the same substrate. However, if the specific example of the present invention shown in Figure 1 is further applied, the required external power source can be reduced to Category 18. In the cross-sectional view (α), regions 110 and 111
indicate the source and train slopes of the insulated gate transistor, respectively, 112 indicates the insulated gate, and 113 indicates the gate insulating film. Region 10Fi is the opposing region, 1 is the thin film, and 10IB is the region that collects minority carriers generated on the surface of the value range 100α by high energy energy carriers that have passed through the thin film 1 with a ton or the like. is provided within the reach of minority carriers from the junction surface of. , region 1nIB is of the opposite conductivity type to region 100a, and is p-type in this example. Area 104A,! :
104B is a region 101B formed in the region 101B.
, are regions of inverse quadruplicity, forming a multi-collector of npn transistors. The base of the above-mentioned npn) transistor is common to the carrier collection region 101B described above, and the emitter is the substrate 1()0α.

1qobで形成でれている。同図中、CT+1示した部
分は(b)図の等価回路(CT+)に示すように対向領
域10に負バイアスを印加した動作するnpn )ラン
ジスタ出力の増幅回路又は論理回路となる。
It is formed in 1 qob. In the figure, the portion indicated by CT+1 is an amplifier circuit or a logic circuit for the output of an NPN transistor which operates with a negative bias applied to the opposing region 10, as shown in the equivalent circuit (CT+) of FIG.

一方艶と示した部分は、(b)図の等価回路に示すよう
にpチャネル絶縁ゲートトランジスタであシ、負バイア
スで動作する回路素子として用いることができる。従っ
て、本発明を用いれば、従来両極性の2つの電源が必要
であった集積回路を1つの電源で動作させることができ
るようになる。なお、(b)図の等価回路に訃いて、各
端子に示されている符号Fi<a)図の電極又は領域か
ら引き出された端子であることを示す。更に第4図でに
高エネルギー電子によって発生した正孔を集め乙領域と
バイボー2トランジスタのべ一2領域とが共通であシ、
本発明の光電素子を含んだ高密度な集積回路が実現され
る。
On the other hand, as shown in the equivalent circuit of FIG. 13(b), the portions marked with gloss are p-channel insulated gate transistors, which can be used as circuit elements that operate with a negative bias. Therefore, by using the present invention, an integrated circuit that conventionally required two bipolar power supplies can be operated with a single power supply. In addition, referring to the equivalent circuit in figure (b), the symbol Fi<a) shown on each terminal indicates a terminal drawn out from the electrode or region in figure (b). Furthermore, in Fig. 4, the region B, which collects holes generated by high-energy electrons, and the two regions of the Bibo 2 transistor are common.
A high-density integrated circuit including the photoelectric device of the present invention is realized.

第4図(α)において点線で示すようにチャネル領域1
05A、 105Bを作れば、領域101Bは俳域(1
00a+100b)をソース領域、 104A、 10
4Bをドレインとする電界効果トランジスタのゲートと
しても犠能し、正孔収集領域と共通に作ることができ欄
。この場合は領域101Bはp形半導体ではなく重も、
整流接合を領域1001!との間に形成する物質(金属
又は100aとヘテ0接合を形成する半導体)でよい。
Channel region 1 as shown by the dotted line in Figure 4 (α)
If you create 05A and 105B, area 101B will become a haiku area (1
00a+100b) as the source region, 104A, 10
It also functions as a gate of a field effect transistor with 4B as the drain, and can be made in common with the hole collection region. In this case, the region 101B is not a p-type semiconductor but also a heavy semiconductor.
Rectifying junction area 1001! (a metal or a semiconductor forming a heterojunction with 100a) may be used.

この集積回路を直結形の論理回路として動作させるため
には、ゲート領域101Bとソース値域(100a +
 100b )とが0バイア)fもチャネル領域が空乏
しているようなチャネルの不純物濃度7寸法関係が選ば
れる。
In order to operate this integrated circuit as a direct-coupled logic circuit, the gate region 101B and the source range (100a +
A channel impurity concentration 7-dimensional relationship is selected such that the channel region is depleted.

第5図は2本発明の他の実施例であシ、第1図における
半導体値域100を薄膜1を通過する主キャリアと同一
導電形の領域102と、それに接し逆導電形の領域10
1によって構成する。薄illは領域101に接して設
ける。このlfr面得面側4例全第5 リアが電子である場合のバンドダイアグラムを(b)に
示す。領域102と対向領341oの間にバイア1を印
加し 対向領域10から主キャリアが薄膜・1−1を通
して、半導体領域101に注入さ八る方向Lヒし;イア
スを増加して行くと、対向領域100工坏ルキーレペル
と領域1°01のバンド端の差が領域101の禁制帯幅
よりも大きくなると注入された生キャリアにより電子・
正孔対が発生し主キャリアと逆極性のキτリアによって
、領域101は領域102に対してバンドダイアグラム
(b)で示されるように逆バイアス状態であったものが
充電さnて行さ、零バイアスに近くなる。これによって
、薄膜1の電界は強められるので、ますます高エネルギ
ーキャリアは注入さ九る。この時、薄[1と領域102
にはさiれた領域101の距離が、薄M1の主キャリア
の拡散又はドリフトによる到達距離以内にあれば、領域
】0】に注入された主キャリア(領域101−に訃いて
は少数キャリアである)は102に到達し、その結釆、
第5図の構造で一度電子・正孔の発生が行なわれると大
きな電流が対向−領域10と領域102の間に流nる。
FIG. 5 shows two other embodiments of the present invention, in which the semiconductor range 100 in FIG.
Consisting of 1. The thin ill is provided in contact with the region 101. The band diagram in the case where all the 5th rears in the four cases on the lfr surface and surface side are electrons is shown in (b). Via 1 is applied between the region 102 and the opposing region 341o, and the main carriers from the opposing region 10 are injected into the semiconductor region 101 through the thin film 1-1 in the direction L; When the difference between the band edges of region 100 and the region 1°01 becomes larger than the forbidden band width of region 101, electrons and
Hole pairs are generated, and the region 101, which was in a reverse bias state with respect to the region 102, is charged by the carrier having the opposite polarity to the main carrier, as shown in the band diagram (b). Close to zero bias. As a result, the electric field in the thin film 1 is strengthened, so that more and more high-energy carriers are injected. At this time, thin [1 and area 102
If the distance between the regions 101 and 1 is within the reach of the main carriers of the thin M1 due to diffusion or drift, the main carriers injected into the region 0] (minority carriers in the region 101-) ) reaches 102, and the conclusion is,
Once electrons and holes are generated in the structure shown in FIG. 5, a large current flows between the opposing regions 10 and 102.

従って、領域101から外部端子を耶り出さなければ光
入力で制御できる電流制御形の負性抵抗又はスイッチ特
性を示す光1!素子を得ることができるし、領域101
から端子101Eを出゛にばこれを上記素子の制御端子
として用いるこ1とができる他、領域102をコレクタ
、領域101委゛ベース、対向領域10をエミッタとす
る負性入力インピーダンスを有する発光又はホト)ラン
ジスタを得ることができる。上記の説明で領域102は
半導体領域101と整流接合を有すればよく異なる材質
でもよい。以上の動作原理の説明は、第4図の素子にも
対向領域10から高エネルギーキャリアが注入される場
合に適用でき、この場合は領域101Bはスイッチング
特性の制御端子とも、発光又はホトトランジスタのベー
ス接続端子ともなるベース接続領域が負性入力インピー
ダンスを示し、?i向領領域10エミッタ、半導体領域
102がコレクタとなる。
Therefore, if the external terminal does not extend from the region 101, the light 1! exhibits a current-controlled negative resistance or switch characteristic that can be controlled by optical input! The element can be obtained and the region 101
If the terminal 101E is outputted from the terminal 101E, it can be used as a control terminal for the above-mentioned element, and can also be used as a light-emitting or photo) transistors can be obtained. In the above description, the region 102 may be made of a different material as long as it has a rectifying junction with the semiconductor region 101. The above explanation of the operating principle can also be applied to the device shown in FIG. 4 when high energy carriers are injected from the opposing region 10. In this case, the region 101B is also the control terminal for switching characteristics, and the base of the light emitting or phototransistor. The base connection area, which also serves as the connection terminal, exhibits negative input impedance, and? The i-directed region 10 serves as an emitter, and the semiconductor region 102 serves as a collector.

次に、第5図光電素子を用いた集積回路の例を述べる。Next, an example of an integrated circuit using the photoelectric element shown in FIG. 5 will be described.

第6図Fi第5図の素子をメモリセルに用いた場合の具
体例で、(a)#′i断面図(b)は等価〕路、(e>
 Fiその動作波形を示す。図において領域1102は
半導体基板として用いられておシ、領・城)102と逆
導電形の領域101は絶縁ゲート電界11トランジスタ
のドレインと共通領域となっている。対向領域10は配
線10Eを介して抵抗性素子Rと接続され、Rの他端は
電源電圧vbtlに接続されている。絶縁ゲート電界効
果トランジスタ(IGFET >)絶縁ゲート112は
X線に接続され、IGFETのソース領域110はY線
に接続されマトリ7クス上のメモリアレイのXY番地と
して選択されるようになっている。このセルの動作を以
下に説明する。まずIGFETを簡単のためにpチャネ
ルを仮定する。この場合は薄膜lはトンネル可能な薄い
(30A〜50A程度)SiOzで、全壁ならばタング
ステン等の不純物をドーピングしたもので構成され、 
10は金属薄膜でもよいし、5hoz等の広いバンドギ
ャップのn形半導体ならば更に効果を有する。まず、領
域101の電位が基板102に対して、よりミ原電圧側
にある場合を’1’、!、!り基板電圧側にある場合を
10′とする。
FIG. 6 Fi is a specific example when the device shown in FIG. 5 is used in a memory cell.
Fi shows its operating waveform. In the figure, a region 1102 is used as a semiconductor substrate, and a region 101 of the opposite conductivity type to the region 1102 is a common region with the drain of the insulated gate electric field transistor 11. Opposing region 10 is connected to resistive element R via wiring 10E, and the other end of R is connected to power supply voltage vbtl. Insulated Gate Field Effect Transistor (IGFET>) The insulated gate 112 is connected to the X-ray, and the source region 110 of the IGFET is connected to the Y-line to be selected as the XY address of the memory array on the matrix 7. The operation of this cell will be explained below. First, it is assumed that the IGFET is a p-channel for simplicity. In this case, the thin film 1 is made of thin SiOz (approximately 30A to 50A) that can be tunneled, and if it is a full wall, it is made of a material doped with impurities such as tungsten.
10 may be a metal thin film, or it will be more effective if it is an n-type semiconductor with a wide bandgap such as 5 hoz. First, if the potential of the region 101 is closer to the voltage source than the substrate 102, it is set to '1'! ,! The case where the voltage is on the substrate voltage side is set as 10'.

′O′書込みはまずIGFETのゲートに適当なる負電
圧を与え、ソースに基板により近い電圧を与えると、領
域101もソースの電圧と近い値の電圧に一俸る。領域
10と薄膜1と領域101と領域102で構成される大
発明の素子において、対向領域41と領域101との間
に大きな電圧が印加されることになるので、対向領域1
0から注入された高エネルギー主キャリアによる電子・
正孔対の発生が起こシ、以後、高エネルギーキャリアは
Rを通してvDDから供給されるので、ゲートの電圧を
オフになるような電位に戻しても状態Fi持続する。領
域101は基板102に近い電位の状態に保持される。
For 'O' writing, first apply a suitable negative voltage to the gate of the IGFET, and when a voltage closer to the substrate is applied to the source, the region 101 also rises to a voltage close to the voltage of the source. In the element of the great invention that is composed of the region 10, the thin film 1, the region 101, and the region 102, a large voltage is applied between the opposing region 41 and the region 101, so that the opposing region 1
Electrons due to high energy main carriers injected from 0
Since the generation of hole pairs occurs and thereafter high energy carriers are supplied from vDD through R, the state Fi persists even if the gate voltage is returned to the potential that would turn it off. Region 101 is held at a potential near substrate 102 .

11′書込みの場合はゲート及びソースにvDDに近い
電位を与えると、領域101もそれと同様な電位にな夛
、書込み以前に例え高エネルギーキャリアの注入が行な
われていても辿断状跡となシ、以後IGFETのゲート
の電位をオフ状態に戻しても領域101はvDゎに近い
電位のままで保持されるC領域101と102の逆バイ
アスによる漏洩電流はRを通し、vt、t、から薄膜1
を通簿1て供給されるので、従来のダイナミノクメ1り
のようなりフレノシー動作を必要としない。
In the case of 11' writing, if a potential close to vDD is applied to the gate and source, the region 101 will also reach the same potential, and even if high-energy carriers have been injected before writing, traces will be created. Afterwards, even if the potential of the gate of the IGFET is returned to the OFF state, the region 101 is maintained at a potential close to vDゎ.The leakage current due to the reverse bias of the C regions 101 and 102 passes through R and from vt, t. thin film 1
Since the system is supplied with a single ledger, there is no need for a french operation like in the conventional Dynaminokume 1.

1に入射光によ多情報よ@き込むことができ、プレイ構
成とすれば光像のスタティク記憶及びランダムアクセス
読出しも可能である。半導体領域が発光材料で構成され
ていれば記憶情報の発光表示も可能である。一方、ウェ
ファ占有面積はほぼlトランジスタ分で可能であるので
、高密度スタティックメモリを得ることができる。
A large amount of information can be written into the incident light, and if a play configuration is used, static storage and random access reading of the optical image is also possible. If the semiconductor region is made of a luminescent material, it is also possible to display stored information by luminescence. On the other hand, since the wafer occupancy area is approximately one transistor, a high-density static memory can be obtained.

スタンドバイ時の電力を小さくするためにRは等制約に
高抵抗の素子(または定電流特性を示す素子でちれば、
微小電流素子)を用いるのが通常であるので、高速読出
しにおいては比較的大きな電流を読出すため、いわゆる
破壊読出しとなるので、サイクルタイムが長くなる。こ
れを避けるために抵抗性素子Rの代シに第7図に示すよ
うに、IGFET QFL  を対向領域10とvt、
わの間に直列に挿入することが考えられる。抵抗性素子
Rは絶蝕膜上に構成された多結晶S、薄膜等で小面積に
1集積できたが、この場合はユニットセルが2つのトラ
ンジスタの占有面積を必要とすboしかし、新たに接続
されたIGFET QRのゲートを読出しの時により低
抵抗になる方向にノ(1アスすることにより、非破壊読
出しが可能と偽り、高速動作を実現することができる。
In order to reduce the power during standby, R should be an element with high resistance (or an element that exhibits constant current characteristics) with equal constraints.
Since a micro current element (small current element) is normally used, a relatively large current is read out in high-speed readout, resulting in so-called destructive readout, resulting in a long cycle time. In order to avoid this, in place of the resistive element R, as shown in FIG.
It is conceivable to insert them in series between the rows. The resistive element R can be integrated in a small area using polycrystalline S, thin film, etc. constructed on an erodible film, but in this case, the unit cell requires the area occupied by two transistors. By setting the gate of the connected IGFET QR to 1 in the direction of lower resistance during reading, it is possible to pretend that non-destructive reading is possible and achieve high-speed operation.

なお、]6図において領域101をコレクタとするノく
イポーラトランジスタを形成すれば、ノくイポーラトラ
ンジスタを選択用素子とするメモリセルを実現すること
ができる0領域101を電界効果トランジスタのドレイ
ン又はソースと共用する力・、バイポーラトランジスタ
のコレクタと共用するかして光伶記憶又は発光により情
報内容のティスプレィ可能々高密度メモリセルを提供−
することかできる。
In addition, in FIG. 6, if a non-ipolar transistor is formed with the region 101 as the collector, a memory cell with the non-ipolar transistor as a selection element can be realized. Alternatively, the power can be shared with the source and the collector of a bipolar transistor to provide a high-density memory cell capable of displaying information content by optical storage or light emission.
I can do something.

更に第8図に示すように対向領域10.71VIP’1
半導体領域】00からなる素子に近接して1個又は多数
の互に近接ししかも@接同士は絶6された電極及び半導
体領域と整流接合を有する領域101Dを設け、 CC
D動作、直列MDS )ランジスタ動作により、機能デ
バイスを実現することができ石。第8図の構成は例えば
次のような機能を行り。第1に絶縁ゲート121 、1
22・・・】27が連続L17t1つのゲートであると
きは、領域101D  t:畳込み読み出し線、絶縁ゲ
ートを番地選択線とした光像を記憶するか、発光で記憶
情報を2次元的に表示するメモリアレイのユニットセル
として動作する。第2に絶縁グー) 121 、122
・・127を適宜位相のずれたパルスによって駆動して
CCD動作をさせ、対向領域10と薄膜1と半導体領域
100で構成される本発明のデバイス部分に発光信号を
り7レフシ一動作なしに発光を記憶させることができる
。また、受光信号領域101Dまで転送して会合ミ情報
の読出しを行う篩−とができる。第3に上記本発明のデ
バイス部廃に上記CCD動作により信号電荷を送シ込み
、規定量だけ電荷が蓄積された時前記本発明のデノ(イ
スがオンになる、すなわち発光することをftl用して
信号電荷の個数のカウント、駆動)くルスの分周を行う
ことができる0 等の種々の有用な機能を実現することができる。
Furthermore, as shown in FIG. 8, the opposing area 10.71VIP'1
Semiconductor region] A region 101D having a rectifying junction with the semiconductor region and one or many electrodes that are close to each other but not in contact with each other is provided in close proximity to the element consisting of CC.
D operation, series MDS) Functional devices can be realized by transistor operation. The configuration shown in FIG. 8 performs the following functions, for example. First, the insulated gate 121,1
22...] When 27 is a continuous L17t one gate, area 101D t: Stores an optical image with the convolution readout line and insulated gate as an address selection line, or displays stored information two-dimensionally by emitting light. operates as a unit cell in a memory array. Second is insulation goo) 121, 122
... 127 is driven with appropriately phase-shifted pulses to cause CCD operation, and a light emission signal is sent to the device portion of the present invention consisting of the facing region 10, the thin film 1, and the semiconductor region 100, and the light is emitted without any reflex action. can be memorized. In addition, a sieve can be formed that transfers the light to the received light signal area 101D and reads out the meeting information. Third, a signal charge is sent to the device part of the present invention by the CCD operation, and when a predetermined amount of charge is accumulated, the device of the present invention turns on, that is, emits light. It is possible to realize various useful functions such as counting the number of signal charges, driving), and dividing the frequency of pulses.

以上の具体例の説明において主キャリアを電子としたが
、正孔とした場合は半導体各領域の4デバイスの場合に
対向領域10側から効率よく光を取シ出したシ照射した
シするためには対向領域10は少なくとも半導体領域1
00よりも禁制帯幅の大きい半導体か又は金属の場合で
あれば数100X以下の薄い膜厚1で構成されているか
、または不透明な材質でも多数のスリットが設けられた
構成かの光透過性の構造である必要がある。しかし、特
に受光デノ(イスの場合は不透明対向領域周辺からの入
射光でも充分動作することが確められている。
In the above description of the specific example, electrons were used as the main carriers, but in the case of holes, in order to efficiently extract light from the opposing region 10 side in the case of four devices in each semiconductor region, and to irradiate it. The opposing region 10 is at least the semiconductor region 1
In the case of a semiconductor with a forbidden band width larger than 000, or a thin film thickness of several hundred times or less in the case of a metal, or a structure with a large number of slits even if it is an opaque material, it has a light transmittance. It needs to be structured. However, especially in the case of a light-receiving device (chair), it has been confirmed that it operates satisfactorily even with incident light from the periphery of the opaque opposing region.

本発明の構成によれば対向領域はもとより、構成要件の
1つでちる半導体領域に対する結晶性、不純物濃度関係
の設計において従来より広範囲の特性のものを用いて良
好力光電素子を実現することができる。特に光[機能と
同時に新秋回路を実現することができるっ
According to the structure of the present invention, it is possible to realize a photoelectric device with a good power by using a wider range of characteristics than conventional ones in designing not only the opposing region but also the crystallinity and impurity concentration of the semiconductor region, which is one of the structural requirements. can. In particular, light [functions can be realized at the same time as the New Autumn circuit].

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第8図は本発明の実施例を示す。 図中、1は薄膜、10は対向領域、100は半導体領域
を示す。 jiフ 1  (′、2) 第11ヨ レコ 2 図 ioo             占 7垢・ 3 =n “1 半4図 (CT、) 培・5図 〉し乙  図 J、    =< − 17′
1 to 8 show embodiments of the present invention. In the figure, 1 is a thin film, 10 is an opposing region, and 100 is a semiconductor region. jifu 1 (', 2) 11th twist 2 Figure ioo Fortune 7 scale 3 = n "1 Half 4 Figure (CT,) Culture 5 Figure 〉shi Otsu Figure J, =< - 17'

Claims (1)

【特許請求の範囲】 1)半導体領域と、該半導体領域に対向する対向領域と
、前記半導体領域より禁制帯幅の大きい物質の薄膜とか
ら少なくとも構成され、前記薄膜の厚さは対向領域と半
導体領域間のキャリア輸送が薄膜の禁制帯内を少なくと
も一部通過する輸送によつて行なわれるように充分薄く
、前記対向領域から前記半導体領域へ前記半導体領域の
エネルギーギャップ以上のエネルギーのキャリアを注入
するためのバイアス手段により前記対向領域から半導体
領域へのキャリア注入を行ない半導体領域表面で電子正
孔対を発生させ発光又は受光を行なう光電素子。 2)特許請求の範囲1)に記載の光電素子において前記
薄膜は前記対向領域から該薄膜をみたバリアの高さが主
キャリアに対して低く、前記半導体領域からみた該薄膜
のバリアの高さが主キャリアと逆極性のキャリアに対し
て高い材料で構成されて成る光電素子。 3)特許請求の範囲1)に記載の光電素子において、前
記薄膜の膜内を輸送されるキャリアが主として単一極性
のものである光電素子。 4)特許請求の範囲1)に記載の光電素子において、前
記対向領域が薄膜の主キャリアの極性と同一極性の導電
型を有する半導体領域である光電素子。 5)特許請求の範囲1)に記載の光電素子において、前
記半導体領域は薄膜との接合面からキャリアが到達でき
る範囲内に該半導体領域と整流性の接合を有する第2の
領域を有して成る光電素子。 6)特許請求の範囲5)に記載の光電素子において、前
記対向領域をエミッタ、前記半導体領域をベース、前記
第2の領域をコレクタとし、バイポーラトランジスタと
して動作させる光電素子。 7)特許請求の範囲5)に記載の光電素子において、前
記対向領域に対向する前記半導体領域表面に反転層ない
し空乏層を形成し、前記対向領域をエミッタ、前記反転
層ないし空乏層をベース、前記半導体領域をコレクタ、
前記第2の領域をベース接続領域とし、バイポーラトラ
ンジスタとして動作させる光電素子。 8)特許請求の範囲5)に記載の光電素子において、前
記第2の領域は、前記半導体領域に対して前記対向領域
に与えられた電圧と逆符号の電圧を発生するか、前記対
向領域から流入する電流に対して逆方向の電流を流すも
のである電源用光電素子。 9)特許請求の範囲5)に記載の光電素子において、前
記半導体領域を、前記対向領域と前記第2の領域との間
のスイッチング特性を制御する領域として用いるスイッ
チング光電素子。 10)特許請求の範囲5)に記載の光電素子において、
前記第2の領域を、前記対向領域と前記半導体領域との
間のスイッチング特性を制御する領域として用いるスイ
ッチング光電素子。 11)特許請求の範囲1)に記載の光電素子において、
該対向領域に絶縁された状態で近接し、かつ前記半導体
領域上に絶縁膜を介して設けられた絶縁ゲートと、該絶
縁ゲート下に一部重なつて設けられ、かつ前記半導体領
域と整流性接 合を有する第3の領域を有することを特徴とする半導体
集積回路。 12)特許請求の範囲11)に記載の半導体集積回路に
おいて、前記絶縁ゲートは、隣接部分で互いに絶縁され
た複数個の絶縁ゲート部分から成る半導体集積回路。
[Scope of Claims] 1) Consists of at least a semiconductor region, a counter region facing the semiconductor region, and a thin film of a material having a wider forbidden band width than the semiconductor region, and the thickness of the thin film is equal to that of the counter region and the semiconductor region. Inject carriers into the semiconductor region from the opposing region to the semiconductor region with an energy greater than the energy gap of the semiconductor region, so that carrier transport between the regions is carried out through transport that passes at least partially within the forbidden zone of the thin film. A photoelectric element in which carriers are injected from the opposing region into the semiconductor region using bias means for generating electron-hole pairs on the surface of the semiconductor region, thereby emitting or receiving light. 2) In the photoelectric device according to claim 1), the thin film has a barrier height lower than the main carrier when viewed from the opposing region, and a barrier height of the thin film when viewed from the semiconductor region. A photoelectric element made of a material that has a high polarity for carriers of opposite polarity to the main carrier. 3) The photoelectric device according to claim 1), wherein the carriers transported within the thin film are mainly of single polarity. 4) The photoelectric device according to claim 1, wherein the opposing region is a semiconductor region having a conductivity type having the same polarity as the polarity of the main carrier of the thin film. 5) In the photoelectric device according to claim 1), the semiconductor region has a second region having a rectifying junction with the semiconductor region within a range that carriers can reach from the junction surface with the thin film. A photoelectric element consisting of 6) The photoelectric device according to claim 5, wherein the opposing region is an emitter, the semiconductor region is a base, and the second region is a collector, and the photoelectric device operates as a bipolar transistor. 7) In the photoelectric element according to claim 5), an inversion layer or a depletion layer is formed on the surface of the semiconductor region opposite to the opposing region, the opposing region is an emitter, and the inversion layer or depletion layer is a base. the semiconductor region as a collector;
A photoelectric device in which the second region is used as a base connection region and operates as a bipolar transistor. 8) In the photoelectric device according to claim 5, the second region generates a voltage with the opposite sign to the voltage applied to the opposing region with respect to the semiconductor region, or generates a voltage applied to the semiconductor region from the opposing region. A photoelectric element for power supply that allows current to flow in the opposite direction to the incoming current. 9) A switching photoelectric device according to claim 5, in which the semiconductor region is used as a region for controlling switching characteristics between the opposing region and the second region. 10) In the photoelectric device according to claim 5),
A switching photoelectric element using the second region as a region for controlling switching characteristics between the opposing region and the semiconductor region. 11) In the photoelectric device according to claim 1),
an insulated gate that is insulated and proximate to the opposing region and is provided on the semiconductor region via an insulating film; A semiconductor integrated circuit comprising a third region having a junction. 12) The semiconductor integrated circuit according to claim 11, wherein the insulated gate is composed of a plurality of insulated gate portions whose adjacent portions are insulated from each other.
JP60171373A 1985-08-02 1985-08-02 Semiconductor device and integrated circuit thereof Granted JPS6150376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60171373A JPS6150376A (en) 1985-08-02 1985-08-02 Semiconductor device and integrated circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60171373A JPS6150376A (en) 1985-08-02 1985-08-02 Semiconductor device and integrated circuit thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP12878777A Division JPS5462787A (en) 1977-10-28 1977-10-28 Semiconductor device and integrated circuit of the same

Publications (2)

Publication Number Publication Date
JPS6150376A true JPS6150376A (en) 1986-03-12
JPH0481354B2 JPH0481354B2 (en) 1992-12-22

Family

ID=15921976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60171373A Granted JPS6150376A (en) 1985-08-02 1985-08-02 Semiconductor device and integrated circuit thereof

Country Status (1)

Country Link
JP (1) JPS6150376A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014073296A1 (en) * 2012-11-08 2014-05-15 株式会社ブイ・テクノロジー Optical interconnection device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4946880A (en) * 1972-09-09 1974-05-07
JPS52128787A (en) * 1976-04-16 1977-10-28 Markem Corp Printing equipment
JPS5462787A (en) * 1977-10-28 1979-05-21 Agency Of Ind Science & Technol Semiconductor device and integrated circuit of the same
JPS6226193A (en) * 1985-07-29 1987-02-04 Nippon Kokan Kk <Nkk> Elimination of ice formed on upper structure of ship

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4946880A (en) * 1972-09-09 1974-05-07
JPS52128787A (en) * 1976-04-16 1977-10-28 Markem Corp Printing equipment
JPS5462787A (en) * 1977-10-28 1979-05-21 Agency Of Ind Science & Technol Semiconductor device and integrated circuit of the same
JPS6226193A (en) * 1985-07-29 1987-02-04 Nippon Kokan Kk <Nkk> Elimination of ice formed on upper structure of ship

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014073296A1 (en) * 2012-11-08 2014-05-15 株式会社ブイ・テクノロジー Optical interconnection device

Also Published As

Publication number Publication date
JPH0481354B2 (en) 1992-12-22

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