JPS6150345U

JPS6150345U -

Info

Publication number: JPS6150345U
Application number: JP12496785U
Authority: JP
Priority date: 1985-08-14
Filing date: 1985-08-14
Publication date: 1986-04-04

Description

[Brief explanation of the drawing]

第１図は従来の、第２図は本考案の試験要領を
説明するブロツク図、第３図は出力パルス等の波
形図、第４図および第５図は第１図の詳細な回路
図、第６図は本考案の実施例を示す回路図、第７
図は第２図、第６図の動作説明用波形図である。図面でＯＳＣは内部発振器、ＦＦ_１〜ＦＦ_２３は多段分周回路、Ｍは出力端子、Ｓ_１１，Ｓ_１２は切換スイツチ、はリセツト端子、ＡＬＭ
は他用途回路が接続されるピン、Ｑ_１，Ｑ_２等は
高インピーダンス状態にする回路、Ｇ_４，Ｇ_９，
Ｇ_１０，ＬＴ_１等はリセツト、同解除制御回路で
ある。 Fig. 1 is a conventional test procedure, Fig. 2 is a block diagram explaining the test procedure of the present invention, Fig. 3 is a waveform diagram of output pulses, etc., Figs. 4 and 5 are detailed circuit diagrams of Fig. 1, FIG. 6 is a circuit diagram showing an embodiment of the present invention, and FIG.
The figure is a waveform diagram for explaining the operation of FIGS. 2 and 6. In the drawing, OSC is an internal oscillator, FF ₁ to FF ₂₃ is a multistage frequency divider circuit, M is an output terminal, S ₁₁ , S ₁₂ is changeover switch, is reset terminal, ALM
are pins to which other purpose circuits are connected, Q ₁ , Q _{2 ,} etc. are circuits that are placed in a high impedance state, G ₄ , G ₉ ,
_G10 , _LT1, etc. are reset and release control circuits.

Claims

[Scope of utility model registration request]

In an integrated circuit that has a multi-stage frequency divider circuit that divides a frequency and an output terminal for the frequency-divided output, the circuit is separated in the middle of the multi-stage frequency divider circuit, and a circuit for other purposes of the integrated circuit is connected to the subsequent stage. A circuit is provided with a changeover switch that guides an external pulse input from a connected pin, and also puts an output section of the other application circuit to the pin into a high impedance state when a reset signal is input through the reset terminal of the integrated circuit. A multi-stage frequency divider circuit, characterized in that a circuit is provided that resets the rear stage part of the frequency divider circuit, releases the reset when an external high frequency pulse is subsequently inputted from the pin, and causes the latter stage part to start counting. Integrated circuit with.