JPS6150338B2 - - Google Patents
Info
- Publication number
- JPS6150338B2 JPS6150338B2 JP56197897A JP19789781A JPS6150338B2 JP S6150338 B2 JPS6150338 B2 JP S6150338B2 JP 56197897 A JP56197897 A JP 56197897A JP 19789781 A JP19789781 A JP 19789781A JP S6150338 B2 JPS6150338 B2 JP S6150338B2
- Authority
- JP
- Japan
- Prior art keywords
- error
- group
- information
- storage control
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003860 storage Methods 0.000 claims description 26
- 238000004458 analytical method Methods 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 7
- 230000010365 information processing Effects 0.000 claims description 6
- 238000003672 processing method Methods 0.000 claims description 4
- 239000000872 buffer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 208000011580 syndromic disease Diseases 0.000 description 2
- 101100421135 Caenorhabditis elegans sel-5 gene Proteins 0.000 description 1
- 102100029951 Estrogen receptor beta Human genes 0.000 description 1
- 101001010910 Homo sapiens Estrogen receptor beta Proteins 0.000 description 1
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 108091008577 estrogen receptors gamma Proteins 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Description
(1) 発明の技術分野
本発明は誤り処理方式詳しくは情報処理システ
ムの中央処理装置へエラーを報告する方式に関す
る。
(2) 技術の背景
情報処理システムでは該システムを構成する各
装置の誤り情報を中央処理装置CPUへ報告し、
処理装置CPUはそれらの誤り情報をメモリの所
定番地へロギングデータとして格納し、その格納
情報を解析することにより誤り発生場所を認識す
る。
(3) 従来技術と問題点
ロギングデータ格納用メモリ領域は勿論有限で
あり、そして最小容量とした方が効率的である。
また誤り情報を各装置から処理装置へ伝送する信
号線の本数も、極力少ないことが望まれる。
(4) 発明の目的
本発明はこれらの点に鑑みてなされたもので、
ロギングデータ用メモリ領域を可及的に小容量に
することができ、信号線本数も減少できるエラー
処理方式を提供しようとするものである。
(5) 発明の構成
本発明ではこれらの要求を満たすべく、処理装
置と記憶制御装置間に固定のインタフエース信号
を用意し、記憶制御装置と記憶装置、および記憶
制御装置内の複数のバツフア毎に誤り検出した
ら、それら誤り情報の組立てを記憶制御装置内で
行ない、誤りの内容および発生場所により信号内
容を切換えて前記インタフエース信号として処理
装置へ報告するようにする。即ち本発明は処理装
置、記憶制御装置、および記憶装置を含む情報処
理システムにおける誤り処理方式において、記憶
制御装置から処理装置へ誤り発生を報告するため
の第１の信号群と、該第１の信号群によつて報告
された誤りを解析する情報を提供するための第２
の信号群を用意し、記憶制御装置内の各単位回路
の誤りを検出するための第１の誤り検出回路群お
よび誤り解析情報回路群と、記憶装置の誤りを検
出するための第２の誤り検出回路群および誤り解
析情報回路群を設け、誤りの内容および誤りの発
生箇所に従つて前記第１、第２の信号群の内容を
変えて所定のタイミングで記憶制御装置から処理
装置へ報告し、処理装置ではこれら第１、第２の
信号群を所定のメモリ領域へ格納することを特徴
とするが、次に図面を参照しながらこれを説明す
る。
(6) 発明の実施例
第１図は本発明が適用される情報処理システム
の概要を示しCPUは中央処理装置、MCUは記憶
制御装置、BS１，BS２はMCU内蔵のバツフアス
トーレツジ、MSUは記憶装置（主記憶）であ
る。MSUは複数のブロツク（セグメントSEGと
いう）からなり、ブロツクも更に細分されてお
り、そして斜線を付して示す増設単位RUと呼ば
れる小ブロツクもある。本システムでは記憶装置
MSUが複数個あり、これらに共通の記憶制御装
置MCUが１つ設けられ、複数の処理装置CPUが
MCUを介してMSUの任意のものにアクセスす
る。
本発明では記憶制御装置MCUを第２図に示す
如く構成する。この図でBS１，BS２は前述のバ
ツフア、PSDは優先順位決定回路、SEL1〜SEL5
は選択回路、ADDCはアドレス変換回路、CTL
は制御回路、ECTLは各種エラーE1〜Enの制御
回路、PWCは部分書換え回路である、バツフア
BS２はCPUから送られてくるデータの格納用、
BS１はその制御用データの格納用である。これ
らのデータにはECC（エラーコレクテイングコ
ード）が付加され、同様にMSUからのデータに
もECCが用意される。
処理装置CPUから例えばメモリ読取り信号が
送られると、メモリアドレスはアドレス変換回路
ADDCを介して記憶装置MSUへ送られ、読取り
データは選択回路SEL5、部分書き換え回路
PWC，MSU用ECC回路、選択回路SEL4の経路
でCPUへ送られる。部分書換え回路PWCはMSU
の読出しデータの一部を、バツフアBS１情報で
選択したバツフアBS２の情報に書換えるなどの
処理をする。
各ECC回路によりエラーが検出されるとエラ
ーシンドロームESRが作成され、これは選択回
路SEL3を通して誤り解析情報EAIの一部として
CPUへ送出される。誤り解析情報EAIには、
MSU番号および増設単位番号MNRと、複数ある
バツフアBS１のWAYナンバー（連想レベル）
BWNも選択回路SEL2により選択されて含まれ
る。MCUおよびMSUで生じる各種エラーE1〜En
はMCUの誤り制御回路ECTLを通して誤り情報
EIとしてCPUへ送られるが、この誤り情報は本
発明の実施例では８ビツト構成とし、各ビツトに
は次の意味を持たせる。
(1) Technical Field of the Invention The present invention relates to an error handling method, and more particularly to a method for reporting errors to a central processing unit of an information processing system. (2) Background of the technology In an information processing system, error information of each device that makes up the system is reported to the central processing unit CPU.
The processing unit CPU stores the error information in a predetermined location in the memory as logging data, and recognizes the error occurrence location by analyzing the stored information. (3) Prior art and problems The memory area for storing logging data is of course limited, and it is more efficient to minimize the capacity.
It is also desirable that the number of signal lines for transmitting error information from each device to the processing device be as small as possible. (4) Purpose of the invention The present invention has been made in view of these points.
The present invention aims to provide an error processing method that can reduce the capacity of a logging data memory area as much as possible and also reduce the number of signal lines. (5) Structure of the Invention In order to meet these requirements, the present invention provides a fixed interface signal between the processing device and the storage control device, and provides a fixed interface signal for each of the storage control device and the storage device, as well as for each of the multiple buffers in the storage control device. When an error is detected, the error information is assembled within the storage control device, and the signal content is switched depending on the content and location of the error and is reported to the processing device as the interface signal. That is, the present invention provides an error processing method in an information processing system including a processing device, a storage control device, and a storage device, which includes a first signal group for reporting error occurrence from the storage control device to the processing device; a second signal to provide information for analyzing errors reported by the signal constellation;
a first error detection circuit group and an error analysis information circuit group for detecting errors in each unit circuit in the storage control device; and a second error detection circuit group for detecting errors in the storage device. A detection circuit group and an error analysis information circuit group are provided, and the contents of the first and second signal groups are changed according to the contents of the error and the location where the error occurs, and are reported from the storage control device to the processing device at a predetermined timing. The processing device is characterized in that these first and second signal groups are stored in a predetermined memory area, which will be explained next with reference to the drawings. (6) Embodiments of the Invention Figure 1 shows an overview of an information processing system to which the present invention is applied, where CPU is a central processing unit, MCU is a storage control unit, BS1 and BS2 are buffer storages with built-in MCU, and MSU. is a storage device (main memory). The MSU consists of multiple blocks (called segments SEG), which are further subdivided, and there are also small blocks called expansion units RU, which are shown with diagonal lines. In this system, the storage device
There are multiple MSUs, one common storage control unit MCU is provided for these, and multiple processing units CPU are provided.
Access anything on the MSU through the MCU. In the present invention, the storage control unit MCU is configured as shown in FIG. In this diagram, BS1 and BS2 are the buffers mentioned above, PSD is the priority determination circuit, and SEL 1 to SEL 5
is selection circuit, ADDC is address conversion circuit, CTL
is a control circuit, ECTL is a control circuit for various errors E 1 to En, PWC is a partial rewriting circuit, buffer
BS2 is for storing data sent from the CPU,
BS1 is for storing the control data. ECC (Error Correcting Code) is added to these data, and ECC is also prepared for data from MSU. For example, when a memory read signal is sent from the processing unit CPU, the memory address is converted to an address conversion circuit.
The read data is sent to the storage device MSU via ADDC, and the read data is sent to the selection circuit SEL 5 and the partial rewriting circuit.
It is sent to the CPU via the PWC, ECC circuit for MSU, and selection circuit SEL 4 . Partial rewriting circuit PWC is MSU
Processing such as rewriting a part of the read data to the information of the buffer BS2 selected by the buffer BS1 information is performed. When an error is detected by each ECC circuit, an error syndrome ESR is created, which is passed through the selection circuit SEL 3 as part of the error analysis information EAI.
Sent to CPU. The error analysis information EAI includes
MSU number, expansion unit number MNR, and WAY number (association level) of multiple buffer BS1
BWN is also selected and included by the selection circuit SEL2 . Various errors E 1 to En that occur in MCU and MSU
The error information is transmitted through the error control circuit ECTL of the MCU.
This error information, which is sent to the CPU as EI, has an 8-bit structure in the embodiment of the present invention, and each bit has the following meaning.
【表】
また本発明の実施例では誤り解析情報EAIを16
ビツト構成とし、各ビツトには次の意味を持たせ
る。[Table] In the embodiment of the present invention, the error analysis information EAI is 16
It has a bit structure, and each bit has the following meaning.
【表】
この表２に示されるように誤り解析情報EIAの
最初の２ビツトはエラーが生じた場所を示してお
り、00ならエラー場所はMSU、01ならBS２，10
ならBS１である。次のNo.２〜６の５ビツトはメ
モリ識別コートで、MSUならセグメント
（SEG）番号および増設単位（FAR）番号を示
し、BS１，BS２ならWAYナンバーを示す。バツ
フアBS１，BS２には増設単位はないからビツト
No.５，６は空きとなる。最後のNo.７〜15の９ビツ
トはエラービツト位置を示し、訂正可能なエラー
ならそのエラービツトの位置（BitLOC）又はシ
ンドロームを示す。
これらの表１，表２に示されるように整理され
た情報をCPUへ送れば、個々ばらばらに送る場
合に比べて所要信号線数は少なくそしてCPUの
メモリ所要領域も少なくて済む。
なお図示しないがCPUではMCUから送られた
誤り情報EIおよび誤り解析情報EAIをメモリのロ
ギングエリヤに格納し、必要に応じて誤り箇所の
解析を行なう。
(7) 発明の効果
以上説明したように本発明によれば、メモリシ
ステムのエラーをMCUで整理してCPUへ送りメ
モリのロギングエリヤに格納させるようにするの
で、所要信号線数およびメモリ容量が節減され、
甚だ有効である。[Table] As shown in Table 2, the first two bits of the error analysis information EIA indicate the location where the error occurred; if it is 00, the error location is MSU, if it is 01, it is BS2, 10.
Then it is BS1. The next 5 bits No. 2 to 6 are memory identification codes, which indicate the segment (SEG) number and expansion unit (FAR) number for MSU, and the WAY number for BS1 and BS2. There is no expansion unit for buffers BS1 and BS2, so it is a bit
Nos. 5 and 6 will be vacant. The last nine bits No. 7 to No. 15 indicate the error bit position, and if the error is correctable, the error bit position (BitLOC) or syndrome is indicated. If the information organized as shown in Tables 1 and 2 is sent to the CPU, the number of required signal lines and the memory area of the CPU will be smaller than when the information is sent individually. Although not shown, the CPU stores the error information EI and error analysis information EAI sent from the MCU in the logging area of the memory, and analyzes error locations as necessary. (7) Effects of the Invention As explained above, according to the present invention, errors in the memory system are sorted out by the MCU, sent to the CPU, and stored in the logging area of the memory, thereby reducing the number of signal lines and memory capacity required. saved,
It is extremely effective.
第１図は本発明が適用される情報処理システム
の概要を示すブロツク図、第２図は本発明の実施
例を示すブロツク図である。
図面でCPUは処理装置、MCUは記憶制御装
置、MSUは記憶装置、EIは第１の信号群、EAI
は第２の信号群、BS２用ECCは第１の誤り検出
回路群、BWN及びESR２はその誤り解析情報回
路群、MSU用ECCは第２の誤り検出回路群、
MNR及びESR３はその誤り解析情報回路群であ
る。
FIG. 1 is a block diagram showing an overview of an information processing system to which the present invention is applied, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the drawing, CPU is a processing unit, MCU is a storage control unit, MSU is a storage device, EI is the first signal group, and EAI
is the second signal group, ECC for BS2 is the first error detection circuit group, BWN and ESR2 are the error analysis information circuit group, ECC for MSU is the second error detection circuit group,
MNR and ESR3 are the error analysis information circuit group.
Claims (1)
含む情報処理システムにおける誤り処理方式にお
いて、 記憶制御装置から処理装置へ誤り発生を報告す
るための第１の信号群と、該第１の信号群によつ
て報告された誤りを解析する情報を提供するため
の第２の信号群を用意し、 記憶制御装置内の各単位回路の誤りを検出する
ための第１の誤り検出回路群および誤り解析情報
回路群と、記憶装置の誤りを検出するための第２
の誤り検出回路群および誤り解析情報路群を設
け、 誤りの内容および誤りの発生箇所に従つて前記
第１，第２の信号群の内容を変えて所定のタイミ
ングで記憶制御装置から処理装置へ報告し、処理
装置ではこれら第１、第２の信号群を所定のメモ
リ領域へ格納することを特徴とした誤り処理方
式。[Claims] 1. An error processing method in an information processing system including a processing device, a storage control device, and a storage device, comprising: a first signal group for reporting error occurrence from the storage control device to the processing device; a second signal group for providing information for analyzing errors reported by the first signal group; and a first error detection for detecting errors in each unit circuit in the storage control device. A circuit group, an error analysis information circuit group, and a second circuit group for detecting errors in the storage device.
An error detection circuit group and an error analysis information path group are provided, and the contents of the first and second signal groups are changed according to the content of the error and the location where the error occurs, and are transmitted from the storage control device to the processing device at a predetermined timing. An error processing method characterized in that the first and second signal groups are reported and stored in a predetermined memory area in a processing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197897A JPS5899850A (en) | 1981-12-09 | 1981-12-09 | Error processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197897A JPS5899850A (en) | 1981-12-09 | 1981-12-09 | Error processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5899850A JPS5899850A (en) | 1983-06-14 |
| JPS6150338B2 true JPS6150338B2 (en) | 1986-11-04 |
Family
ID=16382098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56197897A Granted JPS5899850A (en) | 1981-12-09 | 1981-12-09 | Error processing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5899850A (en) |
-
1981
- 1981-12-09 JP JP56197897A patent/JPS5899850A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5899850A (en) | 1983-06-14 |
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