JPS6015758A - Buffer memory - Google Patents

Abstract

PURPOSE:To process data at a high speed and high efficiency by providing a spare data array which stores the write data when an error arises and a spare address array which stores the address of said data array. CONSTITUTION:In a writing operation to a main memory 12, a data checking circuit 10 checks a data write end signal 14. If an error arises, an error report signal 13 is transmitted to an error control circuit 17 which controls a spare address array 15 and a spare data array 16. Then the circuit 17 writes the contents of a data address register 6 to the array 15 and the contents of a write data register 8 to the array 16, resepctively. When an address sent from a CPU11 is received by a buffer address register 1, a comparator 18 compares the contents of the address with the contents of the array 15. Then the data of the array 16 is read out when the coincidence is obtained from said comparison.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention is directed to a data processing system, in which a buffer storage device provided between a main storage device and a processor ν- is provided with a faulty memory in order to speed up processing. This relates to processing means.

[Prior art]

A conventional 44-column buffer memory arrangement of this type is shown in FIG. 1S1. FIG. 1 is a block diagram showing a conventional pants storage device. In the figure, 1 is a buffer address register (
BAR), 2 is an address array that stores the at L/S of the data array 7 that has a copy of the main memory unit (MMU) 12, and 3 is an address array that stores the contents read from the address array 2 and the central processing unit J! [! A comparison encoding circuit compares and encodes the address sent from the device (CPLT) 11, and 4 is a copy of the data in the main memory unit (MMU) 12 held in the buffer storage device. 5 is a replacement control circuit that controls the replacement control register 4; 6 is a data address register (DAR) for launching the address f necessary to write to the buffer storage device; 8 is a data address register (DAR) for 9 is a write control circuit, and 10 is a data check circuit.

Next, the operation shown in FIG. 1 will be explained. In the block 4f4 diagram shown in FIG. 1, the explanation is given assuming that the pan 7 memory area is 4 cents x 64 columns, one data area is 8 bytes, and the capacity of the main memory device (MMU'') 12 is 1 megabyte. Central processing unit (CPU)
An address of 20 bits (0 to 19 pins) is sent from It1. When this address 2:) is transferred to the buffer address register (BARQ~1.) 1, the buffer storage device is transferred to the buffer address register (BARu~16).
) Read address array 2 according to l. This read address and the buffer address register (B A
Ro~,. )1 from the comparator 11, the data in the write data register (WDR) 8 is written into the data array 7. The address of the data array 7 is a total of 8 bits, which is the 11th to 16th bits of the bumper address register (BAR) 1 and the output of the comparison encoder circuit 3, added to the upper 2 bits.
DAR) 6 and this data address register (
The data is written by the νf write control circuit 90 and the control signal 1 according to the address of DAR)6. , central processing unit (CPU)
The data sent from 11 is sent to the main memory unit (MMU)
12, and the memory W (M M l'J )1
2 starts the reading operation.The main memory device F1γ(A, i
M(J)] 2 checks the sent data through the data check circuit 10, and if there is no error, 〒! Data is written to the upper storage unit R (MMU) 12 by the write control circuit 9. The main memory device (MMUJ 121:J) fetches the data write operation end signal j4 and sends it to the control circuit 9. At this point, an error is reported or the data write operation end signal J4y is sent. If not, the IC sends the error report signal 13 to the central processing unit (CPU).
Send it to 11. When the central processing unit (CPU) 11 receives the error report signal 13.

The process is interrupted and subsequent operations are canceled.

Since the conventional buffer storage device is configured as described above, in the write operation of the Pan7a storage device, if the corresponding address exists in the buffer storage device, the buffer storage device and the device (1.1 above) are M, 1VIU) 1
．． Write data to both swords. At this time, if an error occurs in the write operation to the main memory unit (MU) 12, the data processing system stops 1 and the processing 7i
It had the disadvantage that it was interrupted and it would not be full without it.

[Summary of the invention]

The present invention is intended to eliminate all the drawbacks of the conventional ones as described above, and is to provide a buffer storage device that stores a copy of a part of the memory contents of a main storage device, in which a write operation to the main storage device is performed. The error report signal inside includes a scattering error control circuit, a spare data array 1/- for storing tC write data when an error p occurs, a spare address array for storing the address of this spare data array, and this spare address. A comparison circuit that compares the array address and the requested address is provided. It is an object of the present invention to provide a buffer storage device that can be used to continue operation of a data processing system without interrupting processing.

[Embodiments of the Invention] Examples of the invention will be described below. FIG. 2 is a block diagram showing a buffer storage device according to an embodiment of the present invention. The same parts as those in FIG. In the figure,
16 is a spare data array that stores write data when an error occurs; 15 is a spare address array that stores the address of the spare data array 16; and 17 is a main memory (AiM
U) An error control circuit receives and receives an error report signal 13 during a write operation to 12, and 18 is a comparison circuit that compares the address of the spare address array 15 with the requested address. The rest of the structure is similar to that shown in FIG. 1 above.

Next, the operation shown in FIG. 2 will be explained. In response to a write request from the central processing unit (CPU) i, the write operation to the data array 7 is performed using the first
This is the same as in the figure. Now, the main memory (MM)
U) Upon entering the write operation to 12, the data check circuit 10 checks that the data write operation end signal 14 has been received correctly. Here, when an error occurs, the error report signal 13 is transmitted to the spare address array 15. The error control circuit 17 which controls the preliminary data array 16 is informed. The error control circuit 17 writes the contents of the data address register (DAR) 6 to the spare address array 5, further writes the contents of the write data register (WDR) 8 to the spare data array 16, and ends the operation. Thereafter, for reading and @ writing of the address where the error occurred, the spare address array 15. This is done using the spare data array 16, and the main memory (no writing is done. The central processing unit (
When received by the address register (B) l) 1 sent from the CPU) 11, the contents of the buffer address register (BAR) 1 and the spare address register (BAR) 1 are stored. The comparison circuit 18 compares the contents of the data, and if they match, the data in the preliminary data array 16 is read out. Also,
In response to the request, the central processing unit (CPU)
Write all the acquired data sent from 11.

By doing this, the address of the main storage device (i'1IIRLl) 2 will not be accessed again when an error occurs. By always having a copy of EMU) 12, you may not be able to re-occur the error, and if an error occurs, you will not have to immediately repair the malfunction. Operation of the data processing system can continue.

The entire buffer storage device according to the present invention is shown in FIG. 2 above! 1. However, the present invention is not limited to the example shown in FIG.

〔Effect of the invention〕

As explained above, even if an error occurs in a buffer storage device during a write operation to the main memory unit (MMU), the present invention uses the data in the buffer storage device, without interrupting the entire process. , the operation of the data processing system can be continued, so data processing can be performed efficiently and at high speed, and it has the excellent effect of providing a data processing system with extremely high reliability. It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional buffer storage device, and FIG. 2 is a block diagram showing a buffer storage device according to an embodiment of the present invention. In the figure, l buffer address register (BAR)
, 2. ,．． 7)-Res array, 3... Comparison encoder circuit, 4... Swapping control register, 5.・Exchange control circuit, 6 Data address register (DAR), 7
...Data array, 8...Write data register (
WDR), 9. Write control circuit, 0...Data check circuit, 1. Central processing unit (CPU), 12 Main memory unit (MMU), 13. Error report signal, 14 Data write operation end signal, 15 Spare address array, 16
・・Preliminary data array,】7 Error control circuit, 18 ・
This is a comparison circuit. In addition, in the drawings, the same reference numerals indicate the same parts or parts of the monks. Agent Masuo Oiwa

Claims (1)

[Claims] In a buffer storage device that stores a copy of a part of the memory contents of a main memory device, an error control circuit that receives an error report signal during a write operation to the main memory device, and a reserve that stores write data when an error occurs. A data array, a spare address array that stores the addresses of the spare data array, a comparator circuit that compares the addresses of the spare address array with the requested address, and an error occurs during a write operation to the main memory. In this case, the error control circuit writes data to the spare data array and an address to the spare address array, and in response to a read or write request to the buffer storage device, the requested address and the address of the spare address array are written. A buffer storage device characterized in that the addresses are compared, and if they match, the data from the preliminary data array is read out or the write data sent from the central processing unit is omitted.