JPS61501295A - ウェハスケールパッケージシステム - Google Patents

ウェハスケールパッケージシステム

Info

Publication number
JPS61501295A
JPS61501295A JP60500990A JP50099085A JPS61501295A JP S61501295 A JPS61501295 A JP S61501295A JP 60500990 A JP60500990 A JP 60500990A JP 50099085 A JP50099085 A JP 50099085A JP S61501295 A JPS61501295 A JP S61501295A
Authority
JP
Japan
Prior art keywords
wafer
header
ground
circuit
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60500990A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0584668B2 (enrdf_load_stackoverflow
Inventor
ストツパー・ハーバート
パーキンス,コーネリアス・チヤーチル
Original Assignee
エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン filed Critical エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン
Publication of JPS61501295A publication Critical patent/JPS61501295A/ja
Publication of JPH0584668B2 publication Critical patent/JPH0584668B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12033Gunn diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
JP60500990A 1984-02-21 1985-02-21 ウェハスケールパッケージシステム Granted JPS61501295A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58197584A 1984-02-21 1984-02-21
US581975 1984-02-21

Publications (2)

Publication Number Publication Date
JPS61501295A true JPS61501295A (ja) 1986-06-26
JPH0584668B2 JPH0584668B2 (enrdf_load_stackoverflow) 1993-12-02

Family

ID=24327329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60500990A Granted JPS61501295A (ja) 1984-02-21 1985-02-21 ウェハスケールパッケージシステム

Country Status (3)

Country Link
EP (1) EP0174950A4 (enrdf_load_stackoverflow)
JP (1) JPS61501295A (enrdf_load_stackoverflow)
WO (1) WO1985003804A1 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
EP0481703B1 (en) * 1990-10-15 2003-09-17 Aptix Corporation Interconnect substrate having integrated circuit for programmable interconnection and sample testing

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3657805A (en) * 1970-01-02 1972-04-25 Texas Instruments Inc Method of housing semiconductors
US3781683A (en) * 1971-03-30 1973-12-25 Ibm Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US3983479A (en) * 1975-07-23 1976-09-28 International Business Machines Corporation Electrical defect monitor structure
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
US4257061A (en) * 1977-10-17 1981-03-17 John Fluke Mfg. Co., Inc. Thermally isolated monolithic semiconductor die
US4220917A (en) * 1978-07-31 1980-09-02 International Business Machines Corporation Test circuitry for module interconnection network
JPS58500096A (ja) * 1981-01-16 1983-01-13 ジョンソン,ロバ−ト・ロイス 広範囲な相互接続サブストレ−ト
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4484215A (en) * 1981-05-18 1984-11-20 Burroughs Corporation Flexible mounting support for wafer scale integrated circuits

Also Published As

Publication number Publication date
JPH0584668B2 (enrdf_load_stackoverflow) 1993-12-02
EP0174950A1 (en) 1986-03-26
WO1985003804A1 (en) 1985-08-29
EP0174950A4 (en) 1988-02-05

Similar Documents

Publication Publication Date Title
US4920454A (en) Wafer scale package system and header and method of manufacture thereof
US5306670A (en) Multi-chip integrated circuit module and method for fabrication thereof
US4975765A (en) Highly integrated circuit and method for the production thereof
US3683105A (en) Microcircuit modular package
US6400573B1 (en) Multi-chip integrated circuit module
US6882546B2 (en) Multiple die interconnect system
EP0073149B1 (en) Semiconductor chip mounting module
US4472876A (en) Area-bonding tape
US6184463B1 (en) Integrated circuit package for flip chip
US5892271A (en) Semiconductor device
US5889325A (en) Semiconductor device and method of manufacturing the same
US5796164A (en) Packaging and interconnect system for integrated circuits
US20040238931A1 (en) Assemblies having stacked semiconductor chips and methods of making same
JPH0815188B2 (ja) チツプキヤリヤを用いた集積回路ボ−ド,及び該集積回路ボ−ドを製作する方法
JPH06181283A (ja) 多チップモジュールのための架橋式プログラミングの方法
JP2000164765A (ja) 電源及び接地ラップを具備したクロスト―クノイズ低減形の高密度信号介挿体、並びに、介挿体の製造方法
US5497027A (en) Multi-chip module packaging system
US5061988A (en) Integrated circuit chip interconnect
EP0843357B1 (en) Method of manufacturing a grid array semiconductor package
US5512710A (en) Multilayer package with second layer via test connections
US6413102B2 (en) Center bond flip chip semiconductor carrier and a method of making and using it
US6320250B1 (en) Semiconductor package and process for manufacturing the same
JPS61501295A (ja) ウェハスケールパッケージシステム
JP3330468B2 (ja) 配線基板及び半導体装置
JP3012184B2 (ja) 実装装置