JPS6149252A - Error recovery device for semiconductor memory - Google Patents

Abstract

PURPOSE:To attain the recovery of an error without stopping completely the working of a device by switching a memory space where a defective memory element exists to another memory space as soon as a read information error due to a defect of a memory element is detected. CONSTITUTION:A fault space memory register 10 stores an address signal produced when the error information is detected by means of an error signal delivered from a fault detecting circuit 7. At the same time, the register 10 detects the coincidence or discordance between said address signal and another address signal with which a memory is working. Then a latch circuit 11 stores that a fault is produced in a prescribed memory space. A selection signal gate circuit 12 suppresses the second selection of a memory space where a defective memory element exists. Then a memory space switching circuit 13 switches said memory space to a specific memory space of the final bank 2.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention detects a read information error caused by a failure of a storage element in a device using a semiconductor storage device, and promptly replaces the failed storage element with another storage element. The present invention relates to an error recovery device for a semiconductor memory device, which aims to restore normal operation of the device.

[Prior Art] FIG. 2 is a block diagram of a conventional semiconductor memory device that employs a plurality of random accessory memories each having a predetermined size of memory space as a memory unit (bank).

In the figure, (1) and (2) are banks that constitute one storage unit by grouping random accessory memories digit by digit as storage elements, and bank (2) is connected to the final output terminal n of the bank selection circuit (3). Each bank selection signal (9) indicating the final bank selected by the issued bank selection signal (9) is selected based on the address signal (5) outputted from a microprocessor (hereinafter abbreviated as CPU). It is output from the output terminal of the bank selection circuit (3). Also, (6) is data line information read from banks (1) and (2), and these data line information (6)
is sent to a failure detection circuit (7), and a predetermined detection method is used to detect whether or not an error exists in the information signal, and when an error is detected, an error signal (8) is issued to the CPU.

Note that (4) is an amplifier for shaping the waveform of each information signal.

The operation of a conventional semiconductor memory device with such a configuration will be explained.

When reading information from the storage space of a predetermined bank (1) (2), the upper address signal AH of the address signal (5) sent from the CPU (not shown) is sent to the amplifier (4).
) to the bank selection circuit (3). The bank selection circuit (3) sends a bank selection signal (9) to the bank (1) (2) corresponding to the upper address signal AH to select the bank (1) (2) and read out the stored information. possible.

After a predetermined bank (1) (2) is selected as described above, the information in the storage space is read out by the lower address signal AL of the address signal (5), and
- is sent out on the data line via (4). Also, the read information is sent to the failure detection circuit (7) and the bank (
1) The presence or absence of erroneous information caused by the failure of the storage element in (2) is detected.

At the time of this detection, an error signal (8) is sent from the failure detection circuit (7) to the CPU via the amplifier (4) at the time when erroneous information is detected.

As a result, it is determined that a failure has occurred in the memory element occupying a predetermined storage space in the CPU, and 42
Either stop the operation of the equipment, or stop the storage management or use of the failed storage space and continue the operation of the equipment.

However, since conventional semiconductor storage devices are configured as described above, the operation of the device may stop due to bank failure, or even if the device can be operated depending on the degree of bank failure, it may not be possible to use the device. Due to the presence of some failure-recorded TQ elements in the storage space, an unusable storage space is created, so the CPU has to bear an extra burden to manage the storage area, which reduces the operating efficiency of the device as a whole. However, there was a drawback that a decline in performance was unavoidable.

[Summary of the Invention] The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above. To provide an error recovery device for a semiconductor memory device that can provide a CPU with a continuous memory space free of defective memory spaces due to faulty memory elements by switching between banks.

[Embodiments of the Invention] An embodiment of an error recovery device for a semiconductor memory device according to the present invention will be described below with reference to FIG. In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and detailed descriptions thereof will be omitted.

In the figure, (10) stores an address signal when the error tij# signal is detected by the error signal (14) issued from the failure detection circuit (7), and also stores the address signal and the address signal at which the storage device is currently operating. (11) is a latch circuit that stores the fact that a failure has occurred in a predetermined storage space; (12) is a failure space storage register that detects the coincidence and mismatch between the failure product t! ! A selection signal gate circuit inhibits re-selection of the storage space where the element exists, and (13) is a storage space switching circuit that switches the storage space where the failed storage element exists to a specific storage space in the final bank (2). Nao (lla)
is a fault state holding signal that is output and held when the fault state is memorized by the latch circuit (11), and (14) is the fault detection circuit (7).
), and (15) is a selection prohibition signal that is output when the address signal stored by the failure space storage register (lO) and the input address signal match.

Next, the operation of this embodiment with the above configuration will be explained.

I will clarify. As in the prior art, a bank selection signal (9) is sent out from the bank selection circuit (3). The bank selection signal (9) is applied to the selection signal gate circuit (12), but at the beginning of operation of the storage device, the address signal (5) is applied to the selection signal gate circuit (12).
Since no failure has been detected from bank (1) corresponding to bank (1), bank selection signal (8) is sent to selection signal gate circuit (12).
is passed through and added to the bank ([). Then, the stored information is read out from the bank (1) digit by digit according to the lower address signal AL, and becomes data line information (6) through amplifiers (4) . . . (4).

At that time, the stored information is also added to the failure detection circuit (7). At this time, for example, if a storage element failure occurs in the O-th bank (1), a failure signal (14) is generated from the failure detection circuit (7), and the failure signal (11) causes
The corresponding address signal (
5) is written in the fault space storage register (lO).

In addition, the above fault signal (14) is connected to the latch circuit (1+
) outputs and holds the failure state holding signal (lla) at the "L" level. Furthermore, the fault signal (14) is transmitted to the amplifier (4)
An error signal (8) is generated through the 0th bank (1) to inform the CPU that a failure has occurred in the predetermined storage space of the 0th bank (1).

As a result, the CPU sends an address signal (5) to the storage device and attempts to write information again into the storage space where the failure occurred. However, in the failure space storage register (10), a match is detected between the address signal (5) representing the previously stored failure storage space and the address signal (5) of the storage space in which information is to be written again. Then, the "H" level selection prohibition signal (15) is sent to the fault space storage register (
lO) to the negative input terminal (12a) of the gate circuit (12), and the selection signal is applied to the negative input terminal (12a) of the gate circuit (12).
The bank selection circuit (3) is connected to the other input terminal (12b) of
Bank selection signal of H” level from the “0” terminal of (9)
is sent, the selection signal gate circuit becomes a negative logic, and selection of the rOJth bank (1) by the bank selection signal (9) is inhibited.

In addition, selection of bank (1) is inhibited by selection prohibition signal (15), while CE (C:I(IP
In the storage space switching circuit connected to the EN-△BLE) terminal, the selection signal (9) at the "H" level is applied to the input of the first OR circuit (13a) and the LAND circuit (13b). At the same time, the "H" level selection prohibition signal (15) is connected to the first AND circuit (llb
) is applied to the other input of As a result, a similar AND circuit (
13b) (7) The output is “H”.
An H” level signal is applied to the CE terminal of the final I bank (2) through the p 20 R circuit (13C), and the signal is applied to the CE terminal of the final I bank (2).
) will be selected. Information is written into the storage space of the last bank (2) according to the lower address signal AL.

Also, after the information is written to the last bank (2), the information is read or written to the faulty storage space of the O-th bank (1) according to the address signal (2) sent from the CPU. Similarly to the above, the storage space switching circuit (13) operates to switch to the last bank (2).
Information is read from or written to the storage space of. As a result, change the selection order of bank (1) (2)
This can be done without changing the contents of the address signal.

However, according to the address signal (5), finally @
When the last bank (2) is selected and the "H" level storage space selection signal (9) is output from the final output terminal n of the storage space selection circuit (3) to the second AND circuit (13d). Even if there is, the failure state holding signal (lla) at the "L" level is input to the second AND circuit (13d), so the second AND circuit (13d) becomes a negative logic. Further, the LAND circuit (13b) also becomes a negative logic because the other storage space selection signal (9) and selection inhibition signal (15) are not output. As a result, the output of the second OR circuit (13c) that receives the output signals of the first and second AND circuits is "L".
``level signal, the selection of the final bank (2) is inhibited, and the same content information is not read out again by the storage space selection signal (8) from the final output terminal n.

[Effects of the Invention] As described above, according to the error recovery device for a semiconductor memory device of the present invention, a read information error caused by a defective memory element of a semiconductor memory device is detected, and at the same time, a memory space in which a defective memory element exists is recovered from another memory. Since the configuration is such that switching is performed while the equipment is in operation, error recovery is possible without completely stopping equipment operation when error information is detected.
Since PU can use continuous storage space without considering unusable storage space due to defective storage elements, it has the effect of improving the operating efficiency of equipment using semiconductor storage devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an error recovery device for a semiconductor memory device according to the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor memory device. (1): Punk. (2): Final puncture, (3): Storage space selection circuit, (5) Near address signal. (7): Failure detection circuit. (8): Error signal, Ho): Fault space storage register, (+3): Storage space switching circuit, (+5): Storage space selection prohibition signal. In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1

Claims (1)

[Claims] A plurality of banks in which random access memories are grouped digit by digit as a storage element into one storage unit, a storage space selection circuit that selects a storage space for each bank based on an address signal sent from a microprocessor, and a failure detection circuit that detects the presence or absence of error information from stored information read from the storage space; and a failure detection circuit that stores an address signal at the time of error information detection based on the error signal from the failure detection circuit; A fault space storage register that detects a match or mismatch with the address signal on which the storage device is operating, a storage space selection prohibition signal that is sent out when a match is detected in the fault space storage register, and an address signal that is sent out when the error information is detected. 1. An error recovery device for a semiconductor storage device, comprising a storage space switching circuit for switching an error information reading storage space to another storage space.