JPS6149248A - High-speed writing system of pattern - Google Patents

Abstract

PURPOSE:To improve the data processing efficiency of the titled system by controlling an interruption control circuit according to the result of operations obtained from the initial values of a length counter and an address counter and therefore performing a writing action only when the specific conditions are satisfied. CONSTITUTION:An image pattern and a command are supplied to a pattern register 1 and a state control circuit 8 respectively from a host device via an input. The circuit 8 is started by a command, and the state of the image pattern stored in the register 1 is checked. In other words, the initial values of both a length counter 6 and an address counter 5 are read. Then a writing address is calculated from the writing start address of a bit map memory 3 and the length of data. Then the relation between the writing address and the boundary divided by the memory elements of the memory 3 is calculated. Based on the result of this calculation, a writing control circuit 7 is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for writing patterns into a bitmap memory that stores pattern data such as characters and images. The present invention relates to a high-speed pattern writing method that allows the pattern data to be written at high speed regardless of the writing end address.

With the spread of various information processing devices, information output devices that store character patterns sent from character generation circuits, image patterns given from host devices, etc. in bitmap memory, and read and display or print them. is used.

Since these information output devices are normally used by being connected to a computer system, there is a constant need to improve the data processing efficiency of each information output device in order to increase the processing efficiency of the entire system.

[Conventional technology]

Information output devices that display or print pattern data such as character patterns or image patterns temporarily store character patterns generated by a character generation circuit or image patterns given from a host device in a bitmap memory and then process them. )

When storing pattern data in this bitmap memory, conventionally only one dot of data could be written in one clock cycle of the device, and a plurality of dots could not be written simultaneously. This is because the data to be handled needs to be written in an arbitrary shape at an arbitrary address on the bitmap memory, so it is necessary to specify the addresses in the X and Y directions one dot at a time.

However, this has poor data processing efficiency, so the bitmap memory is composed of 21 storage element groups, and the data to be written matches the boundary of the bitmap memory divided for each storage element group, If you have a cut that allows groups to be written as enabled at the same time, for example n=
2, that is, 4 memory elements, and each memory element is designated as A and B.
,C.

If the data is written as D, then the data is written starting from A and ending with writing B, C, D, and the data is not structured such that writing starts from B or ends with C, then 2T1 bits are written. A high-speed writing method that writes every time is patented in 1982.
147784.

FIG. 5 is a block diagram of a high-speed write circuit based on the above proposal.

An image pattern is sent from the input to the pattern register 1, and a command is sent to the counter control circuit 4 from the host device. The counter control circuit 4 is activated by the command,
The end of the data to be written to the bitmap memory 3 is determined based on the initial value of the length counter 6, which indicates the length of the data, and the initial value of the address counter 5, which indicates the first address at which the data in the bitmap memory 3 is written. calculate.

The counter control circuit 4 uses the above calculation result to compare it with the above-mentioned condition under which each storage element can be enabled simultaneously, and determines whether high-speed writing is possible.

The pattern register 1 sends data to be written into the bitmap memory 3 to the data selection circuit 2 under the control of the counter control circuit 4. When the counter control circuit 4 determines that high-speed writing is possible, it controls the data selection circuit 2 to 1
Data to be written in a plurality of bits of the same number as the number of storage elements, for example, 4 bits in the case of n=2, is sent to the bitmap memory 3 in each clock cycle.

Further, the counter control circuit 4 controls the address counter 5 to send the upper address of the data write address of the bit map memory 3 excluding the lower n bits to the bit map memory 3. At the same time, the address counter 5
The write control circuit 7 sends out the lower n bits to the bitmap memory 3 under the control of the counter control circuit 4, and the write control circuit 7 sends out the lower n bits to the bitmap memory 3.
Enable the storage elements of f[lil at the same time.

When the length counter 6 sends a carry signal indicating the end of writing and detects that data writing for columns in the X direction has been completed, the counter control circuit 4 returns to its initial state and waits for the next command.

Because it operates as described above, the circuit shown in FIG. 5 can write an image pattern into the bitmap memory 3 at high speed under a specific condition in which the break in the write data exactly matches the boundary of the bitmap memory 3. .

[Problem that the invention seeks to solve]

As mentioned above, in the past, when writing a pattern to a bitmap memory, it was only possible to write one bit at a time or at high speed only when certain conditions were met, so the data processing efficiency of the information output device was reduced. The problem is that it is low.

[Means for solving problems]

The above problem is that when a bitmap memory is composed of 2M storage elements, the boundaries of the bitmap memory divided into 2T1 storage element groups are detected, and one line is written to the bitmap memory. From the data length and write start address, the number of write bits up to the first memory boundary, the last number of write bits from the memory boundary, and 2m.
A means for calculating the number of bits that can be written for each bit is provided,
The bits that can be written one by one are written to enable 2M storage elements at the same time, and the bits up to the first memory boundary and the bits after the last memory boundary are written to enable the corresponding storage elements at the same time. This problem is solved by the high-speed pattern writing method according to the present invention.

[Operation] Immediately, using the initial values of the length counter and address counter, calculates the relative position between the range of data to be written to the bitmap memory and the boundary demarcated for each storage element group, and determines the status based on the calculation result. , and controls the write control circuit to arbitrarily enable 2T1 storage elements and write data.

Corresponds to data that does not straddle a boundary with a bit count of zT1 or less, data that straddles or touches a boundary, data that spans multiple boundaries with a bit count of 2M or more, and data after a boundary that is 21 times the final one. The memory element is enabled depending on the state of the data, and data can be written in single, multiple, or 2M bits per clock cycle.

〔Example〕

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention.
Components having the same functions as those in FIG. 5 are represented by the same reference numerals.

An image pattern is input to the pattern register 1 and a command is input to the state control circuit 8 through input from a host device.

The state control circuit 8 is activated by the command and checks the state of the image pattern stored in the pattern register l. That is, the initial value of the length counter 6 and the initial value of the address counter 5 are read, the write end address is calculated from the write start address of the bitmap memory 3 and the length of the data, and the boundary between the storage elements of the bitmap memory 3 is calculated. Calculate the relationship between

FIG. 2 is a diagram explaining the operating principle of the state control circuit 8, FIG. 3 is a flowchart of the state control circuit 8, and FIG. 4 is a diagram explaining each state of the flowchart in FIG.

In FIG. 2, for example, it is assumed that the writing pattern has an arbitrary length from point E to point F. Let this length be L. Assume that the number of storage elements in the bitmap memory 3 at this time is, for example, n-2, that is, 4, and that they are separated by the positions shown by dotted lines.

Assuming that the memory elements are A, B, C, and D and are arranged regularly in this order, in this case, 78 points of data are written to memory element C, then the next point is written to D, and then A, B, C, and D are sequentially written one bit at a time, and the final data at point E is written to B, ending the process.

If the position where the first memory element A appears is G, then 2
This is the first multiple of 2, and if the position where the last memory element appears is H, then this is the last multiple of 22. Let the length from G to F be L''.

Here, point E is set as 22xa+t), and from here the length L=2
” Assume that a pattern of Xj?+m is written.

However, a, l≧0, O≦b≦(2”-1), 0≦m≦
(22-1), and the 0 point is 2"X(a+1), the H point is 2"(a+1)+2"Xp, and the E point is E+L=2
" The result is used to operate as shown in the flowchart of FIG.

First, check whether Lo is smaller than O. If it is small, it will look like the one shown in Figure 4+d)? Move to d. This state occurs when the length of the written pattern is 3 bits or less and data writing is completed within a range that does not reach point G in FIG.

In state d, the lower two bits b of the address sent from the address counter 5 to the bitmap memory 3 and the lower two bits m of the data length are bo, respectively.

When expressed as bl, mo, mI, bo, bl, mO
When ml is "0" and ml is "1", only the storage element A is enabled, and 1-bit data sent by the data selection circuit 2 is written into the bitmap memory 3.

Similarly, when bo and mo are "1" and bl and ml are "O",
Only memory element B is enabled, and bitmap memory 3
Write 1-bit data to b1, mO becomes “1”
", when bo and ml are "0", only write element C is enabled, 1-bit data is written, and bl, bo,
When mo is both "1" and ml is "0", only the storage element is enabled and 1-bit data is written into the bitmap memory 3.

Also, when bo, J, and mo are "0" and ml is 1", storage elements A and B are enabled, 2-bit data is written in the bitmap memory 3, and when bl, mO are "0", bo
, ml are "1", storage elements B and C are enabled and 2-bit data is written.

Furthermore, bl, bO, rno is “0” and ml is “1”.
'', storage elements A, B, and C are enabled, 3-bit data is written in the bitmap memory 3, and the initial state is returned.

If L' is larger than 0, the state shifts to state a shown in FIG. 4 ta+. This state is 2 points from point E at the beginning of data writing in Figure 2.
This is a case of writing forward data of the first multiple of 0 points of 2.

In state a, the lower two bits b sent from the address counter 5 to the bitmap memory 3 are bo.

Expressed by bl, when bl and bo are “0”, memory element A,
B, C, and D are enabled, and the 4-bit data sent by the data selection circuit 2 is written into the bitmap memory 3.

Similarly, when s is "0" and bo is "1", memory element B,
Enable C and D and write 3-bit data into the bitmap memory 3. When b is "1" and bO is "0", enable storage elements C and D and write 2-bit data, bl.

When both bO are “1”, the memory element is enabled,
Write 1-bit data and then check whether p is 0.

If p is O, then q 7! Check whether l< o, q is also O
If so, it is determined that the write data is now finished, and the process returns to the initial state.

If p is not 0, the state shifts to the state +a b shown in FIG. 2 fb). This state indicates that the data to be written is 4 consecutive bits, and data is stored 4 bits at a time until the length counter 6 sends out a carry signal. The state shifts to state C shown in FIG.

In state C, data after the last cut point H in FIG. 2 is written. If q of the lower two bits of L calculated by the state control circuit 8 is expressed as qO and qI, (when both 10 and Ql are 0, it means that there is no write data, and all memory elements are enabled. Bitmap memory 3
No data is written to.

When qI is "0" and qo is "1", only storage element A is enabled and 1-bit data sent from data selection circuit 2 is written into bitmap memory 3, and similarly Ql is "1".
1” and qO is “0”, write the data of 2 pins 1- with α elements A and B enabled, (when η and qO are both “1”, memory elements A, B, C is enabled, writes 3-bit data, and returns to the initial state.

If p is 0 and q is not 0, the process moves to state 9 and returns to the initial state after processing in the same manner as above. It can be shared, and the circuit can be constructed economically.Also, the present invention can be applied even if a character generation circuit is used in place of the pattern register 1.

〔Effect of the invention〕

As explained above, when writing an image pattern to a bitmap memory, the present invention writes data in 2T1 bits every clock cycle for each boundary of a storage area determined by the number of storage elements, and also writes data for other areas. Since target bits can be written at once in one clock cycle, patterns can be written at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, FIG. 2 is a diagram explaining the operating principle of the state control circuit 8, and FIG.
FIG. 4 is a flowchart of the state control circuit 8, FIG. 4 is a diagram explaining each state of the flowchart of FIG. 3, and FIG. 5 is a block diagram of a conventional high-speed write circuit. In the figure, 1 is a pattern register, 2 is a data selection circuit, 3 is a bitmap memory, 4 is a counter control circuit, 5 is an address counter, 6 is a length counter, 7 is a write control circuit, and 8 is a state control circuit. . Shino 2 Mouth 3 Zuryo 40 (A)

Claims (1)

[Claims] In a device for writing pattern data into a bitmap memory, when the bitmap memory is composed of 2^η storage elements, detecting boundaries of the bitmap memory divided into groups of 2^η storage elements. Then, from the data length of one line to be written to the bitmap memory and the write start address, the number of write bits up to the first memory boundary, the last number of write bits from the memory boundary, and 2^η
A means for calculating the number of bits that can be written for each bit is provided,
The bits that can be written every ^η enable and write 2^η storage elements at the same time, and the bits up to the first memory boundary and the bits after the last memory boundary enable the corresponding storage elements at the same time. A high-speed pattern writing method characterized by writing as follows.