JPS6148962A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6148962A JPS6148962A JP17069684A JP17069684A JPS6148962A JP S6148962 A JPS6148962 A JP S6148962A JP 17069684 A JP17069684 A JP 17069684A JP 17069684 A JP17069684 A JP 17069684A JP S6148962 A JPS6148962 A JP S6148962A
- Authority
- JP
- Japan
- Prior art keywords
- resistors
- resistor
- resistance elements
- central axis
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000002146 bilateral effect Effects 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路装置、詳しくは、精密な基準
電圧発生回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a precision reference voltage generation circuit device.
従来例の構成とその問題点
基準電圧発生回路装置の一般的な回路として、バンドギ
ャップ型基準電圧回路がよく知られている。第１図はこ
のようなバンドギャップ型基準電圧回路の一例を示す。2. Description of the Related Art Configuration and Problems Thereof A bandgap reference voltage circuit is well known as a general circuit of a reference voltage generating circuit device. FIG. 1 shows an example of such a bandgap reference voltage circuit.
図中１．２．３はＮＰＮ ）ランジスタ、４，５，６．
７は抵抗、８は基準電圧出力端子、９はこの回路への電
流源である。In the figure, 1.2.3 are NPN) transistors, 4, 5, 6.
7 is a resistor, 8 is a reference voltage output terminal, and 9 is a current source for this circuit.
この回路において、温度補償された基準電圧ｖ、ＩＫ、
を得るために、異なる電流密度で動作しているトランジ
スタ１，２のベース−エミッタ間電圧差、つまり抵抗６
の両端電圧Δｖ８８の正の温度係数が、各トランジスタ
１．２ｔ：ＩＭ）ベース−エミッタ間電圧ＶＢＩ＋の負
の温度係数に加えられて打ち消し合っている。In this circuit, the temperature compensated reference voltage v, IK,
In order to obtain
The positive temperature coefficient of the voltage Δv88 across each transistor is added to the negative temperature coefficient of the base-emitter voltage VBI+ of each transistor 1.2t:IM) and cancel each other out.
ここで、トランジスタ１とトランジスタ２のエミツタ面
積比を１：２とし、トランジスタ１，２゜３のベース電
流を無視すると、出力端子８に現われる基準電圧ｖＲｘ
Ｆは次式で与えられる。ただし、Ｒ（４）〜Ｒ（７）は
抵抗４〜７の各抵抗値である。Here, if the emitter area ratio of transistor 1 and transistor 2 is 1:2 and the base currents of transistors 1 and 2 are ignored, the reference voltage vRx appearing at output terminal 8
F is given by the following equation. However, R(4) to R(7) are respective resistance values of resistors 4 to 7.
ゆえに
この関係式かられかるように、抵抗比Ｒ（５） ：Ｒ（
４）、Ｒ（７） ：Ｒ（ｅ） 、 （Ｒ（５）＋Ｒ（７
））／Ｒ（６） を選ぶことによって低電圧で温度保
償された基準電圧ｖｎｘｙが得られる。また式（２）の
両辺を温度Ｔで微分すると回路全体の温度係数が求まる
。Therefore, as can be seen from this relational expression, the resistance ratio R(5) :R(
4), R(7) :R(e), (R(5)+R(7
))/R(6) A low voltage and temperature guaranteed reference voltage vnxy can be obtained. Further, by differentiating both sides of equation (2) with respect to temperature T, the temperature coefficient of the entire circuit can be found.
さらに、ここで各トランジスタの特性がすべて等しいと
設定すると、この回路は、式（２）かられかる通り、基
準電圧値精度が各抵抗間の相対精度で決定される。した
がって、この相対精度を確保すれば、基準電圧値精度の
向上につながる。半導体集積回路における抵抗の相対精
度を悪化させる原因としては、ホトレジストのマスク合
せ誤差、エツチングのバラツキ、および拡散のバラツキ
があり、これらの影響をさけるためには、一般的に、抵
抗の幅をそろえる、コンタクトの形状や抵抗の方向を合
せる、近接して配置するなどの方策をとる必要がある。Furthermore, if the characteristics of each transistor are all set to be equal, the accuracy of the reference voltage value in this circuit is determined by the relative accuracy between the respective resistors, as can be seen from equation (2). Therefore, ensuring this relative accuracy will lead to an improvement in the accuracy of the reference voltage value. Causes of deterioration of the relative accuracy of resistors in semiconductor integrated circuits include photoresist mask alignment errors, etching variations, and diffusion variations.To avoid these effects, it is generally necessary to make the resistor widths the same. , it is necessary to take measures such as matching the shape of the contacts and the direction of the resistors, and arranging them close to each other.
しかしながら、一般的にバンドギャップ型基準電圧回路
は各抵抗の抵抗比が大きく、とりわけ、各抵抗を単一素
子で構成した場合、前記の相対精度向上のための対策が
非常に困難となり、各抵抗の抵抗比が大きくずれる。仮
りに、抵抗Ｒ（６）のみが他の抵抗に対し＋０．５％の
誤差が出た場合、式（２）で基準電圧の変動を求めると
約＋０．４％の誤差が発生する、また、発熱の大きい素
子の影響でＲ（５）が他の抵抗より＋１°Ｃ温度差が生
じた場合、抵抗の温度係数が２２００ ｐＩ）ｍとして
約＋ｏ、２％基準電圧がずれる。さらに上記の各条件が
重って発生した場合、約＋０．６％の誤差が生じること
になる。このため、発熱の大きい素子を含んだ精密な基
準電圧発生回路装置を構成する場合、ノ（ンドギャノプ
型基準電圧回路の各抵抗の抵抗比が大きいため、通常の
素子配置では、第１に、各抵抗間の相対精度が確保でき
ない。第２に、各抵抗間の抵抗変化率を合せることがで
きないという２つの不都合があった。However, in general, band gap type reference voltage circuits have a large resistance ratio of each resistor, and in particular, when each resistor is configured with a single element, it becomes extremely difficult to take measures to improve relative accuracy, and each resistor The resistance ratio varies greatly. If only the resistor R (6) has an error of +0.5% compared to the other resistors, if the fluctuation of the reference voltage is calculated using equation (2), an error of approximately +0.4% will occur. If R(5) has a temperature difference of +1°C from other resistors due to the influence of an element that generates a large amount of heat, the reference voltage will shift by about +o and 2% assuming that the temperature coefficient of the resistance is 2200 pI)m. Furthermore, if the above conditions occur together, an error of approximately +0.6% will occur. For this reason, when configuring a precision reference voltage generation circuit device that includes elements that generate a large amount of heat, firstly, each The relative accuracy between the resistors cannot be ensured.Secondly, there are two disadvantages: the rate of change in resistance between the resistors cannot be matched.
発明の目的
本発明は、上記の不都合を克服した精密な基準電圧発生
回路を構成することの可能な半導体集積回路装置を提供
する目的を有する。OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device capable of configuring a precise reference voltage generation circuit that overcomes the above-mentioned disadvantages.
発明の構成
本発明は上記目的を達成するために、半導体基板上に同
一形状の基本抵抗素子を複数個、発熱の大きい素子の中
心軸に対し対称的に配置し、回路用抵抗体の各々を前記
基本抵抗素子整数個から構成し、前記発熱の大きい素子
による半導体基板内の温度差に対し、前記回路用抵抗体
の抵抗変化率が互いに等しくなるように前記各抵抗体を
構成する前記基本抵抗素子を配列し、発熱の大きい素子
の中心軸に対し左右対称となるように構成した半導体集
積回路装置であり、これにより各抵抗体間の相対精度の
向上と等温度係数化を図った精密な基準電圧発生回路装
置を構成できる。Structure of the Invention In order to achieve the above object, the present invention arranges a plurality of basic resistance elements of the same shape on a semiconductor substrate symmetrically with respect to the central axis of the element that generates a large amount of heat, and each of the circuit resistors The basic resistor is composed of an integer number of basic resistance elements, and each of the circuit resistors is configured such that the resistance change rate of the circuit resistor is equal to each other with respect to a temperature difference in the semiconductor substrate caused by the element that generates a large amount of heat. It is a semiconductor integrated circuit device in which elements are arranged so that they are symmetrical with respect to the center axis of the elements that generate a large amount of heat. A reference voltage generation circuit device can be configured.
実施例の説明
以下各図に示す一実施例を参照しながら、本発明の詳細
な説明する。DESCRIPTION OF EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in each figure.
まず、半導体基板上に同一形状・同一゛方向・同一抵抗
値の基本抵抗素子を前記基板の中心軸に対し平行に多数
個作り込む。この基本抵抗素子は、抵抗の精度を悪化さ
せる数々の原因からの影響をほぼ排除して、相互には、
非常に優れた相対精度を有している。ゆえに、この基本
抵抗素子の抵抗値を、回路上で要求される各抵抗要素の
抵抗値に組合わせて利用可能な最小単位の抵抗値に設定
しておけば、たとえば、第５図のように、この基本抵抗
素子で、４，５，６．７の４個の合成抵抗体を構成する
ことにより、相対精度の優れた４個の抵抗体を構成でき
ることになる。First, a large number of basic resistance elements having the same shape, direction, and resistance value are fabricated on a semiconductor substrate in parallel to the central axis of the substrate. This basic resistance element almost eliminates the effects of many causes that degrade resistance accuracy, and
It has very good relative accuracy. Therefore, if the resistance value of this basic resistance element is set to the minimum available resistance value by combining the resistance value of each resistance element required on the circuit, for example, as shown in Figure 5, By constructing four composite resistors of 4, 5, and 6.7 using these basic resistance elements, four resistors with excellent relative precision can be constructed.
次に、４個の抵抗体の温度補償方策についてのべる。Next, we will discuss temperature compensation measures for the four resistors.
半導体基板内において４個の抵抗体Ｒ（４）〜Ｒ（７）
の各抵抗体間の抵抗変化率が等しくなるように各抵抗体
を構成するには、各基本抵抗素子の配列から、その組合
せを選諒択して、組み換えることが必要である。第３図
は本発明実施例の平面図である。各々の基本抵抗素子の
中心を結ぶ線に垂直な中心線１０を発熱の大きい素子の
中心軸と一致させ、かつ半導体基板の中心軸とも一致さ
せる。この結果、半導体基板内では、この中心軸に対し
、等温度線が左右対称となり、各抵抗体間の抵抗変化率
を等しくするだめの基本抵抗素子の配列も同じく前記中
心軸に対し左右対称とすることで等抵抗変化率の配列と
なるように容易に選択可能にしている。第３図では、４
個の抵抗体を基本抵抗素子の配列から選択して結線をな
したものを示す。Four resistors R(4) to R(7) in the semiconductor substrate
In order to configure each resistor so that the rate of change in resistance between each resistor is equal, it is necessary to select and rearrange the combinations from the arrangement of each basic resistance element. FIG. 3 is a plan view of an embodiment of the present invention. A center line 10 perpendicular to a line connecting the centers of each basic resistance element is made to coincide with the central axis of the element that generates a large amount of heat, and also to coincide with the central axis of the semiconductor substrate. As a result, within the semiconductor substrate, the isotemperature lines are symmetrical about this central axis, and the arrangement of the basic resistance elements that equalize the rate of change in resistance between each resistor is also symmetrical about the central axis. By doing so, it is possible to easily select an array having an equal resistance change rate. In Figure 3, 4
This figure shows how resistors are selected from the array of basic resistance elements and connected.
図では２６個の基本抵抗素子が中心線１０の両側に分割
して対称的に配列して構成され、各々の基本抵抗素子が
第２図示の各抵抗要素４〜７に対応して結線されている
。In the figure, 26 basic resistance elements are divided and arranged symmetrically on both sides of the center line 10, and each basic resistance element is connected corresponding to each resistance element 4 to 7 shown in the second figure. There is.
前記配列構成を行えば、個々の基本抵抗素子の抵抗変化
率は違っても、この基本抵抗素子で構成された４個の抵
抗体間の抵抗変化率が等しくできる。By performing the above arrangement, even if the resistance change rates of the individual basic resistance elements are different, the resistance change rates among the four resistors made up of these basic resistance elements can be made equal.
なお、説明の便宜上、本発明の一実施例として第１図の
回路構成を例示したがこれに限定されるものではない。For convenience of explanation, the circuit configuration of FIG. 1 is illustrated as an example of the present invention, but the present invention is not limited to this.
また、各抵抗間の相対精度や等抵抗変化率係数を要求さ
れる回路であれば、第１図に例示したバンドギャップ型
基準電圧回路以外の回路の場合でもよいことは当然でち
る。Further, as long as the circuit requires relative precision between each resistor and constant resistance change rate coefficient, it goes without saying that a circuit other than the band gap type reference voltage circuit illustrated in FIG. 1 may be used.
発明の効果
以上のように本発明によれば、発熱の大きい素子を含ん
だ抵抗体の相対精度が要求される半導体集積回路装置に
おいて、各抵抗体間における抵抗値の相対精度がとれ、
その各抵抗体を発熱の大きい素子による悪影響をうけず
に回路を動作させることが可能となり、たとえば基準電
圧発生回路へ本発明による配置構成を採用すれば、基準
電圧値のバラツキが小さくなり、歩留の向上が達せられ
、その利用価値は太きい。また、精密な基準電圧発生回
路装置の構成が可能で、その工業的価値は大きい。Effects of the Invention As described above, according to the present invention, in a semiconductor integrated circuit device that requires relative accuracy of a resistor including an element that generates a large amount of heat, the relative accuracy of the resistance value between each resistor can be obtained.
It is possible to operate the circuit without the resistor being adversely affected by the elements that generate a large amount of heat. For example, if the arrangement according to the present invention is adopted in the reference voltage generation circuit, the variation in the reference voltage value will be reduced, and the The improvement in retention has been achieved, and its utility value is significant. Furthermore, it is possible to construct a precise reference voltage generating circuit device, and its industrial value is great.
第１図は代表的なバンドギャップ型基準電圧回路図、第
２図は本発明の一実施例にかかるバンドギャップ型基準
電圧回路の抵抗構成図、第３図は本発明の一実施例半導
体装置における各抵抗体を構成する基本抵抗素子の配列
を示す平面図である。
１〜３・・・・・・トランジスタ、４〜７・・・・・・
抵抗、８・・・・・・基準電圧出力端子、９・・・・・
・電流源、１０・・・・・・中心線（軸）。FIG. 1 is a typical bandgap reference voltage circuit diagram, FIG. 2 is a resistance configuration diagram of a bandgap reference voltage circuit according to an embodiment of the present invention, and FIG. 3 is a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing an arrangement of basic resistance elements constituting each resistor in FIG. 1-3...transistor, 4-7...
Resistor, 8...Reference voltage output terminal, 9...
・Current source, 10...Center line (axis).
Claims (1)
の大きい素子の中心軸に対し対称的に配置し、回路用抵
抗体の各々を前記基本抵抗素子整数個から構成し、前記
発熱の大きい素子による半導体基板内の温度差に対し、
前記回路用抵抗体の抵抗変化率が互いに等しくなるよう
に前記各抵抗体を構成する前記基本抵抗素子を配列した
ことを特徴とする半導体集積回路装置。A plurality of basic resistance elements of the same shape are arranged on a semiconductor substrate symmetrically with respect to the central axis of the element that generates a large amount of heat, and each of the circuit resistors is composed of an integral number of the basic resistance elements, and Due to the temperature difference within the semiconductor substrate due to the element,
A semiconductor integrated circuit device, characterized in that the basic resistance elements constituting each of the resistors are arranged so that the resistance change rates of the circuit resistors are equal to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17069684A JPS6148962A (en) | 1984-08-16 | 1984-08-16 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17069684A JPS6148962A (en) | 1984-08-16 | 1984-08-16 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6148962A true JPS6148962A (en) | 1986-03-10 |
Family
ID=15909700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17069684A Pending JPS6148962A (en) | 1984-08-16 | 1984-08-16 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148962A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009517577A (en) * | 2005-11-29 | 2009-04-30 | ユーエフアイ フイルターズ ソチエタ ペル アチオーニ | Air filtration system directed to the intake of an internal combustion engine |
| JP2012238739A (en) * | 2011-05-12 | 2012-12-06 | Fujitsu Semiconductor Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58171843A (en) * | 1982-04-02 | 1983-10-08 | Nec Corp | Semiconductor integrated circuit device |
-
1984
- 1984-08-16 JP JP17069684A patent/JPS6148962A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58171843A (en) * | 1982-04-02 | 1983-10-08 | Nec Corp | Semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009517577A (en) * | 2005-11-29 | 2009-04-30 | ユーエフアイ フイルターズ ソチエタ ペル アチオーニ | Air filtration system directed to the intake of an internal combustion engine |
| JP2012238739A (en) * | 2011-05-12 | 2012-12-06 | Fujitsu Semiconductor Ltd | Semiconductor device |
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