JPS6148961A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6148961A JPS6148961A JP17088584A JP17088584A JPS6148961A JP S6148961 A JPS6148961 A JP S6148961A JP 17088584 A JP17088584 A JP 17088584A JP 17088584 A JP17088584 A JP 17088584A JP S6148961 A JPS6148961 A JP S6148961A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- semiconductor
- polycrystalline
- oxide film
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 30
- 238000002844 melting Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 description 7
- 230000008018 melting Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置に関し、特に多結晶半導体で形成さ
れた抵抗体の接続構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a connection structure for a resistor formed of a polycrystalline semiconductor.
（従来の技術）
最近の半導体装置は大集積化及び低消費電力化の為の高
速化の要求がますますはげしくなってきている。抵抗体
としても従来の拡散法による接合を有する抵抗体は接合
容量を有する為、低速であるという理由から多結晶シリ
コンを使用し次接合容量を持たない抵抗体が増加して込
る。又ＭＯＳ型の場合は、シリコンゲートが主ｆｉ？占
め増々多結晶シリコン使用が多くなってきている。更に
高集積化全実現する為に多結晶シリコン抵抗自体の微細
化の要求がはげしくなってきている。(Prior Art) Recent semiconductor devices are increasingly required to have higher speeds for higher integration and lower power consumption. As a resistor, a resistor having a junction made by the conventional diffusion method has a junction capacitance, and because of its low speed, the number of resistors using polycrystalline silicon and having no junction capacitance is increasing. Also, in the case of MOS type, the silicon gate is the main fi? Polycrystalline silicon is increasingly being used. Furthermore, in order to achieve higher integration, there is an increasing demand for miniaturization of the polycrystalline silicon resistor itself.
第２図に従来の実施例の平面図と断面図を示す。FIG. 2 shows a plan view and a sectional view of a conventional embodiment.
１０１はシリコン基板、１０２は酸化膜、１０３゜１０
３’ 、１０５，１０５’は多結晶シリコン。101 is a silicon substrate, 102 is an oxide film, 103°10
3', 105, and 105' are polycrystalline silicon.
１０４．１０６は酸化膜、１０７拡接続用開ロ窓。104.106 is an oxide film, 107 is an open window for expansion connection.
１０８はアルミニウムの配線金示す。その製造方法はシ
リコン基板１０１上に酸化膜１０２ｔ−成長した後、第
１の多結晶シリコン１０３，１０３’を成長し、ドライ
エツチングによりパターンを形成した後、酸化膜を成長
し１表面全体を異方性ドライエ、チングにより選択腐蝕
してやると側面に酸化膜１０４が残る。更に第２の多結
晶シリコンを成長しｔ後、レジスト等で表面を平担化し
て再変異方性ドライエツチングで第１の多結晶シリコン
の上部のＷＩ２の多結晶シリコンを取フ去ってやると第
２の多結晶シリコン１０５．１０５’が第１の多結晶シ
リコン１０３，１０３’ と同一平面で残る。その後、
表面に酸化膜１０６を配して接続用の窓１０７’に開け
、アルミニウムの配線１０８で接続してやると１部分的
に接続された多結晶シリコンによる抵抗体が出来る。Reference numeral 108 indicates an aluminum wire. The manufacturing method is to grow an oxide film 102t on a silicon substrate 101, grow first polycrystalline silicon 103, 103', form a pattern by dry etching, and then grow an oxide film to cover the entire surface. When selective etching is carried out by directional drying and etching, an oxide film 104 remains on the side surfaces. Furthermore, after growing the second polycrystalline silicon, the surface is flattened with a resist or the like, and the polycrystalline silicon of WI2 above the first polycrystalline silicon is removed by retransformation dry etching. The second polycrystalline silicon 105, 105' remains coplanar with the first polycrystalline silicon 103, 103'. after that,
An oxide film 106 is placed on the surface, a connection window 107' is formed, and a connection is made with aluminum wiring 108, thereby creating a partially connected polycrystalline silicon resistor.
（発明が解決しようとする問題点）
かかる従来の構造では、側面に異方性ドライエツチング
により残された酸化膜を介して第１．第２の多結晶シリ
コンは接しているので自己整合しており、高集積化を相
当程度実現してはいるが、第１１第２の多結晶シリコン
を接続する為にコンタクト窓とアルミニウムの配線を必
要とする為にその部分の面積が大きくなる事と、配線の
自由度が少なくなるという欠点がある。(Problems to be Solved by the Invention) In such a conventional structure, the first oxide film is etched on the side surface through an oxide film left by anisotropic dry etching. Since the second polycrystalline silicon is in contact with each other, it is self-aligned, and a high degree of integration has been achieved. This has the disadvantage that the area of that part becomes large because it is necessary, and that the degree of freedom in wiring is reduced.
本発明の目的はかかる従来の欠点を改善し、更に高集積
度で、配線の自由度のある多結晶抵抗体を提供するもの
である。SUMMARY OF THE INVENTION An object of the present invention is to improve these conventional drawbacks and to provide a polycrystalline resistor with a higher degree of integration and a greater degree of freedom in wiring.
〔問題点を解決するための手段〕
かかる目的を達成する為に、本発明によれば、多結晶シ
リコンどうしの接合部の下部に高融点金属を有し、この
高融点金属で多結晶シリコンどうしの電気的接読ヲとっ
た半導体装置を得る。[Means for Solving the Problems] In order to achieve the above object, the present invention has a high melting point metal at the lower part of the joint between polycrystalline silicon, and the high melting point metal is used to bond the polycrystalline silicon to each other. A semiconductor device is obtained which has an electrical connection.
（実施例） 以下１図面上用いて本発明をより詳細に説明する。(Example) The present invention will be explained in more detail below with reference to one drawing.
第１図ｆａｌ、 （ｂ）はそれぞれ本発明の一実施例の
平面図と断面図を示したものである。すなわち、シリコ
ン基板２０１上に酸化膜２０２を約１００００Ａ熱酸化
又はＣＶＤ法にエフ形成する。次にモリブデンやタング
ステン等の高融点金属を約１００ ＯＡ付けた後写真蝕
刻技術とドライエツチング技術にエフ必要な部分にのみ
高融点金属２０３を残す。FIGS. 1(b) and 1(b) respectively show a plan view and a sectional view of an embodiment of the present invention. That is, an oxide film 202 is formed on a silicon substrate 201 using a thermal oxidation method or a CVD method of about 10,000 Å. Next, after applying a high melting point metal such as molybdenum or tungsten at a thickness of about 100 OA, the high melting point metal 203 is left only in the areas necessary for photolithography and dry etching.
次に第１の多結晶シリコン１２０００〜６０００Ａ成長
し、写真蝕刻技術金選択工、チングに：す、第１の多結
晶シリコン抵抗領域２０４，２０４’ ｋ形成し１表面
にＣＶＤ法により酸化膜全成長し。Next, a first polycrystalline silicon layer 12000 to 6000A is grown, and then a photolithography process is performed to form a first polycrystalline silicon resistance region 204, 204'k. Grow.
表面全体を異方性ドライエ、チングにより選択腐食する
と側面に酸化膜２０５が残る。この時ドライエツチング
用のガスは、下表の高融点金属２０３と酸化膜で充分に
選択比が得られるように選ぶ。When the entire surface is selectively etched by anisotropic dry etching, an oxide film 205 remains on the side surfaces. At this time, the gas for dry etching is selected so as to obtain a sufficient selection ratio between the high melting point metal 203 and the oxide film shown in the table below.
次に第２の多結晶シリコンを成長し１表面をレジスト等
で平担化した後、異方性ドライエツチングで選択腐食し
てやると、第１多結晶−シリコン２０４′上部の第２多
結晶シリコンのみが除去され、第２の多結晶抵抗体２０
６が形成される。Next, after growing a second polycrystalline silicon and planarizing one surface with a resist or the like, selective etching is performed by anisotropic dry etching. is removed, and the second polycrystalline resistor 20
6 is formed.
このように、高融点金属を第１．第２の多結晶シＩＪコ
ン２０４’、２０６に接するように部分的に残しておけ
ば、第１．第２の多結晶シリコン２０４’。In this way, the high melting point metal is placed first. If a portion is left in contact with the second polycrystalline silicon IJ 204', 206, the first. Second polycrystalline silicon 204'.
２０６は自己整合的に部分的に接し、かつ他の部分は側
面の酸化膜で絶縁された抵抗体として形成する事が出来
る。206 can be formed as a resistor that partially contacts in a self-aligned manner and other parts are insulated by an oxide film on the side surface.
（発明の効果）
以上述べた構造の本発明の半導体装置は、下に埋め込ま
れて成る高融点金属により、第１．第２の多結晶シリコ
ン抵抗体′ｔ−電気的に接続しているので、この上を絶
縁膜を介してアルミニウム等の配線を自由に引き廻す事
が出来る。また、これら第１．第２の多結晶シリコン抵
抗体同士を接続するためのコンタクト窓を開ける必要が
無い為に、無駄な面積全必要としない。更に、第１．第
２多結晶シリコンの上面で高融点金属で接続しようとす
る場合、酸化膜が介在するとどうしても１回の７中トレ
ジスト工程分余分に工程ががかるが１本発明によればこ
のような工程も必要としない。このように１本発明は多
結晶シリコン抵抗体の高密度実装に非常に優れた装置で
あると言える。(Effects of the Invention) The semiconductor device of the present invention having the above-described structure has the structure shown in FIG. Since it is electrically connected to the second polycrystalline silicon resistor 't, wiring made of aluminum or the like can be freely routed over it via an insulating film. Also, these first. Since there is no need to open a contact window for connecting the second polycrystalline silicon resistors, no unnecessary area is required. Furthermore, the first. When attempting to connect with a high-melting point metal on the upper surface of the second polycrystalline silicon, if an oxide film is present, an extra process is required for one 7-millimeter resist process, but according to the present invention, such a process is also necessary. I don't. In this way, it can be said that the present invention is an extremely excellent device for high-density packaging of polycrystalline silicon resistors.
本発明の実施例に於（八て、第１．第２の多結晶シリコ
ンの導電型はＰ型でもＮ型でも自由であるし、第１．第
２の多結晶シリコンは部分的に基板２０１に接していて
も良い事は勿論である。In the embodiment of the present invention, the conductivity type of the first and second polycrystalline silicons is free to be P type or N type, and the first and second polycrystalline silicon is partially connected to the substrate 201. Of course, it is okay to be in contact with
第１図（ａ）、 （ｂ）は本発明の一実施例を示す平面
図および断面図である。
８ｇ２図ｆａｎ、 （ｂｌはそれぞれ従来の多結晶シリ
コン抵抗体の接続構造を示す平面図および断面図である
。
１０１・・・・・・シリコン基板、１０２・・・・・・
酸化膜、１０３． １０３’・・・・・・第１の多結晶
シリコン。
１０４・・・・・・側面酸化膜、１０５，１０５’・川
・・第２の多結晶シリコン、１０６・・・・・・酸化膜
、１０７・・・・・・コンタクト用開口窓、１０８・山
・・アルミニウムの配線、２０１・・・・・・シリコン
基板、２ｏ２・川・・酸化膜、２０３・・・・・・高融
点金属、２０４，２０４’・・・・・・第１の多結晶シ
リコン、２ｏ５・川・・側面酸化膜、２０６・・・・・
・第２の多結晶シリコン。
ギ１ 回Ｃ０−）
享１図び）FIGS. 1(a) and 1(b) are a plan view and a sectional view showing an embodiment of the present invention. Figure 8g2 (bl is a plan view and a cross-sectional view showing the connection structure of a conventional polycrystalline silicon resistor, respectively. 101...Silicon substrate, 102......
Oxide film, 103. 103'...First polycrystalline silicon. 104... Side oxide film, 105, 105' River... Second polycrystalline silicon, 106... Oxide film, 107... Opening window for contact, 108... Mountain: Aluminum wiring, 201: Silicon substrate, 2o2: River: Oxide film, 203: High melting point metal, 204, 204': First multilayer Crystalline silicon, 2o5・river・side oxide film, 206・・・・
-Second polycrystalline silicon. GI 1 times C0-) Kyou 1 diagram)
Claims (1)
体とを有し、これら第一および第二の多結晶半導体とが
接する部分の下にはこれら第一及び第二の多結晶半導体
を電気的に接続する金属を有することを特徴とする半導
体装置。A first polycrystalline semiconductor and a second polycrystalline semiconductor are provided on a semiconductor substrate, and the first and second polycrystalline semiconductors are provided below a portion where these first and second polycrystalline semiconductors are in contact with each other. A semiconductor device characterized by having a metal that electrically connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17088584A JPS6148961A (en) | 1984-08-16 | 1984-08-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17088584A JPS6148961A (en) | 1984-08-16 | 1984-08-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6148961A true JPS6148961A (en) | 1986-03-10 |
Family
ID=15913116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17088584A Pending JPS6148961A (en) | 1984-08-16 | 1984-08-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148961A (en) |
-
1984
- 1984-08-16 JP JP17088584A patent/JPS6148961A/en active Pending
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